summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2016-02-22drm/i915/gen9: Extend dmc debug mask to include coresMika Kuoppala1-0/+1
2016-02-15drm/i915: Fix hpd live status bits for g4xVille Syrjälä1-7/+8
2016-02-10drm/i915: Handle PipeC fused off on IVB/HSW/BDWGabriel Feceoru1-0/+1
2016-02-10drm/i915/skl: Fix typo in DPLL_CFGCR1 definitionLyude1-1/+1
2016-02-06drm/i915/bxt: Check BIOS RC6 setup before enabling RC6Sagar Arun Kamble1-0/+11
2016-02-04drm/i915: Extend gpio read/write to other coresDeepak M1-0/+2
2016-02-04drm/i915/vlv: drop unused vlv_gps_core_read/write functionsJani Nikula1-1/+0
2016-02-04drm/i915: put the IOSF port defines in numerical orderJani Nikula1-5/+5
2016-02-04drm/i915: implement WaIncreaseDefaultTLBEntriesTim Gore1-0/+7
2016-02-02drm/i915/skl/kbl: Add support for pipe fusingPatrik Jakobsson1-0/+3
2016-01-25drm/i915/skl: Enable Per context Preemption granularity controlArun Siluvery1-0/+3
2016-01-25drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 to HW whitelistArun Siluvery1-0/+1
2016-01-25drm/i915/gen9: Add HDC_CHICKEN1 to HW whitelistArun Siluvery1-0/+2
2016-01-25drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelistArun Siluvery1-0/+2
2016-01-25drm/i915/gen9: Add framework to whitelist specific GPU registersArun Siluvery1-0/+3
2016-01-18Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queuedDaniel Vetter1-24/+24
2016-01-08drm/i915: Add non claimed mmio checking for vlv/chvMika Kuoppala1-0/+5
2015-12-23Merge tag 'drm-intel-next-2015-12-18' of git://anongit.freedesktop.org/drm-in...Dave Airlie1-3/+3
2015-12-15drm/doc: Convert to markdownDanilo Cesar Lemes de Paula1-24/+24
2015-12-11drm/i915: dual link pipe selection for bxtDeepak M1-3/+1
2015-12-08drm/i915: Disable CLKOUT_DP bending on LPT/WPT as neededVille Syrjälä1-0/+2
2015-12-04drm/i915: Correct the Ref clock value for BXTDeepak M1-1/+1
2015-12-02drm/i915: Don't register the CRT connector when it's fused off on LPT-HVille Syrjälä1-0/+1
2015-12-02drm/i915/bxt: backlight clock gating workaroundImre Deak1-0/+7
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä1-1262/+1210
2015-11-18drm/i915: Add missing ')' to SKL_PS_ECC_STAT defineVille Syrjälä1-1/+1
2015-11-18drm/i915: Give names to more ring registersVille Syrjälä1-0/+8
2015-11-18drm/i915: Make the cmd parser 64bit regs explicitVille Syrjälä1-2/+18
2015-11-18drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctlVille Syrjälä1-1/+2
2015-11-18drm/i915: Parametrize MOCS registersVille Syrjälä1-6/+6
2015-11-18drm/i915: Parametrize L3 error registersVille Syrjälä1-4/+2
2015-11-18drm/i915: Prefix raw register defines with underscoreVille Syrjälä1-131/+131
2015-11-17drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson1-0/+1
2015-11-17drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson1-0/+4
2015-11-17drm/i915/gen9: simplify DC toggling codeImre Deak1-0/+1
2015-11-17drm/i915: fix the power well ID for always on wellsImre Deak1-1/+3
2015-11-16drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä1-7/+8
2015-11-16drm/i915: Remove the magic AUX_CTL is at DP + foo tricksVille Syrjälä1-27/+27
2015-11-16drm/i915: Parametrize AUX registersVille Syrjälä1-50/+52
2015-11-10drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä1-1/+1
2015-11-09drm/i915: Add csr programming registers to dmc debugfs entryMika Kuoppala1-0/+10
2015-11-09drm/i915/bxt: Expose DC5 entry countMika Kuoppala1-0/+1
2015-11-09drm/i915/skl: Expose DC5/DC6 entry countsDamien Lespiau1-0/+4
2015-11-05drm/i915/skl: While sanitizing cdclock check the SWF18 as wellShobhit Kumar1-0/+1
2015-10-26drm/i915: Use paramtrized WRPLL_CTL()Ville Syrjälä1-1/+1
2015-10-13drm/i915: Parametrize and fix SWF registersVille Syrjälä1-14/+14
2015-10-13drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.Ville Syrjälä1-6/+6
2015-10-13drm/i915: Fix a few bad hex numbers in register definesVille Syrjälä1-2/+2
2015-10-13drm/i915: Protect register macro argumentsVille Syrjälä1-46/+46
2015-10-13drm/i915: Include gpio_mmio_base in GMBUS reg definesVille Syrjälä1-6/+6
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-01 22:10:41 +0300