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path: root/drivers/gpu/drm/amd/amdgpu
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2021-05-20drm/amdgpu: Refine the error report when flush tlb.Peng Ju Zhou1-1/+1
there are 2 hubs to flush in the gmc, to make it easier to debug when hub flush failed, refine the logs. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: Skip the program of GRBM_CAM* in SRIOVPeng Ju Zhou1-0/+3
KMD should not the program these registers, so skip them in the SRIOV environment. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: Fix GPU TLB update error when PAGE_SIZE > AMDGPU_PAGE_SIZEYi Li1-1/+1
When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB entries which need to update in amdgpu_map_buffer() should be multiplied by AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_PAGE_SIZE). Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yi Li <liyi@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdkfd: heavy-weight flush TLB after unmapPhilip Yang2-3/+10
Need do a heavy-weight TLB flush to make sure we have no more dirty data in the cache for the unmapped pages. Define enum TLB_FLUSH_TYPE, add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: Fill adev->unique_id with data from PF2VF msgJiawei Gu1-0/+2
Initialize unique_id from PF2VF under virtualization. V2: skip smu_get_unique_id() under virtualization Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: flush TLB if valid PDE turns into PTEPhilip Yang2-5/+16
Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping to return table_freed flag to indicate the previously valid PDE may have turned into a PTE if page table is freed. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: move struct amdgpu_vram_reservation into vram mgrChristian König2-5/+5
Not used outside of that file. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: check contiguous flags instead of mm_nodeChristian König1-7/+4
Drop the last user of drm_mm_node. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: set the contiguous flag if possibleChristian König1-2/+3
This avoids reallocating scanout BOs on first pin in a lot of cases. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: use cursor functions in amdgpu_bo_in_cpu_visible_vramChristian König1-6/+9
One of the last remaining uses of drm_mm_node. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: re-apply "use the new cursor in the VM code" v2Christian König2-38/+19
Now that we found the underlying problem we can re-apply this patch. This reverts commit 6b44b667e24cf89603ebdaa31b939c034d425162. v2: rebase on KFD changes Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: query boot config cap before issue psp cmdHawking Zhang1-4/+6
Only send boot_config cmd to ASICs that support dynamic boot config. Otherwise, the boot_config cmd will fail. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: add helper function to query dynamic boot config capHawking Zhang2-0/+17
Check firmware flags to determine whether dynmaic boot config is supported or not. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: switch to cached fw flags for mem training capHawking Zhang3-62/+11
Check cached firmware_flags to determin whether two stage mem training is supported or not. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: switch to cached fw flags for sram ecc capHawking Zhang1-21/+7
Check cached firmware_flags to determine whether sram ecc is supported or not. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: switch to cached fw flags for gpu virt capHawking Zhang3-16/+13
Check cached firmware_flags to determine if gpu virtualization is supported in vbios Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: add atomfirmware helper function to query fw capHawking Zhang4-12/+44
Fimware capability was changed from 16 bits to 32 bits for atomfirmware. add helper funciton to query firmware capability and cache the value at early stage. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: Complete multimedia bandwidth interfaceBokun Zhang4-7/+225
- Update SRIOV PF2VF header with latest revision - Extend existing function in amdgpu_virt.c to read MM bandwidth config from PF2VF message - Add SRIOV Sienna Cichlid codec array and update the bandwidth with PF2VF message v2: squash in removal of unused variable (Alex) Signed-off-by: Bokun Zhang <bokun.zhang@amd.com> Reviewed-by: Monk liu <monk.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: Albebaran: MTYPE_NC for coarse-grain remote memoryFelix Kuehling1-1/+2
MTYPE UC was used for a specific use case that ended up not being implemented. Use NC for better performance for coarse-grained memory where cache coherence during shader execution is not required. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: Arcturus: MTYPE_NC for coarse-grain remote memoryFelix Kuehling1-1/+2
MTYPE UC was used for a specific use case that ended up not being implemented. Use NC for better performance for coarse-grained memory where cache coherence during shader execution is not required. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: Add compile flag for securedisplayJinzhou Su1-0/+4
Add compile flag CONFIG_DEBUG_FS to clear the warning: unused variable 'amdgpu_securedisplay_debugfs_ops' Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/amdgpu: Cancel the hrtimer in sw_finiRoy Sun1-7/+5
Move the process of cancelling hrtimer to sw_fini Signed-off-by: Roy Sun <Roy.Sun@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/pm: enable ASPM by defaultKenneth Feng3-3/+3
Since ASPM function has been stable, we don't need to add the modprobe parameter and we can enable ASPM by default. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: update the method for harvest IP for specific SKULikun Gao1-14/+16
Update the method of disabling VCN IP for specific SKU for navi1x ASIC, it will judge whether should add the related IP at the function of amdgpu_device_ip_block_add(). Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: add judgement when add ip blocks (v2)Likun GAO5-2/+51
Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: add synchronization among waves in the same threadgroupDennis Li1-134/+142
It is possible that the previous waves have exited before others are created, so the other waves maybe reuse pyhsical resouces left by previous ones. Therefore add barrier instruction to synchronize waves within the same threadgroup. Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: stop touching sched.ready in the backendChristian König4-16/+1
This unfortunately comes up in regular intervals and breaks GPU reset for the engine in question. The sched.ready flag controls if an engine can't get working during hw_init, but should never be set to false during hw_fini. v2: squash in unused variable fix (Alex) Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/amdgpu: fix a potential deadlock in gpu resetLang Yu1-1/+0
When amdgpu_ib_ring_tests failed, the reset logic called amdgpu_device_ip_suspend twice, then deadlock occurred. Deadlock log: [ 805.655192] amdgpu 0000:04:00.0: amdgpu: ib ring test failed (-110). [ 806.290952] [drm] free PSP TMR buffer [ 806.319406] ============================================ [ 806.320315] WARNING: possible recursive locking detected [ 806.321225] 5.11.0-custom #1 Tainted: G W OEL [ 806.322135] -------------------------------------------- [ 806.323043] cat/2593 is trying to acquire lock: [ 806.323825] ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.325668] but task is already holding lock: [ 806.326664] ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.328430] other info that might help us debug this: [ 806.329539] Possible unsafe locking scenario: [ 806.330549] CPU0 [ 806.330983] ---- [ 806.331416] lock(&adev->dm.dc_lock); [ 806.332086] lock(&adev->dm.dc_lock); [ 806.332738] *** DEADLOCK *** [ 806.333747] May be due to missing lock nesting notation [ 806.334899] 3 locks held by cat/2593: [ 806.335537] #0: ffff888100d3f1b8 (&attr->mutex){+.+.}-{3:3}, at: simple_attr_read+0x4e/0x110 [ 806.337009] #1: ffff888136b1fd78 (&adev->reset_sem){++++}-{3:3}, at: amdgpu_device_lock_adev+0x42/0x94 [amdgpu] [ 806.339018] #2: ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.340869] stack backtrace: [ 806.341621] CPU: 6 PID: 2593 Comm: cat Tainted: G W OEL 5.11.0-custom #1 [ 806.342921] Hardware name: AMD Celadon-CZN/Celadon-CZN, BIOS WLD0C23N_Weekly_20_12_2 12/23/2020 [ 806.344413] Call Trace: [ 806.344849] dump_stack+0x93/0xbd [ 806.345435] __lock_acquire.cold+0x18a/0x2cf [ 806.346179] lock_acquire+0xca/0x390 [ 806.346807] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.347813] __mutex_lock+0x9b/0x930 [ 806.348454] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.349434] ? amdgpu_device_indirect_rreg+0x58/0x70 [amdgpu] [ 806.350581] ? _raw_spin_unlock_irqrestore+0x47/0x50 [ 806.351437] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.352437] ? rcu_read_lock_sched_held+0x4f/0x80 [ 806.353252] ? rcu_read_lock_sched_held+0x4f/0x80 [ 806.354064] mutex_lock_nested+0x1b/0x20 [ 806.354747] ? mutex_lock_nested+0x1b/0x20 [ 806.355457] dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.356427] ? soc15_common_set_clockgating_state+0x17d/0x19 [amdgpu] [ 806.357736] amdgpu_device_ip_suspend_phase1+0x78/0xd0 [amdgpu] [ 806.360394] amdgpu_device_ip_suspend+0x21/0x70 [amdgpu] [ 806.362926] amdgpu_device_pre_asic_reset+0xb3/0x270 [amdgpu] [ 806.365560] amdgpu_device_gpu_recover.cold+0x679/0x8eb [amdgpu] Signed-off-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Christian KÃnig <christian.koenig@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: update sdma golden setting for Navi12Guchun Chen1-0/+4
Current golden setting is out of date. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-05-20drm/amdgpu: update gc golden setting for Navi12Guchun Chen1-2/+4
Current golden setting is out of date. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-05-20drm/amdgpu: Fix a use-after-freexinhui pan1-0/+1
looks like we forget to set ttm->sg to NULL. Hit panic below [ 1235.844104] general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b7b4b: 0000 [#1] SMP DEBUG_PAGEALLOC NOPTI [ 1235.989074] Call Trace: [ 1235.991751] sg_free_table+0x17/0x20 [ 1235.995667] amdgpu_ttm_backend_unbind.cold+0x4d/0xf7 [amdgpu] [ 1236.002288] amdgpu_ttm_backend_destroy+0x29/0x130 [amdgpu] [ 1236.008464] ttm_tt_destroy+0x1e/0x30 [ttm] [ 1236.013066] ttm_bo_cleanup_memtype_use+0x51/0xa0 [ttm] [ 1236.018783] ttm_bo_release+0x262/0xa50 [ttm] [ 1236.023547] ttm_bo_put+0x82/0xd0 [ttm] [ 1236.027766] amdgpu_bo_unref+0x26/0x50 [amdgpu] [ 1236.032809] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x7aa/0xd90 [amdgpu] [ 1236.040400] kfd_ioctl_alloc_memory_of_gpu+0xe2/0x330 [amdgpu] [ 1236.046912] kfd_ioctl+0x463/0x690 [amdgpu] Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: add video_codecs query support for aldebaranJames Zhu1-0/+1
Add video_codecs query support for aldebaran. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amd/amdgpu: fix refcount leakJingwen Chen1-0/+3
[Why] the gem object rfb->base.obj[0] is get according to num_planes in amdgpufb_create, but is not put according to num_planes [How] put rfb->base.obj[0] in amdgpu_fbdev_destroy according to num_planes Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-20drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hangChangfeng2-5/+7
There is problem with 3DCGCG firmware and it will cause compute test hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid compute hang. Signed-off-by: Changfeng <Changfeng.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-05-20drm/amdgpu: Fix GPU TLB update error when PAGE_SIZE > AMDGPU_PAGE_SIZEYi Li1-1/+1
When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB entries which need to update in amdgpu_map_buffer() should be multiplied by AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_PAGE_SIZE). Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yi Li <liyi@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-05-19Merge tag 'drm-misc-next-2021-05-12' of ↵Dave Airlie17-42/+314
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.14: UAPI Changes: * drm: Disable connector force-probing for non-master clients * drm: Enforce consistency between IN_FORMATS property and cap + related driver cleanups * drm/amdgpu: Track devices, process info and fence info via /proc/<pid>/fdinfo * drm/ioctl: Mark AGP-related ioctls as legacy * drm/ttm: Provide tt_shrink file to trigger shrinker via debugfs; Cross-subsystem Changes: * fbdev/efifb: Special handling of non-PCI devices * fbdev/imxfb: Fix error message Core Changes: * drm: Add connector helper to attach HDR-metadata property and convert drivers * drm: Add connector helper to compare HDR-metadata and convert drivers * drm: Add conenctor helper to attach colorspace property * drm: Signal colorimetry in HDMI infoframe * drm: Support pitch for destination buffers; Add blitter function with generic format conversion * drm: Remove struct drm_device.pdev and update legacy drivers * drm: Remove obsolete DRM_KMS_FB_HELPER config option in core and drivers * drm: Remove obsolete drm_pci_alloc/drm_pci_free * drm/aperture: Add helpers for aperture ownership and convert drivers, replaces rsp fbdev helpers * drm/agp: Mark DRM AGP code as legacy and convert legacy drivers * drm/atomic-helpers: Cleanups * drm/dp: Handle downstream port counts of 0 correctly; AUX channel fixes; Use drm_err_*/drm_dbg_*(); Cleanups * drm/dp_dual_mode: Use drm_err_*/drm_dbg_*() * drm/dp_mst: Use drm_err_*/drm_dbg_*(); Use Extended Base Receiver Capability DPCD space * drm/gem-ttm-helper: Provide helper for dumb_map_offset and convert drivers * drm/panel: Use sysfs_emit; panel-simple: Use runtime PM, Power up panel when reading EDID, Cache EDID, Cleanups; Lms397KF04: DT bindings * drm/pci: Mark AGP helpers as legacy * drm/print: Handle NULL for DRM devices gracefully * drm/scheduler: Change scheduled fence track * drm/ttm: Don't count SG BOs against pages_limit; Warn about freeing pinned BOs; Fix error handling if no BO can be swapped out; Move special handling of non-GEM drivers into vmwgfx; Move page_alignment into the BO; Set drm-misc as TTM tree in MAINTAINERS; Cleanup ttm_agp_backend; Add ttm_sys_manager for system domain; Cleanups Driver Changes: * drm: Don't set allow_fb_modifiers explictly in drivers * drm/amdgpu: Pin/unpin fixes wrt to TTM; Use bo->base.size instead of mem->num_pages * drm/ast: Use managed pcim_iomap(); Fix EDID retrieval with DP501 * drm/bridge: MHDP8546: HDCP support + DT bindings, Register DP AUX channel with userspace; Sil8620: Fix module dependencies; dw-hdmi: Add option to not load CEC driver; Fix stopping in drm_bridge_chain_pre_enable(); Ti-sn65dsi86: Fix refclk handling, Break GPIO and MIPI-to-eDP into subdrivers, Use pm_runtime autosuspend, cleanups; It66121: Add driver + DT bindings; Adv7511: Support I2S IEC958 encoding; Anx7625: fix power-on delay; Nwi-dsi: Modesetting fixes; Cleanups * drm/bochs: Support screen blanking * drm/gma500: Cleanups * drm/gud: Cleanups * drm/i915: Use correct max source link rate for MST * drm/kmb: Cleanups * drm/meson: Disable dw-hdmi CEC driver * drm/nouveau: Pin/unpin fixes wrt to TTM; Use bo->base.size instead of mem->num_pages; Register AUX adapters after their connectors * drm/qxl: Fix shadow BO unpin * drm/radeon: Duplicate some DRM AGP code to uncouple from legacy drivers * drm/simpledrm: Add a generic DRM driver for simple-framebuffer devices * drm/tiny: Fix log spam if probe function gets deferred * drm/vc4: Add support for HDR-metadata property; Cleanups * drm/virtio: Create dumb BOs as guest blobs; * drm/vkms: Use managed drmm_universal_plane_alloc(); Add XRGB plane composition; Add overlay support * drm/vmwgfx: Enable console with DRM_FBDEV_EMULATION; Fix CPU updates of coherent multisample surfaces; Remove reservation semaphore; Add initial SVGA3 support; Support amd64; Use 1-based IDR; Use min_t(); Cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/YJvkD523evviED01@linux-uq9g.fritz.box
2021-05-13drm/amdgpu: fix fence calculation (v2)David M Nieto2-5/+17
The proper metric for fence utilization over several contexts is an harmonic mean, but such calculation is prohibitive in kernel space, so the code approximates it. Because the approximation diverges when one context has a very small ratio compared with the other context, this change filter out ratios smaller that 0.01% v2: make the fence calculation static and initialize variables within that function v3: Fix warnings (Alex) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: David M Nieto <david.nieto@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210513174539.27409-2-david.nieto@amd.com
2021-05-13drm/amdgpu: free resources on fence usage queryDavid M Nieto1-2/+6
Free the resources if the fence needs to be ignored during the ratio calculation Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: David M Nieto <david.nieto@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210513174539.27409-1-david.nieto@amd.com
2021-05-13drm/amdgpu: update vcn1.0 Non-DPG suspend sequenceSathishkumar S1-4/+9
update suspend register settings in Non-DPG mode. Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-13drm/amdgpu: set vcn mgcg flag for picassoSathishkumar S1-1/+2
enable vcn mgcg flag for picasso. Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-13drm/amdgpu: update the method for harvest IP for specific SKULikun Gao1-14/+16
Update the method of disabling VCN IP for specific SKU for navi1x ASIC, it will judge whether should add the related IP at the function of amdgpu_device_ip_block_add(). Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-13drm/amdgpu: add judgement when add ip blocks (v2)Likun GAO5-2/+51
Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11Merge drm/drm-next into drm-misc-nextThomas Zimmermann42-266/+960
Backmerging to get v5.12 fixes. Requested for vmwgfx. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2021-05-11drm/amdgpu: Delete two unneeded bool conversionsZhen Lei1-2/+2
The result of an expression consisting of a single relational operator is already of the bool type and does not need to be evaluated explicitly. No functional change. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11drm/amd/amdgpu: Fix errors in function documentationDwaipayan Ray1-0/+3
Fix a couple of syntax errors and removed one excess parameter in the function documentations which lead to kernel docs build warning. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dwaipayan Ray <dwaipayanray1@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11drm/amdgpu: add function to clear MMEA error status for aldebaranDennis Li3-0/+24
For aldebaran, hardware will not clear error status automatically when reading error status register, insteadly driver should set clear bit of the error status register explicitly to clear error status. Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11drm/amdgpu: correct the funtion to clear GCEA error statusDennis Li1-1/+4
The bit 11 of GCEA_ERR_STATUS register is used to clear GCEA error status. Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11drm/amdgpu: covert ras status to kernel errnoDennis Li2-38/+34
The original codes use ras status and kernl errno together in the same function, which is a wrong code style. Signed-off-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11drm/amdgpu: Quit RAS initialization earlier if RAS is disabledOak Zeng1-1/+1
If RAS is disabled through amdgpu_ras_enable kernel parameter, we should quit the RAS initialization eariler to avoid initialization of some RAS data structure such as sysfs etc. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-11drm/amdgpu: Export ras_*_enabled to debugfsLuben Tuikov1-2/+4
Export the runtime-set "ras_hw_enabled" and "ras_enabled" to debugfs, for debugging. Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: John Clements <john.clements@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-20 18:16:14 +0300