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path: root/drivers/dma/ipu
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2010-05-18DMAENGINE: extend the control command to include an argLinus Walleij1-5/+7
This adds an argument to the DMAengine control function, so that we can later provide control commands that need some external data passed in through an argument akin to the ioctl() operation prototype. [dan.j.williams@intel.com: fix up some missed conversions] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-27dmaengine: provide helper for setting txstateDan Williams1-5/+1
Simple conditional struct filler to cut out some duplicated code. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-27DMAENGINE: generic channel status v2Linus Walleij1-7/+8
Convert the device_is_tx_complete() operation on the DMA engine to a generic device_tx_status()operation which can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE, DMA_TX_PAUSED. [dan.j.williams@intel.com: update for timberdale] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Maciej Sosnowski <maciej.sosnowski@intel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Li Yang <leoli@freescale.com> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Magnus Damm <damm@opensource.se> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Joe Perches <joe@perches.com> Cc: Roland Dreier <rdreier@cisco.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-27DMAENGINE: generic slave control v2Linus Walleij1-6/+15
Convert the device_terminate_all() operation on the DMA engine to a generic device_control() operation which can now optionally support also pausing and resuming DMA on a certain channel. Implemented for the COH 901 318 DMAC as an example. [dan.j.williams@intel.com: update for timberdale] Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Maciej Sosnowski <maciej.sosnowski@intel.com> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Li Yang <leoli@freescale.com> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Magnus Damm <damm@opensource.se> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Joe Perches <joe@perches.com> Cc: Roland Dreier <rdreier@cisco.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-03-04Merge branch 'coh' into dmaengineDan Williams1-18/+7
2010-02-10async-tx: fix buffer submission error handling in ipu_idma.cGuennadi Liakhovetski1-18/+7
If submitting new buffer failed, a wrong descriptor gets completed and it doesn't check, if a callback is at all defined, which can lead to an Oops. Fix these bugs and make ipu_update_channel_buffer() void, because it never fails. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-02-03dma: cases IPU_PIX_FMT_BGRA32, BGR32 and ABGR32 are the same in ↵Roel Kluin1-14/+1
ipu_ch_param_set_size() In these cases the same statements are executed. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-05-13dma: fix ipu_idmac.c to not discard the last queued bufferGuennadi Liakhovetski1-1/+2
This also fixes the case of a single queued buffer, for example, when taking a single frame snapshot with the mx3_camera driver. Reported-by: Agustin Ferrin Pozuelo <gatoguan-os@yahoo.com> Tested-by: Agustin Ferrin Pozuelo <gatoguan-os@yahoo.com> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-05-05ipu_idmac: Use disable_irq_nosync() from within irq handlers.Ben Nizette1-2/+2
disable_irq() should wait for all running handlers to complete before returning. As such, if it's used to disable an interrupt from that interrupt's handler it will deadlock. This replaces the dangerous instances with the _nosync() variant which doesn't have this problem. Note the 2 handlers in question are only used #ifdef DEBUG so I imagine these code paths don't get hit often. Signed-off-by: Ben Nizette <bn@niasdigital.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-04-03Merge branch 'next' of ↵Linus Torvalds2-118/+255
git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup dw_dmac: add cyclic API to DW DMA driver dmaengine: Add privatecnt to revert DMA_PRIVATE property dmatest: add dma interrupts and callbacks dmatest: add xor test dmaengine: allow dma support for async_tx to be toggled async_tx: provide __async_inline for HAS_DMA=n archs dmaengine: kill some unused headers dmaengine: initialize tx_list in dma_async_tx_descriptor_init dma: i.MX31 IPU DMA robustness improvements dma: improve section assignment in i.MX31 IPU DMA driver dma: ipu_idmac driver cosmetic clean-up dmaengine: fail device registration if channel registration fails
2009-04-03dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanupGuennadi Liakhovetski1-9/+56
Add Start-of-Frame and End-of-Frame debugging to ipu_idmac.c, in the future it might also be needed for the actual video processing in mx3-camera, at which point, the ISRs will have to be transferred to mx3_camera.c, for which ipu_irq_map() and ipu_irq_unmap() functions will have to be exported. Also simplify a couple of pointer-dereferences. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-03-25dmaengine: initialize tx_list in dma_async_tx_descriptor_initDan Williams1-2/+0
Centralize this common initialization (and one case where ipu_idmac is duplicating ->chan initialization). Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-03-25dma: i.MX31 IPU DMA robustness improvementsGuennadi Liakhovetski1-84/+181
Add DMA error handling to the ISR, move common code fragments to functions, fix scatter-gather element queuing in the ISR, survive channel freeing and re-allocation in a quick succession. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-03-25dma: improve section assignment in i.MX31 IPU DMA driverGuennadi Liakhovetski2-5/+5
The i.MX31 IPU DMA driver is a platform driver, but doesn't need hotplug, so we can use __init and __exit function attributes. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-03-25dma: ipu_idmac driver cosmetic clean-upGuennadi Liakhovetski1-19/+14
Remove superfluous semicolons, update comments. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-03-13MX31 clkdev supportSascha Hauer1-1/+1
This patch adds clkdev support for i.MX31. This is done in a similar way done previously for i.MX27 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2009-03-05ipu_idmac: fix spinlock typeLuotao Fu1-1/+1
fix a probably accidently dropped reference operator while calling spin_unlock_restore to an ipu lock. Signed-off-by: Luotao Fu <l.fu@pengutronix.de> Cc: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-20i.MX31: Image Processing Unit DMA and IRQ driversGuennadi Liakhovetski4-0/+2330
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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