summaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Collapse)AuthorFilesLines
2012-07-31clk: validate pointer in __clk_disable()Fengguang Wu1-0/+3
clk_get() returns -ENOENT on error and some careless caller might dereference it without error checking: In mxc_rnga_remove(): struct clk *clk = clk_get(&pdev->dev, "rng"); // ... clk_disable(clk); Since it's insane to audit the lots of existing and future clk users, let's add a check in the callee to avoid kernel panic and warn about any buggy user. Cc: Russell King <rmk@arm.linux.org.uk> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: viresh kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-07-31clk: remove redundant depends on from drivers/KconfigViresh Kumar1-1/+0
menu "Common Clock Framework" has "depends on COMMON_CLK" and so configs defined within menu don't require these "depends on COMMON_CLK again". Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Cc: Wolfram Sang <w.sang@pengutronix.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jeff Garzik <jgarzik@redhat.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Bhupesh Sharma <bhupesh.sharma@st.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Mike Turquette <mturquette@linaro.org> Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: viresh kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-07-25Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds18-46/+2170
Pull common clk framework changes from Michael Turquette: "This includes a small number of core framework improvments, platform ports and new DT bindings." Fix up trivial conflicts in drivers/clk/Makefile * tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux: (21 commits) clk: fix compile for OF && !COMMON_CLK clk: fix clk_get on of_clk_get_by_name return check clk: mxs: clk_register_clkdev mx28 usb clocks clk: add highbank clock support dt: add clock binding doc to primecell bindings clk: add DT fixed-clock binding support clk: add DT clock binding support ARM: integrator: convert to common clock clk: add versatile ICST307 driver ARM: integrator: put symbolic bus names on devices ARM: u300: convert to common clock clk: cache parent clocks only for muxes clk: wm831x: Add initial WM831x clock driver clk: Constify struct clk_init_data clk: Add CLK_IS_BASIC flag to identify basic clocks clk: Add support for rate table based dividers clk: Add support for power of two type dividers clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3 clk: mxs: add clkdev lookup for pwm clk: mxs: Fix the GPMI clock name ...
2012-07-24Merge tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds3-0/+53
Pull support for three new arm SoC types from Arnd Bergmann: - The mvebu platform includes Marvell's Armada XP and Armada 370 chips, made by the mvebu business unit inside of Marvell. Since the same group also made the older but similar platforms we call "orion5x", "kirkwood", "mv78xx0" and "dove", we plan to move all of them into the mach-mvebu directory in the future. - socfpga is Altera's platform based on Cortex-A9 cores and a lot of FPGA space. This is similar to the Xilinx zynq platform we already support. The code is particularly clean, which is helped by the fact that the hardware doesn't do much besides the parts that are expected to get added in the FPGA. - The OMAP subarchitecture gains support for the latest generation, the OMAP5 based on the new Cortex-A15 core. Support is rather rudimentary for now, but will be extended in the future. * tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits) ARM: socfpga: initial support for Altera's SOCFPGA platform arm: mvebu: generate DTBs for supported SoCs ARM: mvebu: MPIC: read number of interrupts from control register arm: mach-mvebu: add entry to MAINTAINERS arm: mach-mvebu: add compilation/configuration change arm: mach-mvebu: add defconfig arm: mach-mvebu: add documentation for new device tree bindings arm: mach-mvebu: add support for Armada 370 and Armada XP with DT arm: mach-mvebu: add source files arm: mach-mvebu: add header clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver ARM: Kconfig update to support additional GPIOs in OMAP5 ARM: OMAP5: Add the build support arm/dts: OMAP5: Add omap5 dts files ARM: OMAP5: board-generic: Add device tree support ARM: omap2+: board-generic: clean up the irq data from board file ARM: OMAP5: Add SMP support ARM: OMAP5: Add the WakeupGen IP updates ARM: OMAP5: l3: Add l3 error handler support for omap5 ARM: OMAP5: gpmc: Update gpmc_init() ... Conflicts: Documentation/devicetree/bindings/arm/omap/omap.txt arch/arm/mach-omap2/Makefile drivers/clocksource/Kconfig drivers/clocksource/Makefile
2012-07-24Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2-0/+48
Pull arm soc-specific updates from Arnd Bergmann: "This is stuff that does not fit well into another category and in particular is not related to a particular board. The largest part in here is extending the am33xx support in the omap platform." Fix up trivial conflicts in arch/arm/mach-{imx/mach-mx35_3ds.c, tegra/Makefile} * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (74 commits) ARM: LPC32xx: Add PWM support ARM: LPC32xx: Add PWM clock ARM: LPC32xx: Set system serial based on cpu unique id ARM: vexpress: Config option for early printk console ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses ARM: vexpress: Add fixed regulator for SMSC ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files ARM: vexpress: Initial common clock support ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API ARM: EXYNOS: Add missing static storage class specifier in pmu.c file ARM: EXYNOS: Make combiner_init function static ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12 ARM: versatile: Make plat-versatile clock optional ARM: vexpress: Check master site in daughterboard's sysctl operations ARM: vexpress: remove automatic errata workaround selection ARM: LPC32xx: Adjust to pl08x DMA interface changes ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset ARM: imx: fix mx51 ehci setup errors ARM: imx: make ehci power/oc polarities configurable ...
2012-07-20clk: fix compile for OF && !COMMON_CLKRob Herring1-1/+1
With commit 766e6a4ec602d0c107 (clk: add DT clock binding support), compiling with OF && !COMMON_CLK is broken. Reported-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Reported-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-20clk: fix clk_get on of_clk_get_by_name return checkShawn Guo1-1/+1
The commit 766e6a4 (clk: add DT clock binding support) plugs device tree clk lookup of_clk_get_by_name into clk_get, and fall on non-DT lookup clk_get_sys if DT lookup fails. The return check on of_clk_get_by_name takes (clk != NULL) as a successful DT lookup. But it's not the case. For any system that does not define clk lookup in device tree, ERR_PTR(-ENOENT) will be returned, and consequently, all the client drivers calling clk_get in their probe functions will fail to probe with error code -ENOENT returned. Fix the issue by checking of_clk_get_by_name return with !IS_ERR(clk), and update of_clk_get and of_clk_get_by_name for !CONFIG_OF build correspondingly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Rob Herring <rob.herring@calxeda.com> Tested-by: Marek Vasut <marex@denx.de> Tested-by: Lauri Hintsala <lauri.hintsala@bluegiga.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-19ARM: socfpga: initial support for Altera's SOCFPGA platformDinh Nguyen3-0/+53
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18Clk: SPEAr1340: Update sys clock parent arrayVipul Kumar Samar1-2/+2
sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl register bit no. 23:25, with following possibilities 0XX: pll1_clk 10X: sys_synth_clk 110: pll2_clk 111: pll3_clk Out of several possibilities (h/w wise) to select same clock parent for sys_clk, current clock implementation was considering just one value. When bootloader programmed different (valid) value to select a clock parent then Linux breaks. Here, we try to include all possibilities which can lead to same clock selection thus making Linux independent of bootloader selection values. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2012-07-18clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.Vipul Kumar Samar1-2/+2
This patch is to fix typing mistake of clk enable register of i2c1 and uart1. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2012-07-18Clk:spear6xx:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-62/+60
The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk ras_gen1_synth_gate_clk -> ras_syn1_gclk pll3_48m -> pll3_ Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18Clk:spear3xx:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-94/+86
The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk ras_gen1_synth_gate_clk -> ras_syn1_gclk ras_pll3_48m -> ras_pll3_ pll3_48m -> pll3_ Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18clk:spear1310:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-157/+155
The max limit of con_id is 16 and dev_id is 20. As of now for spear1310, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk gmac_phy -> phy_ gmii_125m_pad -> gmii_pad Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18clk:spear1340:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-138/+135
The max limit of con_id is 16 and dev_id is 20. As of now for spear1340, many clk ids are exceeding this predefined limit. This patch rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk gmac_phy -> phy_ gmii_125m_pad_ -> gmii_pad Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-12Merge branch 'clk/mxs-for-3.6' of ↵Mike Turquette1-0/+4
git://git.linaro.org/people/shawnguo/linux-2.6 into clk-next
2012-07-12clk: mxs: clk_register_clkdev mx28 usb clocksRichard Zhao1-0/+4
Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Tested-by: Subodh Nijsure <snijsure@grid-net.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-07-12clk: add highbank clock supportRob Herring2-0/+347
This adds real clock support to Calxeda Highbank SOC using the common clock infrastructure. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [mturquette@linaro.org: fixed up invalid writes to const struct member] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12clk: add DT fixed-clock binding supportGrant Likely1-0/+23
Add support for DT "fixed-clock" binding to the common fixed rate clock support. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> [Rob Herring] Rework and move into common clock infrastructure Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12clk: add DT clock binding supportGrant Likely2-0/+217
Based on work 1st by Ben Herrenschmidt and Jeremy Kerr, then by Grant Likely, this patch adds support to clk_get to allow drivers to retrieve clock data from the device tree. Platforms scan for clocks in DT with of_clk_init and a match table, and the register a provider through of_clk_add_provider. The provider's clk_src_get function will be called when a device references the provider's OF node for a clock reference. v6 (Rob Herring): - Return error values instead of NULL to match clock framework expectations v5 (Rob Herring): - Move from drivers/of into common clock subsystem - Squashed "dt/clock: add a simple provider get function" and "dt/clock: add function to get parent clock name" - Rebase to 3.4-rc1 - Drop CONFIG_OF_CLOCK and just use CONFIG_OF - Add missing EXPORT_SYMBOL to various functions - s/clock-output-name/clock-output-names/ - Define that fixed-clock binding is a single output v4 (Rob Herring): - Rework for common clk subsystem - Add of_clk_get_parent_name function v3: - Clarified documentation v2: - fixed errant ';' causing compile error - Editorial fixes from Shawn Guo - merged in adding lookup to clkdev - changed property names to match established convention. After working with the binding a bit it really made more sense to follow the lead of 'reg', 'gpios' and 'interrupts' by making the input simply 'clocks' & 'clock-names' instead of 'clock-input-*', and to only use clock-output* for the producer nodes. (Sorry Shawn, this will mean you need to change some code, but it should be trivial) - Add ability to inherit clocks from parent nodes by using an empty 'clock-ranges' property. Useful for busses. I could use some feedback on the new property name, 'clock-ranges' doesn't feel right to me. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Shawn Guo <shawn.guo@freescale.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12ARM: integrator: convert to common clockLinus Walleij2-0/+112
This converts the Integrator platform to use common clock and the ICST driver. Since from this point not all ARM reference platforms use the clock, we define CONFIG_PLAT_VERSATILE_CLOCK and select it for all platforms except the Integrator. Open issue: I could not use the .init_early() field of the machine descriptor to initialize the clocks, but had to move them to .init_irq(), so presumably .init_early() is so early that common clock is not up, and .init_machine() is too late since it's needed for the clockevent/clocksource initialization. Any suggestions on how to solve this is very welcome. Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: use 'select' instead of versatile Kconfig] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12clk: add versatile ICST307 driverLinus Walleij4-0/+113
The ICST307 VCO clock has a shared driver in the ARM architecture. This patch provides a wrapper into the common clock framework so we can use the implementation in the ARM architecture without duplicating the code until all ARM platforms using this VCO are moved over. At that point we can merge the driver from the ARM platform into the generic file altogether. Cc: Russell King <linux@arm.linux.org.uk> Cc: Mike Turquette <mturquette@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: removed versatile Kconfig] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12Merge branch 'clk/mxs-for-3.6' of ↵Mike Turquette2-5/+7
git://git.linaro.org/people/shawnguo/linux-2.6 into clk-3.6
2012-07-12ARM: u300: convert to common clockLinus Walleij2-1/+748
This converts the U300 clock implementation over to use the common struct clk and moves the implementation down into drivers/clk. Since VCO isn't used in tree it was removed, it's not hard to put it back in if need be. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: trivial Makefile conflict] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12clk: cache parent clocks only for muxesRajendra Nayak1-2/+2
caching parent clocks makes sense only when a clock has more than one parent (mux clocks). Avoid doing this for every other clock. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [mturquette@linaro.org: removed extra parentheses] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12clk: wm831x: Add initial WM831x clock driverMark Brown3-0/+438
The WM831x and WM832x series of PMICs contain a flexible clocking subsystem intended to provide always on and system core clocks. It features: - A 32.768kHz crystal oscillator which can optionally be used to pass through an externally generated clock. - A FLL which can be clocked from either the 32.768kHz oscillator or the CLKIN pin. - A CLKOUT pin which can bring out either the oscillator or the FLL output. - The 32.768kHz clock can also optionally be brought out on the GPIO pins of the device. This driver fully supports the 32.768kHz oscillator and CLKOUT. The FLL is supported only in AUTO mode, the full flexibility of the FLL cannot currently be used. Due to a lack of access to systems where the core SoC has been converted to use the generic clock API this driver has been compile tested only. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12clk: Add CLK_IS_BASIC flag to identify basic clocksRajendra Nayak5-5/+5
Most platforms end up using a mix of basic clock types and some which use clk_hw_foo struct for filling in custom platform information when the clocks don't fit into basic types supported. In platform code, its useful to know if a clock is using a basic type or clk_hw_foo, which helps platforms know if they can safely use to_clk_hw_foo to derive the clk_hw_foo pointer from clk_hw. Mark all basic clocks with a CLK_IS_BASIC flag. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12clk: Add support for rate table based dividersRajendra Nayak1-16/+109
Some divider clks do not have any obvious relationship between the divider and the value programmed in the register. For instance, say a value of 1 could signify divide by 6 and a value of 2 could signify divide by 4 etc. Also there are dividers where not all values possible based on the bitfield width are valid. For instance a 3 bit wide bitfield can be used to program a value from 0 to 7. However its possible that only 0 to 4 are valid values. All these cases need the platform code to pass a simple table of divider/value tuple, so the framework knows the exact value to be written based on the divider calculation and can also do better error checking. This patch adds support for such rate table based dividers and as part of the support adds a new registration function 'clk_register_divider_table()' and a new macro for static definition 'DEFINE_CLK_DIVIDER_TABLE'. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-12clk: Add support for power of two type dividersRajendra Nayak1-19/+47
Quite often dividers and the value programmed in the register have a relation of 'power of two', something like value div 0 1 1 2 2 4 3 8... Add support for such dividers as part of clk-divider. The clk-divider flag 'CLK_DIVIDER_POWER_OF_TWO' should be used to define such clocks. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-11Merge tag 'v3.5-rc6' into next/socArnd Bergmann13-49/+55
Linux 3.5-rc6 Dependency for imx/soc changes
2012-07-05clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3Lauri Hintsala1-3/+3
SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand the frequency fix for ref_io1 to get SSP2 and SSP3 to work. Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-07-03clk: fix parent validation in __clk_set_parent()Rajendra Nayak1-15/+13
The below commit introduced a bug in __clk_set_parent() which could cause it to *skip* the parent validation which makes sure the parent passed to the api is a valid one. commit 7975059db572eb47f0fb272a62afeae272a4b209 Author: Rajendra Nayak <rnayak@ti.com> Date: Wed Jun 6 14:41:31 2012 +0530 clk: Allow late cache allocation for clk->parents This was identified by the following compiler warning.. drivers/clk/clk.c: In function '__clk_set_parent': drivers/clk/clk.c:1083:5: warning: 'i' may be used uninitialized in this function [-Wuninitialized] .. as reported by Marc Kleine-Budde. There were various options discussed on how to fix this, one being initing 'i' to clk->num_parents, but the below approach was found to be more appropriate as it also makes the 'parent validation' code simpler to read. Reported-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: stable@kernel.org
2012-06-27clk: mxs: add clkdev lookup for pwmShawn Guo2-0/+2
Add pwm clock lookup for imx23 and imx28 booting from device tree. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-06-27clk: mxs: Fix the GPMI clock nameFabio Estevam1-1/+1
The correct name for the GPMI clock is 'gpmi-nand'. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-06-27clk: mxs: rename the gpmi clock for imx28Huang Shijie1-1/+1
rename the clock name from `8000c000.gpmi` to `8000c000.gpmi-nand`. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2012-06-26clk: mxs: fix clock lookup after freeing init memoryMarc Kleine-Budde2-20/+20
The struct clk_lookup are marked as __initdata, resulting in being removed from memory after the kernel finished booting. However this leads to a NULL pointer de-ref if loading a module which uses clk_get. This patch removes the __initdata from the struct clk_lookup. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-26clk: mxs: fix ref_io clock definitionShawn Guo1-2/+2
The definition of clocks ref_io0 and ref_io1 were inverted. It causes a mmc regression on some boards right away. Fix the regression by correcting the ref_io clock definition. Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-26clk: Check parent for NULL in clk_change_ratePawel Moll1-4/+7
clk_change_rate() is accessing parent's rate without checking if the parent exists at all. In case of root clocks this will cause NULL pointer dereference. This patch follows what clk_calc_new_rates() does in such situation. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: stable@kernel.org
2012-06-26clk: Allow late cache allocation for clk->parentsRajendra Nayak1-5/+10
Parent clocks for muxes are cached in clk->parents to avoid frequent lookups, however the cache allocation happens only during clock registeration and later clk_set_parent() assumes a cache space available and allocated. This is not entirely true for platforms which do early clock registerations wherein the cache allocation using kzalloc could fail during clock registeration. Allow cache allocation to happen later as part of clk_set_parent() to help such cases and avoid crashes assuming a cache being available. While here also replace existing kmalloc() with kzalloc() in the file. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: stable@kernel.org
2012-06-26clk: SPEAr600: Fix ethernet clock name for DT based probingStefan Roese1-1/+1
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-21Viresh has movedViresh Kumar10-10/+10
viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-06-10ARM: nomadik: convert to generic clockLinus Walleij2-0/+48
Remove more custom stuff by simply converting the Nomadik machine to use generic clocks and move the driver to drivers/clk. Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-27Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds3-0/+2072
Pull arm-soc: soc specific changes (part 2) from Olof Johansson: "This adds support for the spear13xx platform, which has first been under review a long time ago and finally been completed after generic spear work has gone into the clock, dt and pinctrl branches. Also a number of updates for the samsung socs are part of this branch." Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much worse than they are: the exonys5 init code was refactored in commit fd454997d687 ("gpio: samsung: refactor gpiolib init for exynos4/5"), and then commit f10590c9836c ("ARM: EXYNOS: add GPC4 bank instance") added a new gpio chip define and did tiny updates to the init code. So the conflict diff looks like hell, but it's actually a fairly simple change. * tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits) ARM: exynos: fix building with CONFIG_OF disabled ARM: EXYNOS: Add AUXDATA for i2c controllers ARM: dts: Update device tree source files for EXYNOS5250 ARM: EXYNOS: Add device tree support for interrupt combiner ARM: EXYNOS: Add irq_domain support for interrupt combiner ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5 ARM: EXYNOS: update irqs for EXYNOS5250 SoC ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll ARM: EXYNOS: add GPC4 bank instance ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition ARM: EXYNOS: Modify the GIC physical address for static io-mapping ARM: EXYNOS: Add watchdog timer clock instance pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res SPEAr: Update MAINTAINERS and Documentation SPEAr13xx: Add defconfig SPEAr13xx: Add compilation support SPEAr13xx: Add dts and dtsi files pinctrl: Add SPEAr13xx pinctrl drivers pinctrl: SPEAr: Create macro for declaring GPIO PINS SPEAr13xx: Add common clock framework support ...
2012-05-26Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2-10/+12
Pull arm-soc device tree conversions (part 2) from Olof Johansson: "These continue the device tree work from part 1, this set is for the tegra, mxs and imx platforms, all of which have dependencies on clock or pinctrl changes submitted earlier." Fix up trivial conflicts due to nearby changes in drivers/{gpio/gpio,i2c/busses/i2c}-mxs.c * tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (73 commits) ARM: dt: tegra: invert status=disable vs status=okay ARM: dt: tegra: consistent basic property ordering ARM: dt: tegra: sort nodes based on bus order ARM: dt: tegra: remove duplicate device_type property ARM: dt: tegra: consistenly use lower-case for hex constants ARM: dt: tegra: format regs properties consistently ARM: dt: tegra: gpio comment cleanup ARM: dt: tegra: remove unnecessary unit addresses ARM: dt: tegra: whitespace cleanup ARM: dt: tegra cardhu: fix typo in SDHCI node name ARM: dt: tegra: cardhu: register core regulator tps62361 ARM: dt: tegra30.dtsi: Add SMMU node ARM: dt: tegra20.dtsi: Add GART node ARM: dt: tegra30.dtsi: Add Memory Controller(MC) nodes ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes ARM: dt: tegra: Add device tree support for AHB ARM: dts: enable audio support for imx28-evk ARM: dts: enable i2c device for imx28-evk i2c: mxs: add device tree probe support ARM: dts: enable mmc for imx28-evk ...
2012-05-16Merge branch 'clk-next' of git://git.linaro.org/people/mturquette/linux into ↵Arnd Bergmann1-1/+10
next/clock * 'clk-next' of git://git.linaro.org/people/mturquette/linux: clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate(). clk: Provide dummy clk_unregister() ARM: Kirkwood: Replace clock gating ARM: Orion: Audio: Add clk/clkdev support ARM: Orion: PCIE: Add support for clk ARM: Orion: XOR: Add support for clk ARM: Orion: CESA: Add support for clk ARM: Orion: SDIO: Add support for clk. ARM: Orion: NAND: Add support for clk, if there is one. ARM: Orion: EHCI: Add support for enabling clocks ARM: Orion: SATA: Add per channel clk/clkdev support. ARM: Orion: UART: Get the clock rate via clk_get_rate(). ARM: Orion: WDT: Add clk/clkdev support ARM: Orion: Eth: Add clk/clkdev support. ARM: Orion: SPI: Add clk/clkdev support. ARM: Orion: Add clocks using the generic clk infrastructure. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-05-16clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate().Saravana Kannan1-1/+1
The clk_set_rate() code shouldn't check the clock's enable count when validating CLK_SET_RATE_GATE flag since the enable count could change after the validation. Similar to clk_set_parent(), it should instead check the prepare count. The prepare count should go to zero only when the end user expects the clock to not be enabled in the future. Since the code already grabs the prepare count before validation, it's not possible for prepare count to change after validation and by association not possible for a well behaving end user to enable the clock while the set rate is in progress. Signed-off-by: Saravana Kannan <skannan@codeaurora.org> Reviewed-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-15clk: Provide dummy clk_unregister()Mark Brown1-0/+9
While there's no actual implementation behind it having the call to use in drivers makes them feel neater from a driver author point of view. An actual implementation can wait for someone who needs to use the function in a real system. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> [mturquette@linaro.org: void return type instead of int -EINVAL] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-05-14SPEAr13xx: Add common clock framework supportViresh Kumar3-0/+2072
This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based on earlier support for SPEAr3xx family. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@ti.com>
2012-05-13mmc: mxs-mmc: get rid of the use of cpu_is_xxxShawn Guo2-6/+6
The register HW_SSP_VERSION is broken for ssp version detection, as the address of the register is different between imx23 and imx28. Let's use platform_device_id to detect the device, so that the use of cpu_is_xxx can be removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Chris Ball <cjb@laptop.org>
2012-05-13Merge branch 'spear/clock' into next/clockArnd Bergmann10-1/+2014
Viresh Kumar <viresh.kumar@st.com> writes: This is rebased over a (merge of Mike's/clk-next & SPEAr's DT) + Russell's patch: CLKDEV: provide helpers for common clock framework rebased over them. * spear/clock: SPEAr: Switch to common clock framework SPEAr: Call clk_prepare() before calling clk_enable SPEAr: clk: Add General Purpose Timer Synthesizer clock SPEAr: clk: Add Fractional Synthesizer clock SPEAr: clk: Add Auxiliary Synthesizer clock SPEAr: clk: Add VCO-PLL Synthesizer clock Conflicts: drivers/clk/Makefile [Arnd: rebased again without the spear/dt branch] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-05-12SPEAr: Switch to common clock frameworkViresh Kumar3-0/+957
SPEAr SoCs used its own clock framework since now. From now on they will move to use common clock framework. This patch updates existing SPEAr machine support to adapt for common clock framework. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-02 18:55:43 +0300