BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2018-06-01	clk: imx6sx: disable unnecessary clocks during clock initialization	Anson Huang	1	-6/+1
2018-06-01	clk: qcom: Add video clock controller driver for SDM845	Amit Nischal	3	-0/+370
2018-06-01	clk: msm8996-gcc: Mark halt check as no-op for USB/PCIE pipe_clk	Manu Gautam	1	-0/+4
2018-06-01	clk: qcom: mmcc-msm8996: leave all mmagic gdscs and clocks always enabled	Rajendra Nayak	2	-12/+12
2018-06-01	clk: qcom: Register the gdscs before the clocks	Rajendra Nayak	1	-16/+16
2018-06-01	clk: qcom: gdsc: Add support for ALWAYS_ON gdscs	Rajendra Nayak	2	-0/+9
2018-06-01	clk: berlin: switch to SPDX license identifier	Jisheng Zhang	9	-108/+9
2018-05-30	clk: davinci: Fix link errors when not all SoCs are enabled	David Lechner	4	-3/+50
2018-05-30	clk: davinci: psc: allow for dev == NULL	David Lechner	5	-18/+52
2018-05-30	clk: davinci: da850-pll: change PLL0 to CLK_OF_DECLARE	David Lechner	3	-6/+21
2018-05-30	clk: davinci: pll: allow dev == NULL	David Lechner	8	-137/+235
2018-05-30	clk: davinci: psc-dm365: fix few clocks	Sekhar Nori	1	-3/+16
2018-05-30	clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled	Sekhar Nori	1	-1/+1
2018-05-30	clk: davinci: psc-dm355: fix ASP0/1 clkdev lookups	David Lechner	1	-2/+2
2018-05-30	clk: davinci: pll-dm355: fix SYSCLKn parent names	David Lechner	1	-5/+5
2018-05-30	clk: davinci: pll-dm355: drop pll2_sysclk2	David Lechner	1	-4/+1
2018-05-23	clk: rockchip: remove deprecated gate-clk code and dt-binding	Heiko Stuebner	2	-99/+0
2018-05-22	clk: rockchip: use match_string() helper	Yisheng Xie	1	-11/+5
2018-05-21	clk: meson: axg: let mpll clocks round closest	Jerome Brunet	1	-0/+4
2018-05-21	clk: meson: mpll: add round closest support	Jerome Brunet	2	-5/+22
2018-05-21	clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL	Martin Blumenstingl	1	-0/+7
2018-05-18	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	Dmitry Osipenko	7	-8/+39
2018-05-18	clk: tegra20: Correct parents of CDEV1/2 clocks	Dmitry Osipenko	1	-4/+2
2018-05-18	clk: tegra20: Add DEV1/DEV2 OSC dividers	Dmitry Osipenko	1	-0/+14
2018-05-18	clk: meson: use SPDX license identifiers consistently	Jerome Brunet	13	-238/+20
2018-05-17	clk: x86: Add ST oscout platform clock	Akshu Agrawal	2	-1/+79
2018-05-17	clk: sunxi-ng: r40: export a regmap to access the GMAC register	Icenowy Zheng	1	-0/+33
2018-05-17	clk: sunxi-ng: r40: rewrite init code to a platform driver	Icenowy Zheng	1	-11/+28
2018-05-16	clk: at91: PLL recalc_rate() now using cached MUL and DIV values	Marcin Ziemianowicz	1	-12/+1
2018-05-16	clk: stm32: fix: stm32 clock drivers are not compiled by default	Gabriel Fernandez	1	-4/+2
2018-05-16	clk: imx6ull: use OSC clock during AXI rate change	Stefan Agner	1	-1/+1
2018-05-16	clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration	Sekhar Nori	1	-1/+2
2018-05-16	clk: imx: Add new clo01 and clo2 controlled by CCOSR	Michael Trimarchi	1	-0/+18
2018-05-16	clk: mediatek: add g3dsys support for MT2701 and MT7623	Sean Wang	3	-0/+102
2018-05-16	clk: mediatek: correct the clocks for MT2701 HDMI PHY module	Ryder Lee	1	-2/+6
2018-05-16	clk: bulk: silently error out on EPROBE_DEFER	Jerome Brunet	1	-2/+3
2018-05-16	clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC	Jianguo Sun	1	-0/+17
2018-05-16	clk:aspeed: Fix reset bits for PCI/VGA and PECI	Jae Hyun Yoo	1	-2/+2
2018-05-16	clk: aspeed: Support second reset register	Joel Stanley	1	-8/+36
2018-05-16	clk: socfpga: stratix10: suppress unbinding platform's clock driver	Dinh Nguyen	1	-0/+1
2018-05-16	clk: socfpga: stratix10: use platform driver APIs	Dinh Nguyen	1	-22/+17
2018-05-16	clk: uniphier: add LD11/LD20 stream demux system clock	Katsuhiro Suzuki	1	-0/+5
2018-05-16	clk: samsung: simplify getting .drvdata	Wolfram Sang	1	-4/+2
2018-05-15	clk: stm32mp1: Fix a memory leak in 'clk_stm32_register_gate_ops()'	Christophe JAILLET	1	-8/+1
2018-05-15	clk: stm32mp1: Add CLK_IGNORE_UNUSED to ck_sys_dbg clock	Gabriel Fernandez	1	-1/+2
2018-05-15	clk: meson: drop CLK_SET_RATE_PARENT flag	Yixun Lan	1	-1/+1
2018-05-15	clk: meson-axg: Add AO Clock and Reset controller driver	Qiufang Dai	4	-1/+195
2018-05-15	clk: meson: aoclk: refactor common code into dedicated file	Yixun Lan	6	-62/+160
2018-05-15	clk: meson: migrate to devm_of_clk_add_hw_provider API	Yixun Lan	1	-1/+1
2018-05-15	clk: meson: gxbb: add the video decoder clocks	Maxime Jourdan	2	-1/+119