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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2021-06-14clk: imx: scu: remove legacy scu clock binding supportDong Aisheng2-135/+81
2021-06-14clk: imx: Remove the audio ipg clock from imx8mpJacky Bai1-1/+0
2021-06-10clk: renesas: Add support for R9A07G044 SoCLad Prabhakar5-0/+141
2021-06-10clk: renesas: Add CPG core wrapper for RZ/G2L SoCLad Prabhakar4-0/+883
2021-06-09clk: meson: g12a: Add missing NNA source clocks for g12bNick Xie1-0/+6
2021-06-09clk: vc5: fix output disabling when enabling a FODLuca Ceresoli1-3/+24
2021-06-09clk: ti: add am33xx/am43xx spread spectrum clock supportDario Binacchi2-0/+124
2021-06-09clk: ti: fix typo in routine descriptionDario Binacchi1-1/+1
2021-06-09clk: qcom: smd-rpm: Fix wrongly assigned RPM_SMD_PNOC_CLKKonrad Dybcio1-1/+1
2021-06-08clkdev: remove unused clkdev_alloc() interfacesArnd Bergmann1-28/+0
2021-06-08clkdev: remove CONFIG_CLKDEV_LOOKUPArnd Bergmann2-7/+2
2021-06-04clk: versatile: Depend on HAS_IOMEMStephen Boyd1-0/+1
2021-06-02clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()Yang Yingliang1-1/+3
2021-06-02clk: qcom: dispcc-sm8250: Add EDP clocksBjorn Andersson1-2/+184
2021-06-02clk: qcom: dispcc-sm8250: Add sc8180x supportBjorn Andersson1-1/+3
2021-06-02clk: qcom: smd-rpm: De-duplicate identical entriesKonrad Dybcio1-405/+247
2021-06-02clk: qcom: smd-rpm: Switch to parent_dataKonrad Dybcio1-4/+16
2021-06-02clk: qcom: Add MDM9607 GCC driverKonrad Dybcio3-0/+1663
2021-06-02clk: analogbits: fix doc warning in wrpll-cln28hpc.cYang Yingliang1-1/+1
2021-06-02clk: sifive: Fix kernel-docYang Li1-1/+1
2021-06-02clk: versatile: remove dependency on ARCH_*Peter Collingbourne1-2/+0
2021-06-02clk: qcom: cleanup some dev_err_probe() callsDan Carpenter1-2/+4
2021-06-02clk: qcom: Simplify usage of dev_err_probe()Uwe Kleine-König1-14/+8
2021-05-31clk: tegra: Don't deassert reset on enabling clocksDmitry Osipenko3-13/+1
2021-05-31clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko1-3/+3
2021-05-31clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttlingDmitry Osipenko2-3/+15
2021-05-31clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko1-0/+3
2021-05-31clk: tegra: Halve SCLK rate on Tegra20Dmitry Osipenko1-3/+3
2021-05-31clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko1-5/+4
2021-05-31clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2-25/+58
2021-05-31clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko1-1/+1
2021-05-28clk: rockchip: export ACLK_VCODEC for RK3036Alex Bee1-1/+1
2021-05-27clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto1-0/+1
2021-05-27clk: renesas: cpg-mssr: Make srstclr[] comment block consistentGeert Uytterhoeven1-1/+3
2021-05-27clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitionsGeert Uytterhoeven1-6/+0
2021-05-26clk: qcom: clk-rcg2: Add support for duty-cycle for RCGTaniya Das1-0/+81
2021-05-24clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audioTobias Schramm1-2/+2
2021-05-24clk: meson: axg-audio: improve deferral handlingJerome Brunet1-3/+2
2021-05-24clk: rockchip: fix rk3568 cpll clk gate bitsPeter Geis1-5/+5
2021-05-20clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet1-1/+1
2021-05-19clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl1-11/+15
2021-05-11clk: rockchip: Optimize PLL table memory usageElaine Zhang1-11/+18
2021-05-11clk: renesas: r9a06g032: Switch to .determine_rate()Geert Uytterhoeven1-12/+13
2021-05-11clk: renesas: div6: Implement range checkingGeert Uytterhoeven1-1/+7
2021-05-11clk: renesas: div6: Consider all parents for requested rateGeert Uytterhoeven1-3/+32
2021-05-11clk: renesas: div6: Switch to .determine_rate()Geert Uytterhoeven1-5/+7
2021-05-11clk: renesas: div6: Simplify src mask handlingGeert Uytterhoeven1-20/+11
2021-05-11clk: renesas: div6: Use clamp() instead of clamp_t()Geert Uytterhoeven1-1/+1
2021-05-11clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()Dinghao Liu1-9/+15
2021-05-11clk: renesas: r8a779a0: Add ISPCS clocksNiklas Söderlund1-0/+4