BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2016-05-28	remove lots of IS_ERR_VALUE abuses	Arnd Bergmann	1	-1/+1
2016-05-21	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	19	-114/+369
2016-05-18	Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/a...	Linus Torvalds	1	-0/+58
2016-05-09	Merge tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/gi...	Arnd Bergmann	1	-0/+58
2016-05-03	Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...	Stephen Boyd	19	-114/+427
2016-04-28	clk: tegra: dfll: Reformat CVB frequency table	Thierry Reding	1	-25/+25
2016-04-28	clk: tegra: dfll: Properly clean up on failure and removal	Thierry Reding	4	-4/+48
2016-04-28	clk: tegra: dfll: Make code more comprehensible	Thierry Reding	3	-41/+37
2016-04-28	clk: tegra: dfll: Reference CVB table instead of copying data	Thierry Reding	3	-27/+17
2016-04-28	clk: tegra: dfll: Update kerneldoc	Thierry Reding	1	-5/+5
2016-04-28	clk: tegra: Fix PLL_U post divider and initial rate on Tegra30	Lucas Stach	1	-5/+6
2016-04-28	clk: tegra: Initialize PLL_C to sane rate on Tegra30	Lucas Stach	1	-0/+1
2016-04-28	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein	3	-2/+66
2016-04-28	clk: tegra: Add sor_safe clock	Thierry Reding	2	-0/+5
2016-04-28	clk: tegra: dpaux and dpaux1 are fixed factor clocks	Thierry Reding	3	-2/+12
2016-04-28	clk: tegra: Add dpaux1 clock	Thierry Reding	3	-0/+3
2016-04-28	clk: tegra: Use correct parent for dpaux clock	Thierry Reding	1	-1/+1
2016-04-28	clk: tegra: Add fixed factor peripheral clock type	Thierry Reding	3	-0/+138
2016-04-28	clk: tegra: Special-case mipi-cal parent on Tegra114	Thierry Reding	2	-2/+6
2016-04-28	clk: tegra: Remove trailing blank line	Thierry Reding	1	-1/+0
2016-04-28	clk: tegra: Constify peripheral clock registers	Thierry Reding	5	-7/+7
2016-04-28	clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs	Andrew Bresticker	1	-0/+58
2016-04-28	treewide: Fix typos in printk	Masanari Iida	1	-1/+1
2016-03-30	clk: tegra: Make reset_control_ops const	Philipp Zabel	1	-1/+1
2016-03-03	clk: tegra: Remove CLK_IS_ROOT	Stephen Boyd	5	-14/+8
2016-02-02	clk: tegra: super: Fix sparse warnings for functions not declared as static	Jon Hunter	1	-3/+3
2016-02-02	clk: tegra: Fix sparse warnings for functions not declared as static	Jon Hunter	1	-17/+19
2016-02-02	clk: tegra: Fix sparse warning for pll_m	Jon Hunter	1	-1/+1
2016-02-02	clk: tegra: Use definition for pll_u override bit	Jon Hunter	1	-1/+1
2016-02-02	clk: tegra: Fix warning caused by pll_u failing to lock	Jon Hunter	1	-2/+0
2016-02-02	clk: tegra: Fix clock sources for Tegra210 EMC	Jon Hunter	1	-1/+2
2016-02-02	clk: tegra: Add the APB2APE audio clock on Tegra210	Jon Hunter	3	-0/+3
2016-02-02	clk: tegra: Add missing of_node_put()	Amitoj Kaur Chawla	1	-2/+4
2016-02-02	clk: tegra: Fix PLLE SS coefficients	Mark Kuo	1	-6/+12
2016-02-02	clk: tegra: Fix typos around clearing PLLE bits during enable	Rhyland Klein	1	-2/+2
2016-02-02	clk: tegra: Do not disable PLLE when under hardware control	Mark Kuo	1	-7/+15
2016-02-02	clk: tegra: Fix pllx dyn step calculation	Rhyland Klein	1	-5/+5
2016-02-02	clk: tegra: pll: Fix potential sleeping-while-atomic	Andrew Bresticker	1	-3/+3
2016-02-02	clk: tegra: Fix the misnaming of nvenc from msenc	Rhyland Klein	1	-1/+1
2016-02-02	clk: tegra: Fix naming of MISC registers	Rhyland Klein	1	-18/+18
2016-01-25	clk: tegra: Remove improper flags for lock_enable	Rhyland Klein	1	-28/+14
2016-01-25	clk: tegra: Fix divider on VI_I2C	Rhyland Klein	1	-1/+1
2016-01-21	Merge tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kerne...	Linus Torvalds	1	-2/+2
2015-12-17	clk: tegra: Read correct IDDQ register in PLL_SS registration	Bill Huang	1	-4/+7
2015-12-17	clk: tegra: Fix WARN_ON in PLL_RE registration	Bill Huang	1	-1/+2
2015-12-17	clk: tegra: pll: Fix issues with rates for VCO PLLs	Andrew Bresticker	1	-4/+12
2015-12-17	clk: tegra: Add support for Tegra210 clocks	Rhyland Klein	5	-0/+2868
2015-12-17	clk: tegra: Add Super Gen5 Logic	Bill Huang	2	-13/+132
2015-12-17	clk: tegra: pll: Add logic for SS	Bill Huang	2	-1/+28
2015-12-17	clk: tegra: pll: Add dyn_ramp callback	Rhyland Klein	2	-0/+11