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path: root/drivers/clk/hisilicon
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2013-12-11clk: hi3620: add gate clock flagHaojian Zhuang1-59/+59
Add missing CLK_SET_RATE_PARENT flag for gate clock. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-12-11clk: hi3620: fix wrong flags on dividerHaojian Zhuang1-11/+11
The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not CLK_MUX_HIWORD_MASK. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
2013-12-04clk: hisilicon: add common clock supportHaojian Zhuang5-0/+651
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-24 02:38:47 +0300