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path: root/drivers/clk/hisilicon
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2017-09-01clk: hi6220: change watchdog clock sourceLeo Yan1-3/+3
The old code uses tcxo (19.2MHz) as watchdog clock but actually the watchdog uses 32K clock, as result the watchdog timeout cannot be set correctly and delay long time to reset SoC. So this patch is to use 'ref32k' as clock source for watchdog. Fixes: 72ea48610d43 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC") Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue1-0/+21
Add usb2 clocks for hi3798cv200 SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-20clk: hi6220: add acpu clockZhangfei Gao1-0/+22
Add acpu clock, including sft clock controlling hi6220 coresight module Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-20clk: hi3660: Set PPLL2 to 2880MZhong Kaihua1-2/+2
Set PPLL2 to 2880M. With this patch, we saw better compatibility on various 1080p HDMI monitors. Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Zheng Shaobo <zhengshaobo1@huawei.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Add UL to long number to silence C90 warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-20clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun1-0/+40
This patch adds more clocks for hi3660, including: - video encoder and decoder - ISP (Image Signal Processing) Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-20clk: hi3660: fix wrong parent name of clk_mux_sysbusChen Jun1-2/+4
Parent name of clk_mux_sysbus is not correct. This patch fixes it. Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-20clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVERLeo Yan1-10/+38
The timer will register into system at very early phase at kernel boot; if timer needs to use clock, the clock should be get ready in function of_clk_init() so later the timer driver probe can retrieve clock successfully. This is finished in below flow on arm64: start_kernel() `-> time_init() `-> of_clk_init(NULL) => register timer's clock `-> clocksource_probe() => register timer On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result, sp804 timer probe returns failure due if cannot bind clock properly. To fix the failure, this patch is to split crgctrl clocks into two subsets. One part is for fixed_rate_clks which includes pre-defined fixed rate clocks, and "osc32k" clock is in this category; So we change their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks can be registered ahead with function of_clk_init() and timer driver can bind timer clock successfully; the rest of the crgctrl clocks are still registered by the probe of the platform driver. This patch also adds checking for all crgctrl clocks registration and print out log if any clock has failure. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: hi3620: Fix a typo in one variable nameMarkus Elfring1-3/+3
The script "checkpatch.pl" pointed information out like the following. CHECK: 'seperated' may be misspelled - perhaps 'separated'? Thus rename the affected variable. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: hi3620: Delete error messages for a failed memory allocation in two ↵Markus Elfring1-6/+2
functions The script "checkpatch.pl" pointed information out like the following. WARNING: Possible unnecessary 'out of memory' message Thus remove such statements here. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()Markus Elfring1-1/+1
* A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kcalloc". This issue was detected by using the Coccinelle software. * Replace the specification of a data type by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: hisilicon: Delete error messages for failed memory allocations in ↵Markus Elfring1-6/+4
hisi_clk_init() The script "checkpatch.pl" pointed information out like the following. WARNING: Possible unnecessary 'out of memory' message Thus remove such statements here. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: hisilicon: Use devm_kmalloc_array() in hisi_clk_alloc()Markus Elfring1-2/+3
* A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "devm_kmalloc_array". This issue was detected by using the Coccinelle software. * Replace the specification of a data type by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-19clk: hisilicon: Use kcalloc() in hisi_clk_init()Markus Elfring1-2/+1
* A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kcalloc". This issue was detected by using the Coccinelle software. * Replace the specification of a data type by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-04-12clk: hi6220: add debug APB clockLeo Yan1-0/+1
The debug APB clock is absent in hi6220 driver, so this patch is to add support for it. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2017-01-27clk: hisilicon: fix lock assignmentLeo Yan1-0/+1
In clock driver initialize phase the spinlock is missed to assignment to struct clkgate_separated, finally there have no locking to protect exclusive accessing for clock registers. This bug introduces the console has no output after enable coresight driver on 96boards Hikey; this is because console using UART3, which has shared the same register with coresight clock enabling bit. After applied this patch it can assign lock properly to protect exclusive accessing, and console can work well after enabled coresight modules. Fixes: 0aa0c95f743a ("clk: hisilicon: add common clock support") Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-10clk: hisilicon: Add clock driver for hi3660 SoCZhangfei Gao3-0/+575
Add clock drivers for hi3660 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Simplify probe with function pointer] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-15clk: Hi6220: enable stub clock driver for ARCH_HISILeo Yan1-0/+1
In current kernel config 'CONFIG_STUB_CLK_HI6220' is disabled by default, as result stub clock driver has not been registered and CPUFreq driver cannot work. This patch is to enable stub clock driver in config for ARCH_HISI. Reported-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-15Merge branch 'clk-hisi' into clk-nextStephen Boyd5-0/+719
* clk-hisi: clk: hisilicon: add CRG driver for Hi3516CV300 SoC clk: hisilicon: add CRG driver for Hi3798CV200 SoC
2016-11-14clk: hisilicon: add CRG driver for Hi3516CV300 SoCPan Wen3-0/+339
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Pan Wen <wenpan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-12clk: hisilicon: add CRG driver for Hi3798CV200 SoCJiancheng Xue4-0/+380
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-18clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock initShawn Guo1-2/+2
The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but also reset controller. It worked fine that single sysctrl/mediactrl device node in DT can be used to initialize clock driver and populate platform device for reset controller. But it stops working after commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks") gets merged. The commit sets flag OF_POPULATED during clock initialization to skip the platform device populating for the same device node. On hi6220, it effectively makes hi6220-sysctrl reset driver not probe any more. The patch changes hi6220 sysctrl and mediactrl clock init macro from CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using the same hardware block can continue working. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-07clk: hi6220: Change syspll and media_syspll clk to 1.19GHzXinliang Liu1-2/+2
In the bootloader of HiKey/96boards, syspll and media_syspll clk was initialized to 1.19GHz. So, here changes it in kernel accordingly. 1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI (74.25MHz required by standards). Closer pixel clock means better compatibility to HDMI monitors. Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1467189955-21694-1-git-send-email-guodong.xu@linaro.org
2016-06-30clk: hisilicon: hi3519: add driver remove path and fix some issuesJiancheng Xue1-16/+100
1. Add driver remove path. 2. Fix some issues. -Fix the ordering issue about clock provider being published. -Add error checking upon registering clocks. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30clk: hisilicon: add hisi_clk_unregister_* functionsJiancheng Xue1-0/+21
Add hisi_clk_unregister_* functions. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30clk: hisilicon: add error processing for hisi_clk_register_* functionsJiancheng Xue2-15/+55
Add error processing for hisi_clk_register_* functions. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30clk: hisilicon: add hisi_clk_alloc function.Jiancheng Xue2-0/+32
Before, there was an ordering issue that the clock provider had been published in hisi_clk_init before it could provide valid clocks to consumers. hisi_clk_alloc is just used to allocate memory space for struct hisi_clock_data. It makes it possible to publish the provider after the clocks are ready. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30reset: hisilicon: change the definition of hisi_reset_initJiancheng Xue3-13/+13
Change the input arguments type to struct platform_device pointer. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-30Merge branch 'clk-hi6220-rtc' into clk-nextStephen Boyd1-0/+2
* clk-hi6220-rtc: clk: hi6220: Add RTC clock for pl031
2016-06-30clk: hi6220: Add RTC clock for pl031Zhangfei Gao1-0/+2
Adds clk support for the pl031 RTC on hi6220 Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [jstultz: Forward ported, tweaked commit description] Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-21clk: hi6220: fix missing clk.h includeBen Dooks1-0/+2
Fix the warning from missing "clk.h" include which defines hi6220_register_clkdiv() function. drivers/clk/hisilicon/clkdivider-hi6220.c:102:12: warning: symbol 'hi6220_register_clkdiv' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: hisilicon: add CRG driver for hi3519 socJiancheng Xue3-0/+140
The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: hisilicon: export some hisilicon APIs to modulesJiancheng Xue2-15/+22
Change some arguments to constant type. Export some hisilicon APIs to modules. Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06reset: hisilicon: add reset controller driver for hisilicon SOCsJiancheng Xue4-0/+178
In most of hisilicon SOCs, reset controller and clock provider are combined together as a block named CRG (Clock and Reset Generator). This patch mainly implements the reset function. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03clk: hisilicon: Remove CLK_IS_ROOTStephen Boyd5-56/+56
This flag is a no-op now. Remove usage of the flag. Tested-by: Leo Yan <leo.yan@linaro.org> Cc: Bintian Wang <bintian.wang@huawei.com> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-17clk: Remove unneeded semicolonsJavier Martinez Canillas1-1/+1
There are cleary typo errors so can be removed. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Acked-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-03clk: Hi6220: separately build stub clock driverLeo Yan2-2/+9
The previous code, kernel builds Hi6220's common clock driver and stub clock driver together. Stub clock driver has introduced the dependency with CONFIG_MAILBOX, so kernel will not build Hi6220's common clock driver due ARM64's defconfig have not enabled CONFIG_MAILBOX by default. So separately build stub clock driver and common clock driver for Hi6220; and only let stub clock driver has the dependency with CONFIG_MAILBOX. Signed-off-by: Leo Yan <leo.yan@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-25clk: Hi6220: add stub clock driverLeo Yan3-2/+278
On Hi6220, there have some clocks which can use mailbox channel to send messages to power controller to change frequency; this includes CPU, GPU and DDR clocks. For dynamic frequency scaling, firstly need write the frequency value to SRAM region, and then send message to mailbox to trigger power controller to handle this requirement. This driver will use syscon APIs to pass SRAM memory region and use common mailbox APIs for channels accessing. This init driver will support cpu frequency change firstly. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-04clk: hisi: refine parameter checking for initLeo Yan1-8/+3
*of_iomap()* will check the device node pointer, and if the pointer is NULL it will return error code. So refine clock's init flow by checking the device node with this simple way; and polish a little for the print out message. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd4-8/+1
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
2015-07-28clk: fix some determine_rate implementationsBoris Brezillon1-1/+1
Some determine_rate implementations are not returning an error when they failed to adapt the rate according to the rate request. Fix them so that they return an error instead of silently returning 0. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon1-22/+17
Clock rates are stored in an unsigned long field, but ->determine_rate() (which returns a rounded rate from a requested one) returns a long value (errors are reported using negative error codes), which can lead to long overflow if the clock rate exceed 2Ghz. Change ->determine_rate() prototype to return 0 or an error code, and pass a pointer to a clk_rate_request structure containing the expected target rate and the rate constraints imposed by clk users. The clk_rate_request structure might be extended in the future to contain other kind of constraints like the rounding policy, the maximum clock inaccuracy or other things that are not yet supported by the CCF (power consumption constraints ?). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Jonathan Corbet <corbet@lwn.net> CC: Tony Lindgren <tony@atomide.com> CC: Ralf Baechle <ralf@linux-mips.org> CC: "Emilio López" <emilio@elopez.com.ar> CC: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Tero Kristo <t-kristo@ti.com> CC: Peter De Schrijver <pdeschrijver@nvidia.com> CC: Prashant Gaikwad <pgaikwad@nvidia.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Thierry Reding <thierry.reding@gmail.com> CC: Alexandre Courbot <gnurou@gmail.com> CC: linux-doc@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-omap@vger.kernel.org CC: linux-mips@linux-mips.org CC: linux-tegra@vger.kernel.org [sboyd@codeaurora.org: Fix parent dereference problem in __clk_determine_rate()] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> [sboyd@codeaurora.org: Folded in fix from Heiko for fixed-rate clocks without parents or a rate determining op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: hisilicon: Remove clk.h includeStephen Boyd4-8/+1
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. Also drop the clkdev.h include in files that aren't using it. Cc: Bintian Wang <bintian.wang@huawei.com> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-05clk: make several parent names constUwe Kleine-König3-39/+39
Since commit 2893c379461a ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04Merge branch 'clk-next-hi6220' into clk-nextMichael Turquette6-12/+505
Conflicts: drivers/clk/Kconfig
2015-06-04clk: hi6220: Clock driver support for Hisilicon hi6220 SoCBintian Wang6-1/+494
Add clock drivers for hi6220 SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. We add one divider clock for hi6220 because the divider in hi6220 also has a mask bit but it doesnot obey the rule defined by flag "CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by left shift fixed bits (e.g. 16 bits), so we add this divider clock to handle it. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Tyler Baker <tyler.baker@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-06-03clk: hisilicon: Remove __init for marking function prototypesBintian Wang1-11/+11
__init markings on function prototypes are useless, so remove them. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Tyler Baker <tyler.baker@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-05-15clk: hix5hd2: Silence sparse warningsStephen Boyd1-2/+3
drivers/clk/hisilicon/clk-hix5hd2.c:255:13: warning: symbol 'hix5hd2_clk_register_complex' was not declared. Should it be static? Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-13clk: don't use __initconst for non-const arraysUwe Kleine-König2-38/+38
The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-03clk: Add rate constraints to clocksTomeu Vizoso1-0/+2
Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
2014-12-04clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso1-1/+1
This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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