summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Expand)AuthorFilesLines
2014-01-22MIPS: Add support for interAptiv coresLeonid Yegoshin9-1/+12
2014-01-22MIPS: Add processor identifiers for the interAptiv processorsLeonid Yegoshin1-0/+2
2014-01-22MIPS: Add debugfs file to print the segmentation control registersSteven J. Hill2-0/+111
2014-01-22MIPS: Add support for FTLBsLeonid Yegoshin7-14/+155
2014-01-22MIPS: mm: Use the TLBINVF instruction to flush the VTLBLeonid Yegoshin1-6/+12
2014-01-22MIPS: Add function for flushing the TLB using the TLBINV instructionLeonid Yegoshin1-0/+13
2014-01-22MIPS: kernel: cpu-probe: Add support for probing proAptiv coresLeonid Yegoshin1-0/+8
2014-01-22MIPS: Add support for the proAptiv coresLeonid Yegoshin10-1/+13
2014-01-22MIPS: Add processor identifiers for the proAptiv processorsLeonid Yegoshin1-0/+2
2014-01-22MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLBLeonid Yegoshin1-1/+3
2014-01-22MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill4-0/+36
2014-01-22MIPS: features: Add initial support for TLBINVF capable coresLeonid Yegoshin3-0/+9
2014-01-22MIPS: mm: Move UNIQUE_ENTRYHI macro to a header fileMarkos Chandras3-8/+3
2014-01-22MIPS: Add missing bits for Config registersLeonid Yegoshin1-2/+38
2014-01-22MIPS: MT: proc: Add support for printing VPE and TC idsMarkos Chandras1-1/+8
2014-01-22MIPS: Malta: Remove ttyS2 serial for CMP platformsLeonid Yegoshin1-0/+2
2014-01-22MIPS: Add printing of ES bit for Imgtec cores when cache error occurs.Leonid Yegoshin1-8/+21
2014-01-22MIPS: GIC: Send IPIs using the GICSteven J. Hill1-0/+27
2014-01-22MIPS: MT: Mark existing TCs as presentMarkos Chandras1-0/+1
2014-01-22MIPS: mm: c-r4k: Panic if IL or DL fields have a reserved valueMarkos Chandras1-8/+16
2014-01-22MIPS: kernel: smp-cmp: MIPS MT code needs CONFIG_MIPS_MTMarkos Chandras1-0/+3
2014-01-22MIPS: BCM47XX: Fix some very confused types and data corruptionIlia Mirkin1-9/+9
2014-01-22MIPS: BCM47XX: add vectored interrupt supportHauke Mehrtens2-0/+24
2014-01-22MIPS: BCM47XX: add cpu-feature-overrides.hHauke Mehrtens1-0/+82
2014-01-22MIPS: BCM47XX: move constant array from stackHauke Mehrtens1-1/+1
2014-01-22MIPS: BCM47XX: add asmlinkage to plat_irq_dispatch()Hauke Mehrtens1-1/+1
2014-01-22MIPS: BCM47XX: update defconfigHauke Mehrtens1-580/+43
2014-01-22MIPS: BCM47XX: add EARLY_PRINTK_8250 supportHauke Mehrtens2-0/+11
2014-01-22MIPS: BCM47XX: Remove CFE supportHauke Mehrtens2-93/+0
2014-01-22MIPS: BCM47XX: only print SoC name in system type in cpuinfoHauke Mehrtens3-22/+13
2014-01-22MIPS: BCM63XX: drop SYS_HAS_CPU_MIPS32R1Jonas Gorski1-1/+0
2014-01-22MIPS: cpu-type: guard BMIPS variants with SYS_HAS_CPU_BMIPS*Jonas Gorski1-3/+10
2014-01-22MIPS: BCM47XX: select BMIPS CPUs for BCM47XX_SSBJonas Gorski1-0/+1
2014-01-22MIPS: BCM63XX: let the individual SoCs select the appropriate CPUsJonas Gorski2-1/+8
2014-01-22MIPS: BCM63XX: always register bmips smp opsJonas Gorski1-4/+2
2014-01-22MIPS: BMIPS: add a smp ops registration helperJonas Gorski3-1/+28
2014-01-22MIPS: BMIPS: extend BMIPS3300 to include BMIPS32Jonas Gorski1-4/+4
2014-01-22MIPS: BMIPS: select CPU_HAS_PREFETCHJonas Gorski1-0/+1
2014-01-22MIPS: BMIPS: select CPU_SUPPORTS_HIGHMEMJonas Gorski1-1/+1
2014-01-22MIPS: BMIPS: merge CPU options into one optionJonas Gorski1-41/+39
2014-01-22MIPS: BMIPS: change compile time checks to runtime checksJonas Gorski4-137/+235
2014-01-22MIPS: allow asm/cpu.h to be included from assemblyJonas Gorski1-0/+3
2014-01-22MIPS: BCM63XX: disable SMP also on BCM3368Jonas Gorski1-4/+4
2014-01-22MIPS: BCM63XX: add HSSPI platform device and register itJonas Gorski4-2/+60
2014-01-22MIPS: BCM63XX: add HSSPI IRQ and register offsetsJonas Gorski1-0/+18
2014-01-22MIPS: BCM63XX: setup the HSSPI clock rateJonas Gorski1-0/+18
2014-01-22MIPS: BCM63XX: expose the HSSPI clockJonas Gorski1-0/+24
2014-01-14MIPS: Support for 64-bit FP with O32 binariesPaul Burton19-236/+449
2014-01-14MIPS: Remove unused {en,dis}able_fpu macrosPaul Burton1-13/+0
2014-01-14MIPS: microMIPS: mfhc1 & mthc1 support for the FPU emulatorSteven J. Hill2-1/+9