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2014-07-22ARM: DRA7: hwmod: remove interrupts for DMANishanth Menon1-9/+0
DMA interrupts are now available in of, and the definitions are duplicates in hwmod. This prevents us from dynamically allocating interrupt resources for dma from devicetree. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-22ARM: OMAP2+: DMA: remove requirement of irq for platform-dma driverNishanth Menon2-2/+6
we have currently 2 DMA drivers that try to co-exist. drivers/dma/omap-dma.c which registers it's own IRQ and is device tree aware and uses arch/arm/plat-omap/dma.c instance created by arch/arm/mach-omap2/dma.c to maintain channel usage (omap_request_dma). Currently both try to register interrupts and mach-omap2/plat-omap dma.c attempts to use the IRQ number registered by hwmod to register it's own interrupt handler. Now, there is no reasonable way of static allocating DMA irq in GIC SPI when we use crossbar. However, since the dma_chan structure is freed as a result of IRQ not being present due to devm allocation, maintaining information of channel by platform code fails at a later point in time when that region of memory is reused. So, if hwmod does not indicate an IRQ number, then, assume that dma-engine will take care of the interrupt handling. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-21Merge tag 'for-v3.17/omap-clock-a' of ↵Tony Lindgren7-100/+154
git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.17/soc An OMAP clock cleanup series for 3.17 from Tero Kristo. This is in preparation for moving this code into drivers/clk/ti. Basic build, boot, and PM test logs are here: http://www.pwsan.com/omap/testlogs/clock-a-v3.17/20140717034329/
2014-07-16ARM: OMAP2+: clock/interface: remove some headers from clkt_iclk.c fileTero Kristo1-4/+4
Instead, copy the used constants from the header file to the source file. This allows the code to be migrated under drivers folder where we don't have access to the OMAP specific header files. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP2+: clock/dpll: remove unused header includes from dpll3xxx.cTero Kristo1-3/+0
Some of the machine specific header includes are no longer used, so remove these from the source file. This allows migration of the file under clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP2+: clock/dpll: remove unused header includes from clkt_dpll.cTero Kristo1-3/+0
Some of the machine specific header includes are no longer used, so remove these from the source file. This allows migration of the file under clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP2+: clock/interface: add a clk_features definition for idlest valueTero Kristo2-7/+12
Helps to get rid of some runtime cpu_is_x checks. This also allows eventual migration of the code under clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP2+: clock/dpll: add jitter correction behind clk_featuresTero Kristo3-2/+9
Currently DPLL code uses runtime cpu_is_343x checks to see if the DPLL has freqsel fields in its control register or not. Instead, add a new flag to the clk_features.flags and use this during runtime. Allows eventual move of the DPLL code under clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP2+: clock/dpll: convert bypass check to use clk_featuresTero Kristo3-12/+31
OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses clk_features data provided during boot. This avoids the need to use cpu_is_X type checks runtime, and allows us to eventually move the clock code under the clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP2+: clock/dpll: add private API for checking if DPLL is in bypassTero Kristo1-28/+32
Currently, same functionality is copy pasted in two locations. Instead, add a private API for this and get rid of some duplicated code. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP2+: clock: add fint values to the ti_clk_features structTero Kristo3-22/+39
These are SoC specific and get their init values based on the SoC type. Previously the values were hard coded within the DPLL clock code, but having them inside the clock features avoids runtime cpu_is_X type checks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP2+: clock: introduce ti_clk_features flagsTero Kristo3-0/+26
This shall be used to replace the cpu type checks around the clock code. Actual bit values will be introduced in patches later. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP4+: dpll44xx: remove cm-regbits-44xx.h and clock44xx.h includesTero Kristo1-2/+10
Instead, copy the used bitfield definitions to the source file. Done in preparation to migrate the clock implementation under clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-16ARM: OMAP4+: dpll: remove cpu_is_omap44xx checksTero Kristo1-4/+3
These are unnecessary, as the clock code is only used on OMAP4+ platforms through clock registrations. This also allows to eventually migrate the clock type implementation under clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-15Merge branch 'for-v3.17/cm-prm-cleanup' of ↵Tony Lindgren8-240/+329
https://github.com/t-kristo/linux-pm into omap-for-v3.17/soc
2014-07-11ARM: OMAP4+: clock: remove DEFINE_CLK_OMAP_HSDIVIDER macroTero Kristo1-25/+0
This clock type declaration is no longer used as all omap4+ SoC clock data has been moved to DT, thus remove it. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-07-09ARM: OMAP4: Ctrl module register define dietJoachim Eastwood4-2042/+33
The mach-omap2 directory contains full register defines for OMAP4 control module but only around 27 of those are used. There are is a total of 1795 register defines in four files with only 27 in use. That is pretty low usefulness ratio... I guess alot more was used when we had omap4 board files and mach-omap2 contained more drivers but this has now changed. Signed-off-by: Joachim Eastwood <manabian@gmail.com> [tony@atomide.com: updated to apply] Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-07-06Merge tag 'fixes-for-linus' of ↵Linus Torvalds23-59/+266
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "This week's arm-soc fixes: - A set of of OMAP patches that we had missed Tony's pull request of: * Reset fix for am43xx * Proper OPP table for omap5 * Fix for SoC detection of one of the DRA7 SoCs * hwmod updates to get SATA and OCP to work on omap5 (drivers merged in 3.16) * ... plus a handful of smaller fixes - sunxi needed to re-add machine specific restart code that was removed in anticipation of a watchdog driver being merged for 3.16, and it didn't make it in. - Marvell fixes for PCIe on SMP and a big-endian fix. - A trivial defconfig update to make my capri test board boot with bcm_defconfig again. ... and a couple of MAINTAINERS updates, one to claim new Keystone drivers that have been merged, and one to merge MXS and i.MX (both Freescale platforms). The largest diffs come from the hwmod code for omap5 and the re-add of the restart code on sunxi. The hwmod stuff is quite late at this point but it slipped through cracks repeatedly while coming up the maintainer chain and only affects the one SoC so risk is low" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: MAINTAINERS: Add few more Keystone drivers MAINTAINERS: merge MXS entry into IMX one ARM: sunxi: Reintroduce the restart code for A10/A20 SoCs ARM: mvebu: fix cpuidle implementation to work on big-endian systems ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup ARM: mvebu: move Armada 375 external abort logic as a quirk ARM: bcm: Fix bcm and multi_v7 defconfigs ARM: dts: dra7-evm: remove interrupt binding ARM: OMAP2+: Fix parser-bug in platform muxing code ARM: DTS: dra7/dra7xx-clocks: ATL related changes ARM: OMAP2+: drop unused function ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm ARM: dts: omap5: Update CPU OPP table as per final production Manual ARM: DRA722: add detection of SoC information ARM: dts: Enable twl4030 off-idle configuration for selected omaps ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
2014-07-05Merge tag 'arm64-fixes' of ↵Linus Torvalds5-6/+9
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull ARM64 fixes from Catalin Marinas: - Exception level check at boot time (for completeness, not triggering any bug before) - I/D-cache synchronisation logic for huge pages - Config symbol typo * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: fix el2_setup check of CurrentEL arm64: mm: Make icache synchronisation logic huge page aware arm64: mm: Fix horrendous config typo
2014-07-05Merge tag 'mvebu-fixes-3.16-2' of git://git.infradead.org/linux-mvebu into fixesOlof Johansson4-18/+47
mvebu fixes for v3.16 (round #2) - mvebu - Fix PCIe deadlock now that SMP is enabled - Fix cpuidle for big-endian systems * tag 'mvebu-fixes-3.16-2' of git://git.infradead.org/linux-mvebu: ARM: mvebu: fix cpuidle implementation to work on big-endian systems ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup ARM: mvebu: move Armada 375 external abort logic as a quirk Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-05ARM: sunxi: Reintroduce the restart code for A10/A20 SoCsMaxime Ripard1-0/+77
This partly reverts commits 553600502b84 (ARM: sunxi: Remove reset code from the platform) and 5e669ec583e2 (ARM: sunxi: Remove init_machine callback) for the sun4i, sun5i and sun7i families. This is needed because the watchdog counterpart of these commits was dropped, and didn't make it into 3.16. In order to still be able to reboot the board, we need to reintroduce that code. Of course, the long term view is still to get rid of that code in mach-sunxi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-05Merge tag 'omap-for-v3.16/fixes-against-rc1' of ↵Olof Johansson16-39/+139
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes Merge OMAP fixes from Tony Lindgren: Fixes for omaps for issues discovered during the merge window and enabling of a few features that had to wait for the driver dependencies to clear. The fixes included are: - Fix am43xx hard reset flags - Fix SoC detection for DRA722 - Fix CPU OPP table for omap5 - Fix legacy mux parser bug if requested muxname is a prefix of multiple mux entries - Fix qspi interrupt binding that relies on the irq crossbar that has not yet been enabled - Add missing phy_sel for am43x-epos-evm - Drop unused gic_init_irq() that is no longer needed And the enabling of features that had driver dependencies are: - Change dra7 to use Audio Tracking Logic clock instead of a fixed clock now that the clock driver for it has been merged - Enable off idle configuration for selected omaps as all the kernel dependencies for device tree based booting are finally merged as this is needed to get the automated PM tests working finally with device tree based booting - Add hwmod entry for ocp2scp3 for omap5 to get sata working as all the driver dependencies are now in the kernel and this patch fell through the cracks during the merge window * tag 'omap-for-v3.16/fixes-against-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: dra7-evm: remove interrupt binding ARM: OMAP2+: Fix parser-bug in platform muxing code ARM: DTS: dra7/dra7xx-clocks: ATL related changes ARM: OMAP2+: drop unused function ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm ARM: dts: omap5: Update CPU OPP table as per final production Manual ARM: DRA722: add detection of SoC information ARM: dts: Enable twl4030 off-idle configuration for selected omaps ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
2014-07-04arm64: fix el2_setup check of CurrentELMarc Zyngier3-4/+6
The CurrentEL system register reports the Current Exception Level of the CPU. It doesn't say anything about the stack handling, and yet we compare it to PSR_MODE_EL2t and PSR_MODE_EL2h. It works by chance because PSR_MODE_EL2t happens to match the right bits, but that's otherwise a very bad idea. Just check for the EL value instead. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> [catalin.marinas@arm.com: fixed arch/arm64/kernel/efi-entry.S] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-07-04ARM: OMAP3: control: isolate control module init to its own functionTero Kristo4-12/+19
Control module related PM initializations are now moved within control module driver. Done in preparation to isolate the code to its own driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP3: PRM: move modem reset and iva2 idle to PRM driverTero Kristo2-15/+7
Done in preparation to move PRM into its own driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP3: control: add API for setting up the modem padsTero Kristo3-14/+28
This patch moves the functionality from PM core to control driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP3: PRM: move PRM init code from PM core to the driverTero Kristo3-70/+92
Helps to isolate the PRM driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP24xx: PRM: add API for clearing wakeup status bitsTero Kristo3-18/+32
This helps to isolate the PRM into its own driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP3: PRM: add API for saving PRM scratchpad contentsTero Kristo3-9/+12
This isolates the PRM register access within the PRM driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP3: PRM: add API for checking and clearing cold reset statusTero Kristo3-5/+22
This isolates the PRM register access within the PRM driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP3: PRM: move modem reset to PRM driverTero Kristo3-4/+17
This is a more proper isolation of the code. Done in preparation of making PRM an individual driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP3: PRM: move iva reset to PRM driverTero Kristo3-48/+47
This is a more proper isolation of the code. Done in preparation of making PRM an individual driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04ARM: OMAP3: PRM: move prcm wakeup helper to prm driverTero Kristo3-56/+64
Done in preparation to make the prm an individual driver. Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-07-04arm64: mm: Make icache synchronisation logic huge page awareSteve Capper1-1/+2
The __sync_icache_dcache routine will only flush the dcache for the first page of a compound page, potentially leading to stale icache data residing further on in a hugetlb page. This patch addresses this issue by taking into consideration the order of the page when flushing the dcache. Reported-by: Mark Brown <broonie@linaro.org> Tested-by: Mark Brown <broonie@linaro.org> Signed-off-by: Steve Capper <steve.capper@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@vger.kernel.org> # v3.11+
2014-07-04arm64: mm: Fix horrendous config typoSteve Capper1-1/+1
The define ARM64_64K_PAGES is tested for rather than CONFIG_ARM64_64K_PAGES. Correct that typo here. Signed-off-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-07-04ptrace,x86: force IRET path after a ptrace_stop()Tejun Heo1-0/+16
The 'sysret' fastpath does not correctly restore even all regular registers, much less any segment registers or reflags values. That is very much part of why it's faster than 'iret'. Normally that isn't a problem, because the normal ptrace() interface catches the process using the signal handler infrastructure, which always returns with an iret. However, some paths can get caught using ptrace_event() instead of the signal path, and for those we need to make sure that we aren't going to return to user space using 'sysret'. Otherwise the modifications that may have been done to the register set by the tracer wouldn't necessarily take effect. Fix it by forcing IRET path by setting TIF_NOTIFY_RESUME from arch_ptrace_stop_needed() which is invoked from ptrace_stop(). Signed-off-by: Tejun Heo <tj@kernel.org> Reported-by: Andy Lutomirski <luto@amacapital.net> Acked-by: Oleg Nesterov <oleg@redhat.com> Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: stable@vger.kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-07-01Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds6-17/+18
Pull KVM fixes from Paolo Bonzini: "A bunch of one-liners (except the s390 one). The two more serious bugs ("KVM: SVM: Fix CPL export via SS.DPL" and "KVM: s390: add sie.h uapi header file to Kbuild and remove header dependency") were introduced in the 3.16 merge window" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: SVM: Fix CPL export via SS.DPL KVM: s390: add sie.h uapi header file to Kbuild and remove header dependency MIPS: KVM: Fix memory leak on VCPU KVM: x86: preserve the high 32-bits of the PAT register kvm: fix wrong address when writing Hyper-V tsc page KVM: x86: Increase the number of fixed MTRR regs to 10
2014-06-30ARM: mvebu: fix cpuidle implementation to work on big-endian systemsThomas Petazzoni3-8/+28
On Marvell Armada XP, when a CPU comes back from deep idle state of cpuidle, it restarts its execution at armada_370_xp_cpu_resume(), which puts back the CPU into the coherency, and then calls the generic cpu_resume() function. While this works on little-endian configurations, it doesn't work on big-endian configurations because the CPU restarts in little-endian, and therefore must be switched back to big-endian to operate properly. To achieve this, a 'setend be' instruction must be executed in big-endian configurations. However, the ARM_BE8() macro that is used to implement nice compile-time conditional for ARM LE vs. ARM BE8 is not easily usable in inline assembly. Therefore, this patch moves the armada_370_xp_cpu_resume() C function, which was anyway just a block of inline assembly, into a proper pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be) instruction. Without this patch, an Armada XP big endian configuration with cpuidle enabled fails to boot, as it hangs as soon as one of the CPU hits the deep idle state. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanupThomas Petazzoni1-6/+6
Commit 497a92308af8e9385fa3d135f7f416a997e4b93b ("ARM: mvebu: implement L2/PCIe deadlock workaround") introduced some logic in coherency.c to adjust the PL310 cache controller Device Tree node of Armada 375 and Armada 38x platform to include the 'arm,io-coherent' property if the system is running with hardware I/O coherency enabled. However, with the L2CC driver cleanup done by Russell King, the initialization of the L2CC driver has been moved earlier, and is now part of the init_IRQ() ARM function in arch/arm/kernel/irq.c. Therefore, calling coherency_init() in ->init_time() is now too late, as the Device Tree property gets added too late (after the L2CC driver has been initialized). In order to fix this, this commit removes the ->init_time() callback use in board-v7.c and replaces it with an ->init_irq() callback. We therefore no longer use the default ->init_irq() callback, but we now use the default ->init_time() callback. In this newly introduced ->init_irq() callback, we call irqchip_init() which is the default behavior when ->init_irq() isn't defined, and then do the initialization related to the coherency: SCU, coherency fabric, and mvebu-mbus (which is needed to start secondary CPUs). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30ARM: mvebu: move Armada 375 external abort logic as a quirkThomas Petazzoni1-4/+13
In preparation to a small re-organization of the initialization sequence in board-v7.c, this commit moves the registration of the custom external abort handler on Armada 375 later in the boot sequence, and makes it more similar to the other quirks that we already have. There is indeed no need to register this abort handler particularly early, it simply needs to be registered before switching to userspace. In addition to this, this commit makes the registration of the custom abort handler conditional on Armada 375 Z1, because Armada 375 A0 and later iterations are not affected by the issue. This commit was tested on both Armada 375 Z1 and Armada 375 A0 platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1402585772-10405-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30Merge commit '33b458d276bb' into kvm-masterPaolo Bonzini1-0/+1
2014-06-30KVM: SVM: Fix CPL export via SS.DPLJan Kiszka1-0/+1
We import the CPL via SS.DPL since ae9fedc793. However, we fail to export it this way so far. This caused spurious guest crashes, e.g. of Linux when accessing the vmport from guest user space which triggered register saving/restoring to/from host user space. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-06-30Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds5-6/+42
Pull ARM fixes from Russell King: "Another round of ARM fixes. The largest change here is the L2 changes to work around problems for the Armada 37x/380 devices, where most of the size comes down to comments rather than code. The other significant fix here is for the ptrace code, to ensure that rewritten syscalls work as intended. This was pointed out by Kees Cook, but Will Deacon reworked the patch to be more elegant. The remainder are fairly trivial changes" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: 8087/1: ptrace: reload syscall number after secure_computing() check ARM: 8086/1: Set memblock limit for nommu ARM: 8085/1: sa1100: collie: add top boot mtd partition ARM: 8084/1: sa1100: collie: revert back to cfi_probe ARM: 8080/1: mcpm.h: remove unused variable declaration ARM: 8076/1: mm: add support for HW coherent systems in PL310 cache
2014-06-29ARM: 8087/1: ptrace: reload syscall number after secure_computing() checkWill Deacon1-3/+4
On the syscall tracing path, we call out to secure_computing() to allow seccomp to check the syscall number being attempted. As part of this, a SIGTRAP may be sent to the tracer and the syscall could be re-written by a subsequent SET_SYSCALL ptrace request. Unfortunately, this new syscall is ignored by the current code unless TIF_SYSCALL_TRACE is also set on the current thread. This patch slightly reworks the enter path of the syscall tracing code so that we always reload the syscall number from current_thread_info()->syscall after the potential ptrace traps. Acked-by: Kees Cook <keescook@chromium.org> Tested-by: Kees Cook <keescook@chromium.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-29ARM: 8086/1: Set memblock limit for nommuLaura Abbott1-0/+1
Commit 1c2f87c (ARM: 8025/1: Get rid of meminfo) changed find_limits to use memblock_get_current_limit for calculating the max_low pfn. nommu targets never actually set a limit on memblock though which means memblock_get_current_limit will just return the default value. Set the memblock_limit to be the end of DDR to make sure bounds are calculated correctly. Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-29ARM: 8085/1: sa1100: collie: add top boot mtd partitionAndrea Adami1-0/+5
The CFI mapping is now perfect so we can expose the top block, read only. There isn't much to read, though, just the sharpsl_params values. Signed-off-by: Andrea Adami <andrea.adami@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-29ARM: 8084/1: sa1100: collie: revert back to cfi_probeAndrea Adami1-1/+1
Reverts commit d26b17edafc45187c30cae134a5e5429d58ad676 ARM: sa1100: collie.c: fall back to jedec_probe flash detection Unfortunately the detection was challenged on the defective unit used for tests: one of the NOR chips did not respond to the CFI query. Moreover that bad device needed extra delays on erase-suspend/resume cycles. Tested personally on 3 different units and with feedback of two other users. Signed-off-by: Andrea Adami <andrea.adami@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-29ARM: 8080/1: mcpm.h: remove unused variable declarationNicolas Pitre1-2/+0
The sync_phys variable has been replaced by link time computation in mcpm_head.S before the code was submitted upstream. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-29ARM: 8076/1: mm: add support for HW coherent systems in PL310 cacheThomas Petazzoni1-0/+31
When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe controller and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note that technically speaking, a fully coherent system wouldn't require any of the other .outer_cache operations. However, in practice, when booting secondary CPUs, these are not yet coherent, and therefore a set of cache maintenance operations are necessary at this point. This explains why we keep the other .outer_cache operations and only ->sync is disabled. While in theory any write to a PL310 register could cause the deadlock, in practice, disabling ->sync is sufficient to workaround the deadlock, since the other cache maintenance operations are only used in very specific situations. Contrary to previous versions of this patch, this new version does not simply NULL-ify the ->sync member, because the l2c_init_data structures are now 'const' and therefore cannot be modified, which is a good thing. Therefore, this patch introduces a separate l2c_init_data instance, called of_l2c310_coherent_data. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-28Merge branch 'x86/urgent' of ↵Linus Torvalds11-124/+297
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Peter Anvin: "A pile of fixes related to the VDSO, EFI and 32-bit badsys handling. It turns out that removing the section headers from the VDSO breaks gdb, so this puts back most of them. A very simple typo broke rt_sigreturn on some versions of glibc, with obviously disastrous results. The rest is pretty much fixes for the corresponding fallout. The EFI fixes fixes an arithmetic overflow on 32-bit systems and quiets some build warnings. Finally, when invoking an invalid system call number on x86-32, we bypass a bunch of handling, which can make the audit code oops" * 'x86/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: efi-pstore: Fix an overflow on 32-bit builds x86/vdso: Error out in vdso2c if DT_RELA is present x86/vdso: Move DISABLE_BRANCH_PROFILING into the vdso makefile x86_32, signal: Fix vdso rt_sigreturn x86_32, entry: Do syscall exit work on badsys (CVE-2014-4508) x86/vdso: Create .build-id links for unstripped vdso files x86/vdso: Remove some redundant in-memory section headers x86/vdso: Improve the fake section headers x86/vdso2c: Use better macros for ELF bitness x86/vdso: Discard the __bug_table section efi: Fix compiler warnings (unused, const, type)
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