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2018-05-30ARM: dts: aspeed: Fix hwrng register addressdev-4.13Joel Stanley2-4/+4
The register address should be the full address of the rng, not the offset from the start of the SCU. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18ARM: dts: aspeed: Use 24MHz fixed clock for pwmLei YU2-2/+2
The aspeed pwm driver always sets the clock source to 24MHz, specify the fixed clock in device tree to make sure the driver is using the correct clock frequency to calculate the fan speed. OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11fsi/fsi-master-gpio: Add "no-gpio-delays" optionBenjamin Herrenschmidt3-0/+3
This adds support for an optional device-tree property that makes the driver skip all the delays around clocking the GPIOs and set it in the device-tree of common POWER9 based OpenPower platforms. This useful on chips like the AST2500 where the GPIO block is running at a fairly low clock frequency (25Mhz typically). In this case, the delays are unnecessary and due to the low precision of the timers, actually quite harmful in terms of performance. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11ARM: dts: aspeed-g5: Clean up sio registersJoel Stanley1-19/+18
Remove the unnecessary reg property. Drop the 'rx' in the name, as this refers to a quirk in the datasheet and is not useful. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-07ARM: configs: aspeed: Add watchdog sysfsEddie James2-0/+2
This kernel config adds sysfs entries for watchdog devices. This is needed in order to access the bootstatus sysfs file that will indicate whether or not the BMC has tripped the watchdog and subsequently switched sides. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-07ARM: dts: aspeed: Move random number deviceJoel Stanley2-12/+12
Move the node out from under the syscon/simple-mfd. Being a child of this node causes the driver to fail to probe, as platform_get_resource returns NULL due to dev->num_resources being zero. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-01ARM: dts: romulus: Enable the GFX IPJoel Stanley1-0/+12
The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and enables the GFX node. OpenBMC-Staging-Count: 1 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-26ARM: dts: aspeed: Add Inventec Lanyang BMCBrian Yang2-0/+332
The Inventec Lanyang is Power 9 platform with ast2500 BMC. Tested-by: Brian Yang <yang.brianc.w@inventec.com> Signed-off-by: Brian Yang <yang.brianc.w@inventec.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-26ARM: dts: aspeed: Add Portwell Neptune machineAmithash Prasad2-1/+161
Initial introduction of Portwell Neptune family equipped with Aspeed 2500 BMC SoC. Neptune is a x86 server development kit with a ASPEED ast2500 BMC manufactured by Portwell. Specifically, This adds the neptune platform device tree file including the flash layout used by the neptune machines. Signed-off-by: Amithash Prasad <amithash@fb.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20ARM: dts: aspeed-g5: Add DAC MUX userspace controlJoel Stanley1-2/+6
This exposes SCU2C "Misc. Control Register" bits 16 and 17 which control the input to the VGA DAC. They are used to select which graphics device drives the analog output: 00: VGA mode (default) 01: Graphics CRT mode 10: Pass-through mode from Video input port-A 11: Pass-through mode from Video input port-B We don't need the reg property, so remove it and the unit name. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20ARM: dts: witherspoon: Enable the GFX IPJoel Stanley1-0/+8
The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20ARM: dts: ast2500-evb: Enable the GFX IPJoel Stanley1-1/+20
The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20ARM: dts: aspeed-g5: Add resets and clocks to GFX nodeJoel Stanley1-0/+4
The ast2500 has a reset for the CRT device that must be deasserted before it can be used. Similarly it has a clock gate for a clock called D1CLK that must be set to running. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-19dts: aspeed-g5: Expose SuperIO scratch registersAndrew Jeffery1-0/+88
OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-19dts: aspeed-g5: Expose VGA scratch registersAndrew Jeffery1-0/+48
OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-19Merge tag 'drm-for-v4.14' into dev-4.13Joel Stanley8-120/+64
This is the DRM tree that was merged into the mainline 4.14 kernel. The ASPEED GFX DRM driver requires functionaliy that was included in this tree, so we merge it back into the 4.13 OpenBMC tree. This should have no impact on other parts of the BMC. Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-17ARM: dts: aspeed: romulus: Add id-button gpio keyLei YU1-0/+6
OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: npcm: enable L2 cache in NPCM7xx architectureTomer Maimon1-0/+2
This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure. At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments regarding the flags use in L2 cache module. - https://www.spinics.net/lists/arm-kernel/msg613212.html After checking again the L2 cache use in the NPCM7xx, the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE and it is done in the device tree: https://patchwork.kernel.org/patch/10063497/ L2 cache flag mask allowed all the flag option. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit d893c4de012ad586400d9ccf5143884eafd8d841) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: npcm: modify configuration for the NPCM7xx BMC.Tomer Maimon2-30/+13
Modify configuration and MakeFile for the Nuvoton NPCM and NPCM7xx BMC. [arnd: took this one late, since it fixes some build problems with the original commit] Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit cd903711fd9dce808b5cc07e509135886d962b0c) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify Nuvoton NPCM7xx device tree structureTomer Maimon3-178/+190
Modify Nuvoton NPCM7xx device tree structure by adding nuvoton common nNPCM7xx device tree structure that include all common modules. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 518d2f43c358da2072948f64df99b1bd417288dc) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify Makefile NPCM750 configuration nameTomer Maimon1-1/+1
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 82e9f1d1f87d23ae943f8508a720f482bc2de256) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify clock binding in NPCM750 device treeTomer Maimon1-14/+44
Modify clock binding in a common device tree for all Nuvoton NPCM750 BMCs. Modify NPCM750 modules clock numbers accourding the new clock driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 016c366f505f96dce2a4d0e1e9075fe6e0dfad3e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify timer register size in NPCM750 device treeTomer Maimon1-1/+1
Modify timer register size in a common device tree for all Nuvoton NPCM750 BMCs. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 4828b20a0b89efba524eb34b3234d98683dbe108) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify UART compatible name in NPCM750 device treeTomer Maimon1-4/+4
Modify UART compatible name in a common device tree for all Nuvoton NPCM750 BMCs. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 33a5365900e9cf914cd1d2bdde1457b79b3e9ed9) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: add watchdog device to NPCM750 device treeTomer Maimon2-0/+28
Add watchdog device node to a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 1c4937eec91426014247b9ae8cb3f04935cd4865) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: add Nuvoton NPCM750 device treeBrendan Higgins3-0/+202
Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit d6bdd009c21db3f677dd1d1bbb8c20bc819074bc) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: npcm: add basic support for Nuvoton BMCsBrendan Higgins7-0/+172
Adds basic support for the Nuvoton NPCM750 BMC. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 7bffa14c9aed5f788d3126271f0fd8758fbd129e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-28ARM: dts: aspeed: Describe random number deviceJoel Stanley2-0/+14
There is a random number generator that updates a register in the SCU every second. This is compatible with the timeriomem rng driver in the kernel. From the timeriomem_rng bindings: quality: estimated number of bits of true entropy per 1024 bits read from the rng. Defaults to zero which causes the kernel's default quality to be used instead. Note that the default quality is usually zero which disables using this rng to automatically fill the kernel's entropy pool. As to the recommended value for us to use: Rick Altherr <raltherr@google.com> wrote: > Quality is #bit of entropy per 1000 bits read. 100 is a > conservative value that was suggested by those in the know. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-13ARM: dts: aspeed: witherspoon: set alternate bootEddie James1-0/+4
Set watchdog 2 to boot from the alternate flash chip when the watchdog timer expires and the system is reset. This enables "brick protection." OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-07Revert "ARM: dts: power9-cfam: Update OCC hwmon compatible"Eddie James1-2/+3
This reverts commit f370fa626a127aec50801dafcd595a2b5a47e482. The dts properties were correct for the OCC driver. OpenBMC-Staging-Count: 1 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-02powerpc/44x/fsp2: Add irq error handlersIvan Mikhaylov1-1/+204
Add irq error handlers for cmu, plb, opb, mcue, conf with debug information output in case of problems. Signed-off-by: Ivan Mikhaylov <ivan@de.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> (cherry picked from commit 7813043e1bbcea764c86ef2fcf43aeae2b0e240d) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-02powerpc/44x/fsp2: tvsense workaround for dd1Ivan Mikhaylov1-0/+17
TVSENSE(temperature and voltage sensors) reset is blocked (clock gated) by the POR default of the TVS sleep config bit. As a consequence, TVSENSE will provide erratic sensor values, which may result in spurious (parity) errors recorded in the CMU FIR and leading to erroneous interrupt requests once the CMU interrupt is unmasked. Purpose of this to set up CMU in working state in any cases even in case of parity errors. Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Ivan Mikhaylov <ivan@de.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> (cherry picked from commit 50f01c57d700cce04a9dc87bc55db2e283f57212) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-02powerpc/44x/fsp2: Interrupt handling setupIvan Mikhaylov1-0/+37
* clear out any possible plb6 errors * board interrupt handling setup within l2 reg set * fsp2 parity error setup All those points are needed for correct interrupt handling on board level including error handling report. Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Ivan Mikhaylov <ivan@de.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> (cherry picked from commit 9c4c374676a12db4a452534f3347323d35c32d1a) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-02powerpc/44x/fsp2: Add fsp2 headersIvan Mikhaylov1-0/+272
Add cmu, plbX, l2, ddr3/4, crcs register definitions. Add mfcmu, mtcmu functions for indirect access to cmu. Add mtl2, mfl2 same for l2 cache core reg set. Signed-off-by: Ivan Mikhaylov <ivan@de.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> (cherry picked from commit 494d82ceae7f3b9fdb5154b4469e5bb22f56040b) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-22ARM: dts: aspeed: Add Qualcomm Centriq 2400 REP BMCKen Chen2-0/+226
The Qualcomm Centriq 2400 REP (Reference Evaluation Platform) is an aarch64 Armv8 server platform with an ast2520 BMC. Signed-off-by: Ken Chen <chen.kenyy@inventec.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-22ARM: dts: aspeed-palmetto: Enable rear UARTJoel Stanley1-0/+15
The Palmetto BMC has a UART connected to a RS-232 transceiver designed to be used as a serial console for the host processor. It appears as a D-sub connector on the back of the chassis. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-21ARM: dts: aspeed: Add LPC reset controller nodeJoel Stanley2-0/+20
On both the ast2400 and ast2500 SoCs, the LPC reset controller is required to bring the UARTs out of reset without waiting for the LPC reset to be deasserted. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-13ARM: dts: aspeed: Add LPC clock phandlesJoel Stanley2-0/+2
The LPC device uses LCLK. OpenBMC-Staging-Count: 1 Tested-by: Lei YU <mine260309@gmail.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-08ARM: dts: power9-cfam: Update OCC hwmon compatibleJoel Stanley1-3/+2
The newer version of the driver has a different compatible string. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-08ARM: dts: aspeed: Sync G4 and G5 dtsJoel Stanley1-4/+3
This addresses some differences in the two device trees that make them hard to compare. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-08ARM: dts: aspeed-g5: Fix IPMI BT node addressJoel Stanley1-2/+2
The address was incorrect. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-08ARM: dts: aspeed-g4: Add reset phandles to ADC and PWMJoel Stanley1-0/+2
OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-06ARM: configs: aspeed: Update defconfigsJoel Stanley2-20/+91
This adds options that are required to boot and test parts of OpenBMC userspace. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-05ARM: dts: palmetto: Enable mbox and occ-hwmon nodesJoel Stanley1-0/+20
The mbox driver and the OCC hwmon driver are both not upstream. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-05ARM: dts: palmetto: Add LEDs and GPIO keysJoel Stanley1-0/+27
These describe the front panel LEDs that are present on a Palmetto chassis, and the checkstop GPIO that comes from the Power8 CPU to indicate a host error. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-05ARM: dts: aspeed: Add Palmetto hogsJoel Stanley1-0/+157
This is the ugly hog patch Andrew cooked up several months ago when we had issues with the post-1.0 OpenBMC branch on Palmetto. The idea was these hogs were to make it into userspace. No one has taken on that work, so we will do it in the kernel for now. There are also some pinmux hogs, where the default mode of the IP block is configured. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-05ARM: dts: aspeed: Enable IPMI BT node on OpenPower machinesJoel Stanley4-0/+16
These BMC systems require this device to communicate with the host. OpenBMC-Staging-Count: 2 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-02-05ARM: dts: aspeed: Add IPMI BT nodeJoel Stanley2-0/+14
The IPMI BT device part of the LPC interface and is used for communication with the host processor. OpenBMC-Staging-Count: 2 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-01-30ARM: dts: aspeed-g5: Correct VUART IRQ numberJoel Stanley1-1/+1
This should have always been 8. Fixes: db4d6d9d80fa ("ARM: dts: aspeed: Correctly order UART nodes") Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-01-30ARM: dts: aspeed-g4: Correct VUART IRQ numberJoel Stanley1-1/+1
This should have always been 8. Fixes: db4d6d9d80fa ("ARM: dts: aspeed: Correctly order UART nodes") Cc: stable@vger.kernel.org Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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