BMC/Intel-BMC/linux.git - Intel OpenBMC Linux kernel source tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2015-06-21	MIPS: Pistachio: Support 8250-based early printk	Ezequiel Garcia	1	-0/+2
2015-06-21	MIPS: BMIPS: dts: Add uart device nodes to bcm7xxx platforms	Jaedon Shin	8	-0/+136
2015-06-21	MIPS: BMIPS: Add support for Broadcom BCM97435SVMB	Florian Fainelli	3	-0/+65
2015-06-21	MIPS: BMIPS: Add BCM7435 dtsi	Florian Fainelli	1	-0/+239
2015-06-21	MIPS: BCM63xx: Utilize asm/bmips-spaces.h	Florian Fainelli	1	-1/+1
2015-06-21	MIPS: BMIPS: Define BMIPS_FIXADDR_TOP in asm/bmips-spaces.h	Florian Fainelli	2	-1/+8
2015-06-21	MIPS: ingenic: Initial MIPS Creator CI20 support	Paul Burton	4	-0/+211
2015-06-21	MIPS: ingenic: Initial JZ4780 support	Paul Burton	8	-6/+134
2015-06-21	MIPS: JZ4740: use Ingenic SoC UART driver	Paul Burton	11	-120/+28
2015-06-21	MIPS: JZ4740: only detect RAM size if not specified in DT	Paul Burton	3	-1/+10
2015-06-21	MIPS: JZ4740: remove clock.h	Paul Burton	3	-27/+3
2015-06-21	MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu	Paul Burton	4	-99/+1
2015-06-21	MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu	Paul Burton	1	-13/+0
2015-06-21	MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu	Paul Burton	1	-16/+0
2015-06-21	MIPS,clk: migrate JZ4740 to common clock framework	Paul Burton	9	-968/+32
2015-06-21	MIPS: JZ4740: replace use of jz4740_clock_bdata	Paul Burton	3	-4/+29
2015-06-21	MIPS: JZ4740: Call jz4740_clock_init earlier	Paul Burton	3	-2/+5
2015-06-21	MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip	Paul Burton	4	-204/+2
2015-06-21	MIPS: JZ4740: support newer SoC interrupt controllers	Paul Burton	1	-0/+9
2015-06-21	MIPS: JZ4740: Avoid JZ4740-specific naming	Paul Burton	3	-16/+16
2015-06-21	MIPS: JZ4740: read intc base address from DT	Paul Burton	1	-3/+6
2015-06-21	MIPS: JZ4740: define IRQ numbers based on number of intc IRQs	Paul Burton	1	-3/+7
2015-06-21	MIPS: JZ4740: support >32 interrupts	Paul Burton	1	-25/+46
2015-06-21	MIPS: JZ4740: Remove jz_intc_base global	Paul Burton	1	-8/+31
2015-06-21	MIPS: JZ4740: drop intc debugfs code	Paul Burton	1	-42/+0
2015-06-21	MIPS: JZ4740: register an irq_domain for the interrupt controller	Paul Burton	1	-0/+6
2015-06-21	MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT	Paul Burton	1	-1/+6
2015-06-21	MIPS: JZ4740: probe interrupt controller via DT	Paul Burton	4	-5/+18
2015-06-21	MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c	Paul Burton	3	-4/+11
2015-06-21	MIPS: JZ4740: use generic plat_irq_dispatch	Paul Burton	1	-12/+0
2015-06-21	MIPS: JZ4740: probe CPU interrupt controller via DT	Paul Burton	2	-2/+9
2015-06-21	MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.	Ralf Baechle	11	-225/+51
2015-06-21	MIPS: JZ4740: require & include DT	Paul Burton	6	-0/+43
2015-06-21	MIPS: ingenic: Add newer vendor IDs	Paul Burton	2	-3/+7
2015-06-21	MIPS: JZ4740: introduce CONFIG_MACH_INGENIC	Paul Burton	4	-9/+13
2015-06-21	MIPS: DEC: Update CPU overrides	Maciej W. Rozycki	1	-0/+16
2015-06-21	MIPS: netlogic: remove unnecessary MTD partition probe specification	Brian Norris	1	-3/+0
2015-06-21	MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation	Maciej W. Rozycki	1	-2/+2
2015-06-21	MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'	Maciej W. Rozycki	3	-7/+8
2015-06-21	MIPS: tlb-r3k: Also invalidate wired TLB entries on boot	Maciej W. Rozycki	1	-11/+13
2015-06-21	MIPS: dump_tlb: Take XPA into account	James Hogan	1	-5/+13
2015-06-21	MIPS: dump_tlb: Take RI/XI bits into account	James Hogan	1	-7/+20
2015-06-21	MIPS: dump_tlb: Take EHINV bit into account	James Hogan	1	-0/+3
2015-06-21	MIPS: dump_tlb: Take global bit into account	James Hogan	2	-3/+12
2015-06-21	MIPS: dump_tlb: Make use of EntryLo bit definitions	James Hogan	2	-12/+12
2015-06-21	MIPS: dump_tlb: Refactor TLB matching	James Hogan	1	-30/+35
2015-06-21	MIPS: dump_tlb: Use tlbr hazard macros	James Hogan	1	-8/+3
2015-06-21	MIPS: mipsregs.h: Add EntryLo bit definitions	James Hogan	1	-0/+22
2015-06-21	MIPS: hazards: Add hazard macros for tlb read	James Hogan	1	-0/+52
2015-06-21	MIPS: Add SysRq operation to dump TLBs on all CPUs	James Hogan	2	-0/+78