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path: root/arch/x86/oprofile/op_model_amd.c
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2013-09-04oprofilefs_create_...() do not need superblock argumentAl Viro1-7/+7
same story as with oprofilefs_mkdir() Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-09-04oprofilefs_mkdir() doesn't need superblock argumentAl Viro1-2/+2
it's always equal to ->d_sb of the second argument (parent dentry), due to either being literally that, or ->d_sb of parent's parent. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-09-04oprofile: don't bother with passing superblock to ->create_files()Al Viro1-12/+12
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2012-07-05perf/x86/amd: Unify AMD's generic and family 15h pmusRobert Richter1-2/+2
There is no need for keeping separate pmu structs. We can enable amd_{get,put}_event_constraints() functions also for family 15h event. The advantage is that there is only a single pmu struct for all AMD cpus. This patch introduces functions to setup the pmu to enabe core performance counters or counter constraints. Also, cpuid checks are used instead of family checks where possible. Thus, it enables the code independently of cpu families if the feature flag is set. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1340217996-2254-4-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
2011-10-10perf, x86: Implement IBS initializationRobert Richter1-197/+0
This patch implements IBS feature detection and initialzation. The code is shared between perf and oprofile. If IBS is available on the system for perf, a pmu is setup. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1316597423-25723-3-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-10-10perf, x86: Share IBS macros between perf and oprofileRobert Richter1-34/+3
Moving IBS macros from oprofile to <asm/perf_event.h> to make it available to perf. No additional changes. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1316597423-25723-2-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-05-30oprofile, x86: Add comments to IBS LVT offset initializationRobert Richter1-4/+9
Adding a comment in the code as IBS LVT setup is not obvious at all ... Signed-off-by: Robert Richter <robert.richter@amd.com>
2011-05-20oprofile, x86: Enable preemption during pci device setup in IBS initRobert Richter1-41/+54
IBS initialization is a mix of per-core register access and per-node pci device setup. Register access should be pinned to the cpu, but pci setup must run with preemption enabled. This patch better separates the code into non-/preemptible sections and fixes sleeping with preemption disabled. See bug message below. Fixes also freeing the eilvt entry by introducing put_eilvt(). BUG: sleeping function called from invalid context at mm/slub.c:824 in_atomic(): 1, irqs_disabled(): 0, pid: 32357, name: modprobe INFO: lockdep is turned off. Pid: 32357, comm: modprobe Not tainted 2.6.39-rc7+ #14 Call Trace: [<ffffffff8104bdc8>] __might_sleep+0x112/0x117 [<ffffffff81129693>] kmem_cache_alloc_trace+0x4b/0xe7 [<ffffffff81278f14>] kzalloc.constprop.0+0x29/0x2b [<ffffffff81278f4c>] pci_get_subsys+0x36/0x78 [<ffffffff81022689>] ? setup_APIC_eilvt+0xfb/0x139 [<ffffffff81278fa4>] pci_get_device+0x16/0x18 [<ffffffffa06c8b5d>] op_amd_init+0xd3/0x211 [oprofile] [<ffffffffa064d000>] ? 0xffffffffa064cfff [<ffffffffa064d298>] op_nmi_init+0x21e/0x26a [oprofile] [<ffffffffa064d062>] oprofile_arch_init+0xe/0x26 [oprofile] [<ffffffffa064d010>] oprofile_init+0x10/0x42 [oprofile] [<ffffffff81002099>] do_one_initcall+0x7f/0x13a [<ffffffff81096524>] sys_init_module+0x132/0x281 [<ffffffff814cc682>] system_call_fastpath+0x16/0x1b Reported-by: Dave Jones <davej@redhat.com> Cc: <stable@kernel.org> [2.6.37.x] Signed-off-by: Robert Richter <robert.richter@amd.com>
2011-01-06Merge branch 'x86-mce-for-linus' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: apic, amd: Make firmware bug messages more meaningful mce, amd: Remove goto in threshold_create_device() mce, amd: Add helper functions to setup APIC mce, amd: Shorten local variables mci_misc_{hi,lo} mce, amd: Implement mce_threshold_block_init() helper function
2011-01-05Merge commit 'v2.6.37' into perf/coreIngo Molnar1-8/+16
Merge reason: Add the final .37 tree. Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-01-03arch/x86/oprofile/op_model_amd.c: Perform initialisation on a single CPURobert Richter1-8/+16
Disable preemption in init_ibs(). The function only checks the ibs capabilities and sets up pci devices (if necessary). It runs only on one cpu but operates with the local APIC and some MSRs, thus it is better to disable preemption. [ 7.034377] BUG: using smp_processor_id() in preemptible [00000000] code: modprobe/483 [ 7.034385] caller is setup_APIC_eilvt+0x155/0x180 [ 7.034389] Pid: 483, comm: modprobe Not tainted 2.6.37-rc1-20101110+ #1 [ 7.034392] Call Trace: [ 7.034400] [<ffffffff812a2b72>] debug_smp_processor_id+0xd2/0xf0 [ 7.034404] [<ffffffff8101e985>] setup_APIC_eilvt+0x155/0x180 [ ... ] Addresses https://bugzilla.kernel.org/show_bug.cgi?id=22812 Reported-by: <atswartz@gmail.com> Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: oprofile-list@lists.sourceforge.net <oprofile-list@lists.sourceforge.net> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: Dan Carpenter <error27@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: <stable@kernel.org> [2.6.37.x] LKML-Reference: <20110103111514.GM4739@erda.amd.com> [ small cleanups ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-12-19oprofile, x86: Add support for 6 counters (AMD family 15h)Robert Richter1-18/+36
This patch adds support for up to 6 hardware counters for AMD family 15h cpus. There is a new MSR range for hardware counters beginning at MSRC001_0200 Performance Event Select (PERF_CTL0). Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-10-25Merge branch 'x86' of ↵Ingo Molnar1-37/+83
git://git.kernel.org/pub/scm/linux/kernel/git/rric/oprofile into perf/urgent
2010-10-25apic, amd: Make firmware bug messages more meaningfulRobert Richter1-0/+1
This improves error messages in case the BIOS was setting up wrong LVT offsets. Signed-off-by: Robert Richter <robert.richter@amd.com> Acked-by: Borislav Petkov <borislav.petkov@amd.com> LKML-Reference: <1288015419-29543-6-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-10-25Merge branch 'oprofile/core' into oprofile/x86Robert Richter1-15/+117
Conflicts: arch/x86/oprofile/op_model_amd.c Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-10-25x86/oprofile: Fix uninitialized variable use in debug printkIngo Molnar1-15/+11
Stephen Rothwell reported this build warning: arch/x86/oprofile/op_model_amd.c: In function 'ibs_eilvt_valid': arch/x86/oprofile/op_model_amd.c:289: warning: 'offset' may be used uninitialized in this function And correctly observed that indeed the variable is used uninitialized in this function. The result of this bug can be a debug printk with a bogus value. Also fix a few more small details that made this function hard to read and which probably contributed to the bug being introduced to begin with: - Use more symmetric error conditions - Remove the !0 obfuscation - Add newlines to the printk output - Remove bogus linebreaks in printk strings and elsewhere Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Robert Richter <robert.richter@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> LKML-Reference: <20101025115736.41d51abe.sfr@canb.auug.org.au> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-10-20apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsetsRobert Richter1-18/+127
We want the BIOS to setup the EILVT APIC registers. The offsets were hardcoded and BIOS settings were overwritten by the OS. Now, the subsystems for MCE threshold and IBS determine the LVT offset from the registers the BIOS has setup. If the BIOS setup is buggy on a family 10h system, a workaround enables IBS. If the OS determines an invalid register setup, a "[Firmware Bug]: " error message is reported. We need this change also for upcomming cpu families. Signed-off-by: Robert Richter <robert.richter@amd.com> LKML-Reference: <1286360874-1471-3-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-10-15oprofile, x86: Add support for IBS periodic op counter extensionRobert Richter1-3/+19
The count value for IBS op sampling has been extended by 7 bits. The feature is reflected in bit 6 (OpCntExt) of the IBS capability register (CPUID Fn8000_001B_EAX). Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-10-15oprofile, x86: Add support for IBS branch target address reportingRobert Richter1-6/+20
This patch adds support for IBS branch target address reporting. A new MSR (MSRC001_103B IBS Branch Target Address) has been added that provides the logical address in canonical form for the branch target. The size of the IBS sample that is transferred to the userland has been increased. For backward compatibility, the userland daemon must explicit enable the feature by writing to the oprofilefs file ibs_op/branch_target After enabling branch target address reporting, the userland daemon must handle the extended size of the IBS sample. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-10-15oprofile, x86: Introduce struct ibs_stateRobert Richter1-11/+18
This patch introduces struct ibs_state that will extended by additinal members in follow-on patches. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-10-15oprofile, x86: Remove duplicate check for IBS_CAPS_OPCNTRobert Richter1-2/+1
Since oprofile is setting up ibs_op/dispatched_ops in the fs only if the feature is available, its corresponding variable ibs_config.dispatched_ops is only set, if the feature is available. Thus the check is duplicate and can be removed. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-10-15oprofile, x86: Check IBS capability bits 1 and 2Robert Richter1-21/+38
There are IBS CPUID feature flags in CPUID Fn8000_001B to detect if the cpu supports IBS fetch sampling (FetchSam) and/or IBS execution sampling (OpSam). This patch adds checks if the both features are available. Spec: http://support.amd.com/us/Processor_TechDocs/31116.pdf Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-05-06oprofile/x86: make AMD IBS hotplug capableRobert Richter1-38/+16
Current IBS code is not hotplug capable. An offline cpu might not be initialized or deinitialized properly. This patch fixes this by removing on_each_cpu() functions. The IBS init/deinit code is executed in the per-cpu functions model->setup_ctrs() and model->cpu_down() which are also called by hotplug notifiers. model->cpu_down() replaces model->exit() that became obsolete. Cc: Andi Kleen <andi@firstfloor.org> Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-05-04oprofile/x86: remove duplicate IBS capability checkRobert Richter1-2/+1
The check is already done in ibs_exit(). Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-05-04oprofile/x86: move IBS codeRobert Richter1-110/+110
Moving code to make future changes easier. This groups all IBS code together. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-05-04oprofile/x86: return -EBUSY if counters are already reservedRobert Richter1-11/+13
In case a counter is already reserved by the watchdog or perf_event subsystem, oprofile ignored this counters silently. This case is handled now and oprofile_setup() now reports an error. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-05-04oprofile/x86: moving shutdown functionsRobert Richter1-12/+12
Moving some code in preparation of the next patch. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-05-04oprofile/x86: reserve counter msrs pairwiseRobert Richter1-24/+19
For AMD's and Intel's P6 generic performance counters have pairwise counter and control msrs. This patch changes the counter reservation in a way that both msrs must be registered. It joins some counter loops and also removes the unnecessary NUM_CONTROLS macro in the AMD implementation. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-03-01perf, x86: rename macro in ARCH_PERFMON_EVENTSEL_ENABLERobert Richter1-3/+3
For consistency reasons this patch renames ARCH_PERFMON_EVENTSEL0_ENABLE to ARCH_PERFMON_EVENTSEL_ENABLE. The following is performed: $ sed -i -e s/ARCH_PERFMON_EVENTSEL0_ENABLE/ARCH_PERFMON_EVENTSEL_ENABLE/g \ arch/x86/include/asm/perf_event.h arch/x86/kernel/cpu/perf_event.c \ arch/x86/kernel/cpu/perf_event_p6.c \ arch/x86/kernel/cpu/perfctr-watchdog.c \ arch/x86/oprofile/op_model_amd.c arch/x86/oprofile/op_model_ppro.c Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-03-01perf, x86: add some IBS macros to perf_event.hRobert Richter1-3/+3
Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-03-01perf, x86: make IBS macros available in perf_event.hRobert Richter1-11/+0
This patch moves code from oprofile to perf_event.h to make it also available for usage by perf. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: fix msr access to reserved countersRobert Richter1-5/+4
During switching virtual counters there is access to perfctr msrs. If the counter is not available this fails due to an invalid address. This patch fixes this. Cc: stable@kernel.org Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: use kzalloc() instead of kmalloc()Robert Richter1-4/+0
Cc: stable@kernel.org Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: fix perfctr nmi reservation for mulitplexingRobert Richter1-19/+0
Multiple virtual counters share one physical counter. The reservation of virtual counters fails due to duplicate allocation of the same counter. The counters are already reserved. Thus, virtual counter reservation may removed at all. This also makes the code easier. Cc: stable@kernel.org Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: warn user if a counter is already activeRobert Richter1-1/+10
This patch generates a warning if a counter is already active. Implemented for AMD and P6 models. P4 is not supported. Cc: Naga Chumbalkar <nagananda.chumbalkar@hp.com> Cc: Shashi Belur <shashi-kiran.belur@hp.com> Cc: Tony Jones <tonyj@suse.de> Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: implement randomization for IBS periodic op counterRobert Richter1-6/+63
IBS selects an op (execution operation) for sampling by counting either cycles or dispatched ops. Better statistical samples can be produced by adding a software generated random offset to the periodic op counter value with each sample. This patch adds software randomization to the IBS periodic op counter. The lower 12 bits of the 20 bit counter are randomized. IbsOpCurCnt is initialized with a 12 bit random value. There is a work around if the hw can not write to IbsOpCurCnt. Then the lower 8 bits of the 16 bit IbsOpMaxCnt [15:0] value are randomized in the range of -128 to +127 by adding/subtracting an offset to the maximum count (IbsOpMaxCnt). The linear feedback shift register (LFSR) algorithm is used for pseudo-random number generation to have low impact to the memory system. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: implement lsfr pseudo-random number generator for IBSSuravee Suthikulpanit1-0/+23
This patch implements a linear feedback shift register (LFSR) for pseudo-random number generation for IBS. For IBS measurements it would be good to minimize memory traffic in the interrupt handler since every access pollutes the data caches. Computing a maximal period LFSR just needs shifts and ORs. The LFSR method is good enough to randomize the ops at low overhead. 16 pseudo-random bits are enough for the implementation and it doesn't matter that the pattern repeats with a fairly short cycle. It only needs to break up (hard) periodic sampling behavior. The logic was designed by Paul Drongowski. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: implement IBS cpuid feature detectionRobert Richter1-17/+63
This patch adds IBS feature detection using cpuid flags. An IBS capability mask is introduced to test for certain IBS features. The bit mask is the same as for IBS cpuid feature flags (Fn8000_001B_EAX), but bit 0 is used to indicate the existence of IBS. The patch also changes the handling of the IbsOpCntCtl bit (periodic op counter count control). The oprofilefs file for this feature (ibs_op/dispatched_ops) will be only exposed if the feature is available, also the default for the bit is set to count clock cycles. In general, the userland can detect the availability of a feature by checking for the corresponding file in oprofilefs. If it exists, the feature also exists. This may lead to a dynamic file layout depending on the cpu type with that the userland has to deal with. Current opcontrol is compatible. Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: remove node check in AMD IBS initializationRobert Richter1-10/+0
Standard AMD systems have the same number of nodes as there are northbridge devices. However, there may kernel configurations (especially for 32 bit) or system setups exist, where the node number is different or it can not be detected properly. Thus the check is not reliable and may fail though IBS setup was fine. For this reason it is better to remove the check. Cc: stable <stable@kernel.org> Signed-off-by: Robert Richter <robert.richter@amd.com>
2010-02-26oprofile/x86: remove OPROFILE_IBS config optionRobert Richter1-30/+1
OProfile support for IBS is now for several versions in the kernel. The feature is stable now and the code can be activated permanently. As a side effect IBS now works also on nosmp configs. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-08-04arch/x86/oprofile/op_model_amd.c: fix op_amd_handle_ibs() return typeAndrew Morton1-5/+3
arch/x86/oprofile/op_model_amd.c: In function 'op_amd_handle_ibs': arch/x86/oprofile/op_model_amd.c:217: warning: no return statement in function returning non-void Fix this by making op_amd_handle_ibs() return void. Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-08-04Revert "x86: oprofile/op_model_amd.c set return values for op_amd_handle_ibs()"Robert Richter1-5/+2
This reverts commit 21e70878215f620fe99ea7d7c74bc641aeec932f. Instead Andrew's patch will be applied he posted at the same time. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-07-20x86/oprofile: Small coding style fixesRobert Richter1-3/+2
Some small coding style fixes. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-07-20x86/oprofile: Implement op_x86_virt_to_phys()Robert Richter1-1/+1
This patch implements a common x86 function to convert virtual counter numbers to physical. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-07-20x86/oprofile: Remove unused num_virt_controls from struct op_x86_model_specRobert Richter1-1/+0
The member num_virt_controls of struct op_x86_model_spec is not used. This patch removes it. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-07-20x86/oprofile: Remove const qualifier from struct op_x86_model_specRobert Richter1-1/+1
This patch removes the const qualifier from struct op_x86_model_spec to make model parameters changable. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-07-20oprofile: Grouping multiplexing code in op_model_amd.cRobert Richter1-34/+41
This patch moves some multiplexing code to the new function op_mux_fill_in_addresses(). Also, the whole multiplexing code is now at a single location. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-07-20oprofile: Introduce op_x86_phys_to_virt()Robert Richter1-49/+31
This new function translates physical to virtual counter numbers. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-07-20x86/oprofile: Fix usage of NUM_CONTROLS/NUM_COUNTERS macrosRobert Richter1-2/+2
Use the corresponding macros when iterating over counter and control registers. Since NUM_CONTROLS and NUM_COUNTERS are equal for AMD cpus the fix is more a cosmetical change. Signed-off-by: Robert Richter <robert.richter@amd.com>
2009-07-20oprofile: Implement performance counter multiplexingJason Yeh1-14/+96
The number of hardware counters is limited. The multiplexing feature enables OProfile to gather more events than counters are provided by the hardware. This is realized by switching between events at an user specified time interval. A new file (/dev/oprofile/time_slice) is added for the user to specify the timer interval in ms. If the number of events to profile is higher than the number of hardware counters available, the patch will schedule a work queue that switches the event counter and re-writes the different sets of values into it. The switching mechanism needs to be implemented for each architecture to support multiplexing. This patch only implements AMD CPU support, but multiplexing can be easily extended for other models and architectures. There are follow-on patches that rework parts of this patch. Signed-off-by: Jason Yeh <jason.yeh@amd.com> Signed-off-by: Robert Richter <robert.richter@amd.com>
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