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BMC/Intel-BMC/linux.git
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dev-4.10
dev-4.13
dev-4.17
dev-4.18
dev-4.19
dev-4.3
dev-4.4
dev-4.6
dev-4.7
dev-5.0
dev-5.1
dev-5.10-intel
dev-5.10.46-intel
dev-5.10.49-intel
dev-5.14-intel
dev-5.15-intel
dev-5.2
dev-5.3
dev-5.4
dev-5.7
dev-5.8
dev-5.8-intel
master
Intel OpenBMC Linux kernel source tree (mirror)
Andrey V.Kosteltsev
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sparc64
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kernel
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tsb.S
Age
Commit message (
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)
Author
Files
Lines
2007-03-19
[SPARC64]: store-init needs trailing membar.
David S. Miller
1
-0
/
+1
2006-06-30
Remove obsolete #include <linux/config.h>
Jörn Engel
1
-1
/
+0
2006-03-22
[SPARC64]: Add a secondary TSB for hugepage mappings.
David S. Miller
1
-50
/
+160
2006-03-20
[SPARC64]: Optimized TSB table initialization.
David S. Miller
1
-0
/
+69
2006-03-20
[SPARC64]: Fix and re-enable dynamic TSB sizing.
David S. Miller
1
-1
/
+70
2006-03-20
[SPARC64]: Simplify TSB insert checks.
David S. Miller
1
-14
/
+0
2006-03-20
[SPARC64]: Fix _PAGE_EXEC handling.
David S. Miller
1
-0
/
+9
2006-03-20
[SPARC64]: More TLB/TSB handling fixes.
David S. Miller
1
-6
/
+11
2006-03-20
[SPARC64]: Fix some SUN4V TLB handling bugs.
David S. Miller
1
-3
/
+3
2006-03-20
[SPARC64]: Do not write garbage into %pstate in tsb_context_switch().
David S. Miller
1
-1
/
+7
2006-03-20
[SPARC64]: Deal with PTE layout differences in SUN4V.
David S. Miller
1
-4
/
+5
2006-03-20
[SPARC64]: Simplify sun4v TLB handling using macros.
David S. Miller
1
-10
/
+8
2006-03-20
[SPARC64]: Fix hypervisor call arg passing.
David S. Miller
1
-3
/
+3
2006-03-20
[SPARC64]: Hypervisor TSB context switching.
David S. Miller
1
-15
/
+27
2006-03-20
[SPARC64]: Implement sun4v TSB miss handlers.
David S. Miller
1
-2
/
+5
2006-03-20
[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch
David S. Miller
1
-6
/
+6
2006-03-20
[SPARC64]: Initial sun4v TLB miss handling infrastructure.
David S. Miller
1
-13
/
+76
2006-03-20
[SPARC64]: Sanitize %pstate writes for sun4v.
David S. Miller
1
-2
/
+10
2006-03-20
[SPARC64]: Refine register window trap handling.
David S. Miller
1
-1
/
+0
2006-03-20
[SPARC64]: Add explicit register args to trap state loading macros.
David S. Miller
1
-8
/
+1
2006-03-20
[SPARC64]: Access TSB with physical addresses when possible.
David S. Miller
1
-5
/
+30
2006-03-20
[SPARC64]: Fix too early reference to %g6
David S. Miller
1
-2
/
+5
2006-03-20
[SPARC64]: Kill PROM locked TLB entry preservation code.
David S. Miller
1
-7
/
+0
2006-03-20
[SPARC64]: Use sparc64_highest_unlocked_tlb_ent in __tsb_context_switch()
David S. Miller
1
-6
/
+8
2006-03-20
[SPARC64]: Preload TSB entries from update_mmu_cache().
David S. Miller
1
-0
/
+17
2006-03-20
[SPARC64]: Add infrastructure for dynamic TSB sizing.
David S. Miller
1
-34
/
+21
2006-03-20
[SPARC64]: TSB refinements.
David S. Miller
1
-0
/
+11
2006-03-20
[SPARC64]: Elminate all usage of hard-coded trap globals.
David S. Miller
1
-6
/
+20
2006-03-20
[SPARC64]: Move away from virtual page tables, part 1.
David S. Miller
1
-0
/
+169