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path: root/arch/mips/mti-malta
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2014-08-02MIPS: Malta: initialise MAARsPaul Burton1-0/+26
2014-08-02MIPS: Malta: Fix dispatching of GIC interruptsJeffrey Deans1-7/+18
2014-08-02MIPS: GIC: Remove GIC_FLAG_IPIJeffrey Deans1-1/+1
2014-06-10Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds8-199/+109
2014-06-05Merge branch '3.15-fixes' into mips-for-linux-nextRalf Baechle1-1/+1
2014-06-04Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm into nextLinus Torvalds1-12/+2
2014-05-30MIPS: Malta: support powering downPaul Burton1-0/+4
2014-05-30MIPS: Malta: hang on haltPaul Burton1-4/+6
2014-05-30MIPS: Malta: add suspend state entry codePaul Burton2-0/+98
2014-05-30MIPS: KVM: Override guest kernel timer frequency directlyJames Hogan1-12/+2
2014-05-25MIPS: malta: Remove 'maybe_unused' attribute from ememsize{, _str}Markos Chandras1-2/+2
2014-05-25MIPS: malta: memory.c: Initialize the 'memsize' variableMarkos Chandras1-1/+1
2014-05-24MIPS: MT: Remove SMTC supportRalf Baechle5-194/+0
2014-03-31Merge branch '3.14-fixes' into mips-for-linux-nextRalf Baechle2-3/+3
2014-03-31MIPS: Malta: GIC IPIs may be used without MTPaul Burton1-8/+11
2014-03-31MIPS: Malta: Fix CONFIG_BLK_DEV_IDE vestiges.Ralf Baechle1-9/+13
2014-03-27MIPS: malta: malta-init: Fix System Controller memory mapping for EVALeonid Yegoshin1-0/+13
2014-03-27MIPS: malta: malta-memory: Add free_init_pages_eva() callbackMarkos Chandras1-0/+8
2014-03-27MIPS: malta: malta-memory: Use the PHYS_OFFSET to build the memory mapMarkos Chandras1-7/+7
2014-03-27MIPS: malta: malta-memory: Add support for the 'ememsize' variableMarkos Chandras1-9/+27
2014-03-27MIPS: malta: Configure Segment Control registers for EVA bootMarkos Chandras1-0/+4
2014-03-27MIPS: Malta: Allow use of MIPS CPS SMP implementationPaul Burton1-0/+2
2014-03-27MIPS: Malta: Probe CPC when supportedPaul Burton1-0/+7
2014-03-27MIPS: Malta: Make use of generic CM supportPaul Burton3-63/+19
2014-03-07MIPS: APRP: Choose the correct VPE loader by fixing the linkingDeng-Cheng Zhu1-1/+1
2014-03-06MIPS: APRP: Fix the linking of rtlx interrupt hookDeng-Cheng Zhu1-2/+2
2014-01-25mips: delete non-required instances of include <linux/init.h>Paul Gortmaker1-1/+0
2014-01-23MIPS: Malta: use generic 8250 early consolePaul Burton3-74/+33
2014-01-23MIPS: Malta: initialise the RTC at bootPaul Burton1-0/+13
2014-01-23MIPS: Malta: remove unused cpu_khz variablePaul Burton1-3/+0
2014-01-22MIPS: APRP: Code formatting clean-ups.Steven J. Hill2-76/+63
2014-01-22MIPS: APRP: Add support for Malta CMP platform.Deng-Cheng Zhu2-3/+33
2014-01-22MIPS: Malta: Remove ttyS2 serial for CMP platformsLeonid Yegoshin1-0/+2
2013-11-08Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds1-1/+0
2013-10-30MIPS: malta: Fix GIC interrupt offsetsMarkos Chandras1-4/+5
2013-10-30MIPS: Remove unused defines in piix4.hDeng-Cheng Zhu1-1/+0
2013-09-18MIPS: Cleanup CP0 PRId and CP1 FPIR register access masksMaciej W. Rozycki1-2/+3
2013-07-15MIPS: Delete __cpuinit/__CPUINIT usage from MIPS codePaul Gortmaker2-4/+4
2013-07-12Merge branch '3.10-fixes' into mips-for-linux-nextRalf Baechle1-25/+8
2013-07-01MIPS: Malta: Update GCMP detection.Leonid Yegoshin1-1/+3
2013-07-01MIPS: Malta: Move platform-specific PCI code to arch/mips/pci.Ralf Baechle2-255/+0
2013-06-21MIPS: malta: Remove software reset defines from generic header.Steven J. Hill1-24/+5
2013-06-21MIPS: malta: Move defines of reset registers and values.Steven J. Hill1-1/+3
2013-05-09Merge branch 'mti-next' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhi...Ralf Baechle8-308/+182
2013-05-09MIPS: Add new GIC clockevent driver.Raghu Gandham1-0/+3
2013-05-09MIPS: Refactor GIC clocksource code.Steven J. Hill1-13/+24
2013-05-09MIPS: Move 'gic_frequency' to common location.Steven J. Hill1-1/+0
2013-05-09MIPS: Move 'gic_present' to common location.Steven J. Hill1-1/+0
2013-05-08MIPS: FW: malta: Code formatting clean-ups.Steven J. Hill4-88/+64
2013-05-08MIPS: FW: Remove obsolete header file for MTI platforms.Steven J. Hill4-6/+0