summaryrefslogtreecommitdiff
path: root/arch/mips/include
AgeCommit message (Expand)AuthorFilesLines
2014-11-24MIPS: ralink: add a helper for reading the ECO versionJohn Crispin1-0/+5
2014-11-24MIPS: lantiq: export soc typeJohn Crispin1-0/+2
2014-11-24clocksource: mips-gic: Use CPU notifiers to setup the timerAndrew Bresticker1-4/+1
2014-11-24clocksource: mips-gic: Combine with GIC clockevent driverAndrew Bresticker1-1/+1
2014-11-24MIPS: bcm3384: Initial commit of bcm3384 platform supportKevin Cernekee2-0/+72
2014-11-24MIPS: Create a helper function for DT setupKevin Cernekee1-0/+1
2014-11-24MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)Kevin Cernekee1-0/+1
2014-11-24MIPS: BMIPS: Let each platform customize the CPU1 IRQ maskKevin Cernekee1-0/+1
2014-11-24MIPS: Loongson1B: Some fixes/updates for LS1BKelvin Cheung6-8/+152
2014-11-24MIPS: Loongson1B: Fix reboot problem on LS1BKelvin Cheung1-7/+4
2014-11-24MIPS: BCM47XX: Clean up nvram headerRafał Miłecki1-34/+1
2014-11-24MIPS: ELF: Set FP mode according to .MIPS.abiflagsPaul Burton1-17/+33
2014-11-24MIPS: ELF: Add definition for the .MIPS.abiflags sectionPaul Burton1-0/+25
2014-11-24MIPS: Support for hybrid FPRsPaul Burton3-8/+46
2014-11-24MIPS: detect presence of the FRE & UFR bitsPaul Burton2-0/+5
2014-11-24MIPS: define bits introduced for hybrid FPRsPaul Burton1-0/+3
2014-11-24MIPS: Loongson-3: Add RS780/SBX00 HPET supportHuacai Chen1-0/+73
2014-11-24MIPS: Loongson: Improve LEFI firmware interfaceHuacai Chen6-8/+107
2014-11-24MIPS: Loongson: Allow booting from any coreHuacai Chen3-4/+6
2014-11-24MIPS: Loongson-3: Add PHYS48_TO_HT40 supportHuacai Chen1-3/+3
2014-11-24MIPS: Remove __strlen_user().Ralf Baechle1-27/+0
2014-11-24MIPS: BCM47XX: Make ssb init NVRAM instead of bcm47xx polling itRafał Miłecki1-0/+1
2014-11-24MIPS: Move gic.h to include/linux/irqchip/mips-gic.hAndrew Bresticker3-327/+2
2014-11-24irqchip: mips-gic: Use proper iomem accessorsAndrew Bresticker1-65/+7
2014-11-24irqchip: mips-gic: Export function to read counter widthAndrew Bresticker1-0/+1
2014-11-24irqchip: mips-gic: Remove unnecessary globalsAndrew Bresticker1-5/+0
2014-11-24irqchip: mips-gic: Support local interruptsAndrew Bresticker3-9/+34
2014-11-24irqchip: mips-gic: Use separate edge/level irq_chipsAndrew Bresticker1-1/+0
2014-11-24irqchip: mips-gic: Probe for number of external interruptsAndrew Bresticker3-2/+2
2014-11-24irqchip: mips-gic: Stop using per-platform mapping tablesAndrew Bresticker3-40/+22
2014-11-24irqchip: mips-gic: Use IRQ domainsAndrew Bresticker1-1/+0
2014-11-24irqchip: mips-gic: Implement irq_set_type callbackAndrew Bresticker1-0/+9
2014-11-24irqchip: mips-gic: Remove platform irq_ack/irq_eoi callbacksAndrew Bresticker1-2/+0
2014-11-24MIPS: Move MIPS_GIC_IRQ_BASE into platform irq.hAndrew Bresticker3-4/+6
2014-11-24MIPS: Malta: Move MSC01 interrupt baseAndrew Bresticker1-4/+4
2014-11-24MIPS: sead3: Do not overlap CPU/GIC IRQ rangesAndrew Bresticker1-1/+1
2014-11-24MIPS: Remove gic_{enable,disable}_interrupt()Andrew Bresticker1-2/+0
2014-11-24MIPS: Add hook to get C0 performance counter interruptAndrew Bresticker1-0/+1
2014-11-24MIPS: Rename mips_cpu_intc_init() -> mips_cpu_irq_of_init()Andrew Bresticker1-2/+2
2014-11-24mips: Convert pr_warning to pr_warnJoe Perches1-42/+27
2014-11-24MIPS: Add arch_trigger_all_cpu_backtrace() functionEunbong Song1-0/+3
2014-11-24MIPS: cpu-probe: Set the FTLB probability bit on supported coresMarkos Chandras1-0/+2
2014-11-24MIPS: uaccess.h: Fix strnlen_user comment.Ralf Baechle1-4/+2
2014-11-24MIPS: r4kcache: Add EVA case for protected_writeback_dcache_lineMarkos Chandras1-0/+4
2014-11-24MIPS: Fix a copy & paste error in unistd.hHuacai Chen1-1/+1
2014-11-22Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller3-7/+15
2014-11-19MIPS: jump_label.c: Handle the microMIPS J instruction encodingMaciej W. Rozycki1-1/+7
2014-11-19MIPS: Zero variable read by get_user / __get_user in case of an error.Ralf Baechle1-1/+4
2014-11-19MIPS: asm: uaccess: Add v1 register to clobber list on EVAMarkos Chandras1-3/+4
2014-11-19MIPS: Loongson: Set Loongson-3's ISA level to MIPS64R1Huacai Chen1-2/+0
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-23 05:37:08 +0300