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path: root/arch/mips/include/asm/mipsregs.h
AgeCommit message (Expand)AuthorFilesLines
2013-09-19MIPS: Add MIPS R5 config5 register.Ralf Baechle1-0/+7
2013-07-01MIPS: microMIPS: Fix improper definition of ISA exception bit.Steven J. Hill1-1/+1
2013-05-09MIPS: microMIPS: Add support for exception handling.Steven J. Hill1-0/+1
2013-05-02MIPS: microMIPS: Add instruction utility macros.Steven J. Hill1-0/+18
2013-03-19MIPS: Fix code generation for non-DSP capable CPUsFlorian Fainelli1-19/+190
2013-02-21Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-j...Ralf Baechle1-186/+125
2013-02-19MIPS: Probe for and report hardware virtualization support.David Daney1-0/+1
2013-02-17MIPS: dsp: Simplify the DSP macros.Steven J. Hill1-201/+30
2013-02-17MIPS: dsp: Support toolchains without DSP ASE and microMIPS.Steven J. Hill1-0/+89
2013-02-17MIPS: dsp: Add assembler support for DSP ASEs.Steven J. Hill1-17/+36
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill1-0/+1
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-199/+199
2013-02-01MIPS: Whitespace cleanups and reformatting.Steven J. Hill1-11/+15
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle1-8/+0
2012-12-12MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORTDavid Daney1-1/+1
2012-10-11MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill1-0/+1
2012-10-11MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)Al Cooper1-0/+2
2012-09-28Merge branch 'ralf-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhi...Ralf Baechle1-0/+2
2012-09-14MIPS: Add base architecture support for RI and XI.Steven J. Hill1-0/+1
2012-09-14MIPS: Add support for the 1074K core.Steven J. Hill1-0/+2
2011-12-08MIPS: BMIPS: Add set/clear CP0 macros for BMIPS operationsKevin Cernekee1-1/+8
2011-10-25MIPS: Add accessor macros for 64-bit performance counter registers.David Daney1-0/+8
2011-03-31Fix common misspellingsLucas De Marchi1-2/+2
2010-10-29MIPS: Add BMIPS CP0 register definitionsKevin Cernekee1-0/+51
2010-08-05MIPS: Define ST0_NMI in asm/mipsregs.hDavid Daney1-0/+1
2010-05-16 MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1Shane McDonald1-1/+8
2010-02-27MIPS: Add accessor functions and bit definitions for c0_PageGrainDavid Daney1-0/+11
2010-02-27MIPS: Decode c0_config4 for large TLBs.David Daney1-0/+4
2010-01-28MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQsDavid VomLehn1-0/+12
2009-06-17MIPS: Add hugetlbfs page defines.David Daney1-0/+16
2009-05-14MIPS: Fix sign-extension bug in 32-bit kernel on 32-bit hardware.Ralf Baechle1-4/+4
2009-05-14MIPS: Cavium: Add support for 8k and 32k page sizes.Ralf Baechle1-0/+11
2009-05-14MIPS: SMTC: Bring set/clear/change_c0_## return value semantics uptodate.Kevin D. Kissell1-8/+11
2009-03-24MIPS: Change {set,clear,change}_c0_<foo> to return old value.Ralf Baechle1-11/+11
2009-01-11MIPS: Override assembler target architecture for octeon.David Daney1-0/+2
2009-01-11MIPS: Add Cavium OCTEON specific register definitions to mipsregs.hDavid Daney1-0/+20
2008-10-27MIPS: Add CONFIG_CPU_R5500 for NEC VR5500 series processorsShinya Kuribayashi1-0/+1
2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle1-0/+1526