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2013-09-04MIPS: Lantiq: Falcon: add cpu-feature-override.hThomas Langer1-0/+58
Add cpu-feature-override.h for the GPON SoC Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5658/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-21Merge branch 'mips-next-3.9' of ↵Ralf Baechle1-0/+2
git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
2013-02-17MIPS: lantiq: rework external irq codeJohn Crispin1-0/+1
This code makes the irqs used by the EIU loadable from the DT. Additionally we add a helper that allows the pinctrl layer to map external irqs to real irq numbers. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4818/
2013-02-17MIPS: lantiq: adds static clock for PP32John Crispin1-0/+1
The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle3-15/+15
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-13Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into ↵Ralf Baechle1-0/+3
mips-for-linux-next
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle1-1/+0
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-11-11MIPS: lantiq: adds code for booting GPHYJohn Crispin1-0/+3
The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to boot them up. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4522
2012-09-13MIPS: lantiq: make use of __gpio_to_irqJohn Crispin1-4/+1
The gpio_chip struct allows us to set a .to_irq callback. Once this is set we can rely on the generic __gpio_to_irq() function to map gpio->irq allowing more than one gpio_chip to register an interrupt Signed-off-by: John Crispin <blogic@openwrt.org>
2012-09-13OF: pinctrl: MIPS: lantiq: adds support for FALCON SoCJohn Crispin1-0/+4
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
2012-08-23MIPS: lantiq: split up IRQ IM rangesJohn Crispin2-0/+4
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate the SVIP we need to support IM ranges that are scattered inside the register range. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4237/
2012-05-26MIPS: lantiq: remove orphaned codeJohn Crispin4-169/+3
Now that all drivers are converted to OF we are able to remove some remaining pieces of orphaned code. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3841/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-21MIPS: lantiq: implement support for FALCON socJohn Crispin3-0/+108
Adds support for the FALCON SoC. This SoC is from the FTTH/GPON SoC family. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-21watchdog: MIPS: lantiq: implement OF support and minor fixesJohn Crispin2-1/+2
Add support for OF. We also apply the following small fixes * reduce boiler plate by using devm_request_and_ioremap * sane error path for the clock * move LTQ_RST_CAUSE_WDTRST to a soc specific header file * add a message to show that the driver loaded Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Wim Van Sebroeck <wim@iguana.be> Cc: linux-watchdog@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3810/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-21MIPS: lantiq: implement support for clkdev apiJohn Crispin2-15/+17
This patch unifies all clock generation and gating code into one file. All drivers will now be able to request their clocks via their device. This patch also adds support for the clockout feature, which allows clock generation on external pins. Support for COMMON_CLK will be provided in the next series. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-21MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()John Crispin2-2/+16
As part of the conversion to OF we also implement pinctrl drivers. Previously we used ltq_gpio_request() to set pinmuxing. This is now obselete and we can hence drop the function. Additionally we remove gpio_to_irq() from the gpio driver and move it to a header file. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3801/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15MIPS: lantiq: cleanup reset codeJohn Crispin2-1/+12
Add 2 new soc specifc handlers and remove superflous pr_notice calls. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15MIPS: lantiq: add xway soc idsJohn Crispin1-6/+21
Add the soc ids for additional xway socs. The patch also merges the amazon_se code with the other socs. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15MIPS: lantiq: fix early printkThomas Langer1-0/+6
The code was using a 32bit write operations in the early_printk code. This resulted in 3 zero bytes also being written to the serial port. This patch changes the memory access to 8bit. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3721/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add ethernet driverJohn Crispin2-2/+9
This patch adds the driver for the ETOP Packet Processing Engine (PPE32) found inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit ethernet work. Support for all 8 dma channels, gbit and the embedded switch found on the ar9/vr9 still needs to be implemented. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2357/ Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add DMA supportJohn Crispin2-1/+62
This patch adds support for the DMA engine found inside the XWAY family of SoCs. The engine has 5 ports and 20 channels. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add PCI controller support.John Crispin1-0/+46
The Lantiq family of SoCs have a EBU (External Bus Unit). This patch adds the driver that allows us to use the EBU as a PCI controller. In order for PCI to work the EBU is set to endianess swap all the data. In addition we need to make use of SWAP_IO_SPACE for device->host DMA to work. The clock of the PCI works in several modes (internal/external). If this is not configured correctly the SoC will hang. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2250/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: add SoC specific code for XWAY familyJohn Crispin3-0/+224
Add support for the Lantiq XWAY family of Mips24KEc SoCs. * Danube (PSB50702) * Twinpass (PSB4000) * AR9 (PSB50802) * Amazon SE (PSB5061) The Amazon SE is a lightweight SoC and has no PCI as well as a different clock. We split the code out into seperate files to handle this. The GPIO pins on the SoCs are multi function and there are several bits we can use to configure the pins. To be as compatible as possible to GPIOLIB we add a function int lq_gpio_request(unsigned int pin, unsigned int alt0, unsigned int alt1, unsigned int dir, const char *name); which lets you configure the 2 "alternate function" bits. This way drivers like PCI can make use of GPIOLIB without a cubersome wrapper. The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was taken from a 2.4.20 source tree and was never really changed by me since then. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2249/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-05-19MIPS: Lantiq: Add initial support for Lantiq SoCsJohn Crispin2-0/+87
Add initial support for Mips based SoCs made by Lantiq. This series will add support for the XWAY family. The series allows booting a minimal system using a initramfs or NOR. Missing drivers and support for Amazon and GPON family will be provided in a later series. [Ralf: Remove some cargo cult programming and fixed formatting.] Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2252/ Patchwork: https://patchwork.linux-mips.org/patch/2371/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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