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path: root/arch/blackfin/mach-common/cache.S
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2011-03-18Blackfin: SMP: work around anomaly 05000491Sonic Zhang1-0/+20
In order to safely work around anomaly 05000491, we have to execute IFLUSH from L1 instruction sram. The trouble with multi-core systems is that all L1 sram is visible only to the active core. So we can't just place the functions into L1 and call it directly. We need to setup a jump table and place the entry point in external memory. This will call the right func based on the active core. In the process, convert from the manual relocation of a small bit of code into Core B's L1 to the more general framework we already have in place for loading arbitrary pieces of code into L1. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-18Blackfin: split optimization settings moreMike Frysinger1-6/+12
We need to place icache flush funcs into L1 inst sram to work around a hardware anomaly. But this currently breaks SMP support as the L1 inst sram is per-core and cannot be called directly. So in preparation for making that work, split the two options. Further, split out the SMP depend so that we can allow some for SMP. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-04Blackfin: iflush: update anomaly 05000491 workaroundMike Frysinger1-0/+2
Recent feedback from design says we need three NOPs in the hardware loop. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-08-06Blackfin: allow cache funcs to be in L1 for IFLUSH Anomaly 05000491Mike Frysinger1-11/+4
Anomaly 05000491 says that IFLUSH cannot have certain types of memory stalls triggered before it has completed in order to function correctly. One such condition is that it be in L1 instruction. So add a config option to move it there, default it to on, and throw up a warning when it is turned off and this anomaly exists. Since the anomaly should be worked around, we can drop the older method of calling IFLUSH multiple times. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2009-10-07Blackfin: mass clean up of copyright/licensing infoRobin Getz1-2/+0
Bill Gatliff & David Brownell pointed out we were missing some copyrights, and licensing terms in some of the files in ./arch/blackfin, so this fixes things, and cleans them up. It also removes: - verbose GPL text(refer to the top level ./COPYING file) - file names (you are looking at the file) - bug url (it's in the ./MAINTAINERS file) - "or later" on GPL-2, when we did not have that right It also allows some Blackfin-specific assembly files to be under a BSD like license (for people to use them outside of Linux). Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-12Blackfin: simplify the do_flush macroMike Frysinger1-15/+15
Simplify the do_flush macro now that we don't need to take into account a second instruction being used together. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-06-12Blackfin: fix data cache flushing when doing icache flushingMike Frysinger1-16/+0
Make sure we flush all data caches and their write buffers before flushing icache, otherwise random edge cases could crop up where stale data is read into icache from external memory. As fallout, punt the combined icache + dcache flush function since we cannot safely do them back to back -- the SSYNC is needed between the dcache flush and the icache flush. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-03-05Blackfin arch: Fix bug - KGDB single step into the middle of a 4 bytes ↵Sonic Zhang1-0/+22
instruction on bf561 after soft bp is hit Run IFLUSH twice to avoid loading wrong instruction after invalidating icache and following sequence is met. 1) The one instruction address is cached in the icache. 2) This instruction in SDRAM is changed. 3) IFLASH[P0] is executed only once in lackfin_icache_flush_range(). 4) This instruction is executed again, but not the changed new one. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: rewrite blackfin_invalidate_entire_dcache functionMike Frysinger1-36/+0
rewrite blackfin_invalidate_entire_dcache() in C for easier management, better optimization, and so we take all SSYNC anomalies into account Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2009-01-07Blackfin arch: SMP supporting patchset: Blackfin header files and machine ↵Graf Yang1-0/+36
common code Blackfin dual core BF561 processor can support SMP like features. https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like In this patch, we provide SMP extend to Blackfin header files and machine common code Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-28Blackfin arch: only add IFLUSH nop padding when anomaly 443 is enabledMike Frysinger1-1/+5
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-28Blackfin arch: fix bug - kernel build with write back policy fails to be ↵Mike Frysinger1-1/+1
booted up Make sure IFLUSH is not the last instruction in the hardware loop to avoid infinite core stall. The dcache/icache function that only gets used in writeback mode was putting IFLUSH as the last instruction in the hardware loop ... we know from design that this may often lead to inifite core stalling, so switch the FLUSH/IFLUSH order. Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-11-18Blackfin arch: fix bug - dmacopy test case fail on all platformMike Frysinger1-1/+5
The cache code I added flushes 1 line too little if the start address is not aligned to the cache size. Cache align the start address so that when we straddle cache aligns, we get the right count. Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-10-16Blackfin arch: unify/cleanup cache codeMike Frysinger1-115/+58
- to be correct wrt to end ranges - to be optimal with a one-instruction hardware loop Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2008-08-13Blackfin arch: delete unused cache functionsMike Frysinger1-115/+0
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2007-07-25Blackfin arch: use HI/LO macros rather than masking the bit ranges ourselvesMike Frysinger1-4/+4
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-06-21Blackfin arch: update ANOMALY handlingRobin Getz1-10/+10
update lists for 533, 537, and add SSYNC workaround into assembly files. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-06-11Blackfin arch: add proper ENDPROC()Mike Frysinger1-0/+10
add proper ENDPROC() to close out assembly functions so size/type is set properly in the final ELF image Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-05-07blackfin architectureBryan Wu1-0/+253
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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