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2020-05-20ARM: dts: imx6qdl-gw5910: add support for bcm4330-btTim Harvey1-20/+12
The Sterling-LWB has a BCM4330 which has a UART based bluetooth HCI. Add support for binding to the bcm_hci driver to take care of handling the shutdown gpio and loading firmware. Because the shutdown gpio is more of an enable than a regulator go ahead and replace the regulator with a shutdown-gpio. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20ARM: dts: imx6qdl-gw5904: add lsm9ds1 iio imu/magn supportTim Harvey1-0/+31
Add one node for the accel/gyro i2c device and another for the separate magnetometer device in the lsm9ds1. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20ARM: dts: imx6qdl-gw560x: add lsm9ds1 iio imu/magn supportTim Harvey1-0/+31
Add one node for the accel/gyro i2c device and another for the separate magnetometer device in the lsm9ds1. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20ARM: dts: imx53: Add src node interruptAnson Huang1-0/+1
Interrupt is a required property according to SRC binding, add it for SRC node. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20ARM: dts: imx51: Add src node interruptAnson Huang1-0/+1
Interrupt is a required property according to SRC binding, add it for SRC node. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20ARM: dts: imx50: Remove unused iomuxc-gpr nodeFabio Estevam1-5/+0
The iomuxc-gpr node is not used and causes the following dtc warning with W=1: arch/arm/boot/dts/imx50.dtsi:286.28-289.6: Warning (unique_unit_address): /soc/bus@50000000/iomuxc@53fa8000: duplicate unit-address (also used in node /soc/bus@50000000/iomuxc-gpr@53fa8000) Remove the node to fix the warning. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id"Martin Blumenstingl2-5/+2
Let the PHY generate the RX and TX delay on the Odroid-C1 and MXIII Plus. Previously we did not know that these boards used an RX delay. We assumed that setting the TX delay on the MAC side It turns out that these boards also require an RX delay of 2ns (verified on Odroid-C1, but the u-boot code uses the same setup on both boards). Ethernet only worked because u-boot added this RX delay on the MAC side. The 4ns TX delay was also wrong and the result of using an unsupported RGMII TX clock divider setting. This has been fixed in the driver with commit bd6f48546b9cb7 ("net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs"). Switch to phy-mode "rgmii-id" to let the PHY side handle all the delays, (as recommended by the Ethernet maintainers anyways) to correctly describe the need for a 2ns RX as well as 2ns TX delay on these boards. This fixes the Ethernet performance on Odroid-C1 where there was a huge amount of packet loss when transmitting data due to the incorrect TX delay. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200512215148.540322-3-martin.blumenstingl@googlemail.com
2020-05-20ARM: dts: meson: Add the Ethernet "timing-adjustment" clockMartin Blumenstingl2-4/+6
Add the "timing-adjusment" clock now that we now that this is connected to the PRG_ETHERNET registers. It is used internally to generate the RGMII RX delay no the MAC side (if needed). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com
2020-05-20ARM: dts: meson8m2: Use the Meson8m2 specific USB2 PHY compatibleMartin Blumenstingl1-0/+8
Use the Meson8m2 specific USB2 PHY compatible string. The 3.10 vendor kernel has at least one known difference between Meson8 and Meson8m2: Meson8m2 sets the ACA_ENABLE bit while Meson8 doesn't. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200515202520.1487514-1-martin.blumenstingl@googlemail.com
2020-05-20ARM: dts: meson: add the gadget mode properties to the USB0 controllerMartin Blumenstingl1-0/+3
Testing with a USB RNDIS connection and iperf3 gives the following results: - From the host computer to the device at ~250Mbit/s - From the device to the host computer at ~76Mbit/s Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200504195105.2909711-1-martin.blumenstingl@googlemail.com
2020-05-19ARM: dts: rockchip: add rga node for rk322xJustin Swartz1-0/+10
Add a node to define the presence of RGA, a 2D raster graphic acceleration unit. Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> Link: https://lore.kernel.org/r/20200419125134.29923-2-justin.swartz@risingedge.co.za Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-05-19ARM: dts: remove disable-wp from rk3229-xms6 emmcJustin Swartz1-1/+0
Remove the disable-wp attribute from &emmc as it is, according to Documentation/devicetree/bindings/mmc/mmc-controller.yaml: "Not used in combination with eMMC or SDIO." Suggested-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> Link: https://lore.kernel.org/r/20200406135006.23759-2-justin.swartz@risingedge.co.za Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-05-19ARM: dts: enable WLAN for Mecer Xtreme Mini S6Justin Swartz1-0/+16
The Mecer Xtreme Mini S6 features a wireless module, based on a Realtek 8723BS, which provides WLAN and Bluetooth connectivity via SDIO and UART interfaces respectively. Define a simple MMC power sequence that declares the GPIO pins connected to the module's WLAN Disable and Bluetooth Disable pins as active low reset signals, because both signals must be deasserted for WLAN radio operation. Configure the host's SDIO interface for High Speed mode with 1.8v I/O signalling and IRQ detection over a 4-bit wide bus. Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> Link: https://lore.kernel.org/r/20200406135006.23759-1-justin.swartz@risingedge.co.za Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-05-19ARM: dts: rockchip: remove identical #include from rk3288.dtsiJohan Jonker1-1/+0
There are 2 identical '#include' for 'rk3288-power.h', so remove one of them. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200403180159.13387-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-05-19ARM: dts: rockchip: rename and label gpio-led subnodesJohan Jonker10-27/+27
Current dts files with 'gpio-led' nodes were manually verified. In order to automate this process leds-gpio.txt has been converted to yaml. With this conversion a check for pattern properties was added. A test with the command below gives a screen full of warnings like: arch/arm/boot/dts/rk3188-radxarock.dt.yaml: gpio-leds: 'blue', 'green', 'sleep' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' Fix these errors with help of the following rules: 1: Add nodename in the preferred form. 2: Always add a label that ends with '_led' to prevent conflicts with other labels such as 'power' and 'mmc' 3: If leds need pinctrl add a label that ends with '_led_pin' also to prevent conflicts with other labels. patternProperties: # The first form is preferred, but fall back to just 'led' # anywhere in the node name to at least catch some child nodes. "(^led-[0-9a-f]$|led)": make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/leds/ leds-gpio.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20200428144933.10953-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-05-18arm64: dts: vexpress: Fix VExpress LED namesAndre Przywara1-8/+8
The common LED binding wants the LED node names to start with led- and then have just a single number. Changing the naming for the 8 user LEDs from using user<x> to led-<x>. Also there is no default-trigger named "mmc0" in the kernel, so use the more generic "disk-activity". Link: https://lore.kernel.org/r/20200513103016.130417-18-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18arm64: dts: fvp/juno: Fix bus node namesAndre Przywara1-2/+2
Most Arm Ltd. boards are employing a layered bus structure, to map the hardware design (SoC, motherboard, IOFPGA) and structure the DTs. The "simple-bus" nodes only allow a limited set of node names. Switch to use *-bus to be binding compliant. This relies on a pending dt-schema.git fix for now: https://github.com/devicetree-org/dt-schema/pull/38 Link: https://lore.kernel.org/r/20200513103016.130417-16-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18arm64: dts: fvp/juno: Fix serial node namesAndre Przywara1-4/+4
The UARTs for all Arm Ltd. boards were using "uart" as their node name stub. Replace that with the required "serial" string, to comply with the PL011 DT binding. Link: https://lore.kernel.org/r/20200513103016.130417-14-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-18ARM: dts: at91: sama5d2_xplained: Add aliases for the dedicated I2C IPsTudor Ambarus1-0/+2
The sama5d2 SoC has two dedicated I2C IPs that are enabled on sama5d2_xplained. Add alias for the i2c devices to not rely on probe order for the i2c device numbering. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200518114802.253660-1-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-17ARM: dts: ux500: Add touchscreen to the SkomerLinus Walleij1-1/+31
This adds touchscreen support to the Ux500 Samsung GT-S7710 "Skomer" mobile phone. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20200516212913.485365-1-linus.walleij@linaro.org
2020-05-17arm64: dts: vexpress: Move fixed devices out of bus nodeAndre Przywara1-154/+154
The devicetree compiler complains when DT nodes without a reg property live inside a (simple) bus node: Warning (simple_bus_reg): Node /bus@8000000/motherboard-bus/refclk32khz missing or empty reg/ranges property Move the fixed clocks, the fixed regulator, the leds and the config bus subtree to the root node, since they do not depend on any busses. Link: https://lore.kernel.org/r/20200513103016.130417-5-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17arm64: dts: fvp/juno: Fix node address fieldsAndre Przywara1-5/+5
The Arm Ltd. boards were using an outdated address convention in the DT node names, by separating the high from the low 32-bits of an address by a comma. Remove the comma from the node name suffix to be DT spec compliant. Link: https://lore.kernel.org/r/20200513103016.130417-3-andre.przywara@arm.com Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2020-05-17ARM: dts: kirkwood: ReadyNAS NV+v2: Add LCD panelBrian J. Tarricone1-0/+14
The NV+ v2 has a WH1602 LCD panel (which is just a rebranded HD44780), similar to the Netgear RN104, just with different GPIO assignments. Signed-off-by: Brian J. Tarricone <brian@tarricone.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-05-17ARM: dts: kirkwood: Add Check Point L-50 boardPawel Dembicki2-0/+439
This patch adds dts for the Check Point L-50 from 600/1100 series routers. Specification: -CPU: Marvell Kirkwood 88F6821 1200MHz -RAM: 512MB -Flash: NAND 512MB -WiFi: mPCIe card based on Atheros AR9287 b/g/n -WAN: 1 Gigabit Port (Marvell 88E1116R PHY) -LAN: 9 Gigabit Ports (2x Marvell 88E6171(5+4)) -USB: 2x USB2.0 -Express card slot -SD card slot -Serial console: RJ-45 115200 8n1 -Unsupported DSL Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-05-17ARM: dts: marvell: drop i2c timeout-ms propertyBaruch Siach5-11/+0
The timeout-ms property for i2c master nodes is undocumented, and as never been supported. Drop it. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-05-16arm: dts: mt2701: Add usb2 device nodesMin Guo2-0/+54
Add musb nodes and usb2 phy nodes for MT2701 Signed-off-by: Min Guo <min.guo@mediatek.com> Link: https://lore.kernel.org/r/20191211015446.11477-3-min.guo@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-16arm: dts: mt7623: add Mali-450 device nodeRyder Lee1-0/+25
Add a node for Mali-450. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Link: https://lore.kernel.org/r/af7b5a2e00eb3a4b6262807c378e43afd5f74779.1563867856.git.ryder.lee@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-15ARM: dts: at91: Configure I2C SCL gpio as open drainCodrin Ciubotariu4-13/+13
The SCL gpio pin used by I2C bus for recovery needs to be configured as open drain. Fixes: 455fec938bbb ("ARM: dts: at91: sama5d2: add i2c gpio pinctrl") Fixes: a4bd8da893a3 ("ARM: dts: at91: sama5d3: add i2c gpio pinctrl") Fixes: 8fb82f050cf6 ("ARM: dts: at91: sama5d4: add i2c gpio pinctrl") Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20200515140001.287932-1-codrin.ciubotariu@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2_xplained: Describe the flx0 I2C functionTudor Ambarus1-0/+21
Users can choose which flexcom function to use. Describe the I2C Flexcom0 function. Add alias for the i2c2 node in order to not rely on probe order for the i2c device numbering. The sama5d2 SoC has two dedicated i2c buses and five flexcoms that can function as i2c. The i2c0 and i2c1 aliases are kept for the dedicated i2c buses, the i2c flexcom functions can be numbered in order starting from i2c2. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-16-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2_ptc_ek: Add comments to describe the aliasesTudor Ambarus1-3/+3
Indicate which i2c alias is for which connector on the board. Specify that serial0 is for DBGU. This eases tester's life. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-17-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2_xplained: Add alias for DBGUTudor Ambarus1-0/+4
The aliases should be defined in the board dts rather than in the SoC dtsi. Don't rely on the aliases defined in the SoC dtsi and define the alias for the Serial DBGU in the board dts file. sama5d2 boards use the "serial0" alias for the Serial DBGU, do the same for sama5d2_xplained. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-15-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add missing flexcom definitionsTudor Ambarus1-0/+79
Describe all the flexcom functions for all the flexcom nodes. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-13-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Remove i2s and tcb aliases from SoC dtsiTudor Ambarus1-4/+0
Device aliases are board-specific, if needed one should define them in board dts rather than in the SoC dtsi. If an alias from the SoC dtsi is addressed by a driver that does not use any of the of_alias*() methods, we can drop it. This is the case for the i2s aliases, drop them. tcb aliases point to nodes that are not enabled in any of the sama5d2 based platforms. atmel_tclib.c is scheduled to go away, any board using that alias is already broken, so get rid of the tcb aliases too. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-14-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and I2C flx0 functionsTudor Ambarus3-1/+19
Spare boards of duplicating the DMA bindings. Describe the flx0 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-12-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add DMA bindings for the flx1 I2C functionTudor Ambarus2-1/+9
Spare boards of duplicating the DMA bindings. Describe the flx1 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-11-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add DMA bindings for the flx3 SPI functionTudor Ambarus3-0/+11
Spare boards of duplicating the DMA bindings. Describe the flx3 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-10-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Add DMA bindings for the SPI and UART flx4 functionsTudor Ambarus2-0/+20
Spare boards of duplicating the DMA bindings. Describe the flx4 DMA bindings in the SoC dtsi. Users that don't want to use DMA for their flexcom functions have to overwrite the flexcom DMA bindings in their board device tree. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-9-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Specify the FIFO size for the Flexcom UARTTudor Ambarus1-0/+2
The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs. Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-8-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx0 definitions in the SoC dtsiTudor Ambarus6-44/+41
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. There is a single functional change in this patch. With the move of the flx0 uart5 definition in the SoC dtsi, the uart5 from at91-sama5d27_wlsom1_ek.dts inherits the following optional property: atmel,fifo-size = <32>; This particular change was tested by Codrin. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-7-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx1 definitions in the SoC dtsiTudor Ambarus3-19/+29
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-6-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx2 definitions in the SoC dtsiTudor Ambarus2-12/+18
The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-5-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx3 definitions in the SoC dtsiTudor Ambarus4-31/+30
The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-4-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Move flx4 definitions in the SoC dtsiTudor Ambarus5-50/+40
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together with its function definitions in sama5d2.dtsi. Boards will just fill the pins and enable the desired functions. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-3-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-15ARM: dts: at91: sama5d2: Fix the label numbering for flexcom functionsTudor Ambarus5-21/+21
The sama5d2 SoC has the following IPs: [uart0, uart4], {spi0, spi1}, {i2c0, i2c1}. Label the flexcom functions in order: flx0: uart5, spi2, i2c2 flx1: uart6, spi3, i2c3 flx2: uart7, spi4, i2c4 flx3: uart8, spi5, i2c5 flx4: uart9, spi6, i2c6 Some boards respected this scheme, others not. Fix the ones that didn't. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200514050301.147442-2-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2020-05-14ARM: dts: stm32: Split Avenger96 into DHCOR SoM and Avenger96 boardMarek Vasut6-615/+675
The Avenger96 is in fact an assembly of DH Electronics DHCOR SoM on top of an Avenger96 reference board. The DHCOR SoM can be populated with any STM32MP15xx. Split the DTs to reflect this such that the common SoM and Avenger96 parts are now in stm32mp15xx-dhcor-*dtsi and a specific example implementation of STM32MP157A SoM and Avenger96 board is separated into stm32mp157a-dhcor-*dts* . The stm32mp157a-avenger96.dts is retained for the sake of backward naming compatibility. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Split SoC-independent parts of DHCOM SOM and PDK2Marek Vasut3-338/+352
The DH Electronics PDK2 can be populated with SoM with any STM32MP15xx variant. Split the SoC-independent parts of the SoM and PDK2 into the stm32mp15xx-dhcom-*.dtsi and reduce stm32mp157c-dhcom-*dts* to example of adding STM32MP157C variant of the SoM into a PDK2 carrier board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Add GPIO LEDs for STM32MP1 DHCOM PDK2Marek Vasut1-0/+28
Add bindings for the four GPIO LEDs on DH PDK2 board. Note that LED5 GPIO-E may conflict with touchscreen interrupt, hence LED5 must be disabled when using the DH 560-200 display unit with touchscreen. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Add GPIO keys for STM32MP1 DHCOM PDK2Marek Vasut1-0/+43
Add bindings for the four GPIO keys on DH PDK2 board. Note that TA1 key is polled because it's IRQ line conflicts with ethernet IRQ, the rest of the GPIO keys, TA2, TA3, TA4, are interrupt-driven and wake up sources. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Add IoT Box board supportManivannan Sadhasivam2-0/+69
IoT Box is an IoT gateway device based on Stinger96 board powered by STM32MP1 SoC, designed and manufactured by Shiratech Solutions. This device makes use of Stinger96 board by having it as a base board with one additional mezzanine on top. Following are the features exposed by this device in addition to the Stinger96 board: * WiFi/BT * CCS811 VOC sensor * 2x Digital microphones IM69D130 * 12x WS2812B LEDs Following peripherals are tested and known to work: * WiFi/BT * CCS811 More information about this device can be found in Shiratech website: https://www.shiratech-solutions.com/products/iot-box/ Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-05-14ARM: dts: stm32: Add Stinger96 board supportManivannan Sadhasivam3-0/+355
Stinger96 is a 96Boards IoT Extended edition board designed and manufactured by Shiratech solutions based on STM32MP1 SoC. Following are the features of this board: * 256MB DDR * 125MB NAND Flash * Onboard BG96 modem * 1x uSD * 2x USB (1 available as external connector and another connected to BG96) * 1x SPI * 1x PCM * 2x UART (apart from serial console) * 2x I2C (apart from one connected to PMIC) Following peripherals are tested and known to work: * BG96 modem * 1x I2C (LS-I2C0) * 1x SPI * 1x UART (LS-UART0) * USB (Only Gadget mode) * uSD More information about this board can be found in Shiratech website: https://www.shiratech-solutions.com/products/stinger96/ Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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