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2021-03-18ARM: dts: add silicon_id misc node into aspeed-bmc-intel-ast2600dev-5.8-intelJae Hyun Yoo1-0/+8
This commit adds silicon_id sub-node into misc_control node. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Change-Id: I60c09b654ca8a8881e5df4be07f062280210e570
2021-02-19hwmon: (aspeed-pwm-tacho) Add pwm chip driver supportJae Hyun Yoo1-4/+7
This commit adds pwm chip driver support into aspeed-g6-pwm-tacho driver to enable beep speaker driver. The pwm chip driver cannot be added as a separate platform driver because it makes resource conflicts with existing pwm-tacho driver so it uses hacky tweak on the existing driver. Note: Do not try upstream this hacky implementation. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Change-Id: I22ad12be2ae3a061d7942fec813cdb11be321db7
2021-02-18fixup! ARM: dts: aspeed-bmc-intel-ast2600: Update to latest SGPIOsJason M. Bills1-9/+9
Update based on the latest SGPIO list provided by the Archer City CPLD team. Change-Id: Ia14bcc86171f22b173229d46e1dc2cb9e241ad6f Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
2021-02-04Enable mailbox interruptsYong Li1-3/+3
Support interrupt generation for both 16 and 32 mailbox registers. Tested: After applied this patch, write the mailbox registers from BIOS side, the misc manager can capture the new mailbox data. Change-Id: I4030b6df176a53656aea9cb68ee80b67add8ed14 Signed-off-by: Yong Li <yong.b.li@linux.intel.com>
2021-01-20ARM: dts: aspeed-bmc-intel-ast2600: add status_susack LED nodeJae Hyun Yoo1-0/+5
This commit adds an LED control node for status_susack. Change-Id: I324ac20ec14cecb4c3ff48ec2964a885ad6a4480 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
2021-01-08fixup! ARM: dts: aspeed-bmc-intel-ast2600: Fix CPU2_MEM_VRHOT nameJason M. Bills1-1/+1
Change-Id: I91a4b82df13c3e1a5ff826e4d893c970e4a1ae02 Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
2021-01-08Update I3C driversDylan Hung2-6/+209
This commit ports I3C updates from Aspeed SDK v00.06.00. Note: Should be refined to get upstreamed. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Change-Id: Ic674bf5d6b5e72b389c739b136710915aabc6324
2021-01-08ARM: dts: aspeed: enable gpio1 nodeJae Hyun Yoo1-1/+1
This commit enables gpio1 node. Change-Id: I63e8731974190e2241db0bc41e3882f9be37cff4 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
2020-11-14Revert "Add a WA to defer flash writes on PS_ALERT_N assertion"Jae Hyun Yoo2-10/+1
It's ineffective. A complete solution will be provided in CPLD logic. This reverts commit 40fe787c69a2949684091b4647188d8915c8e2fa. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Change-Id: I0e5972adfd424d64152f208b30add98b67e32d48
2020-11-05Merge v5.8.17, commit '6d07b544ce203a684d9ca52635dcf2f4fc89b7d4' into ↵Jason M. Bills51-238/+1405
dev-5.8-intel
2020-10-30Merge tag 'v5.8.17' into dev-5.8Joel Stanley17-65/+90
This is the 5.8.17 stable release Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-29ARM: dts: aspeed-g6: add I3C1 and I3C2 pinctrl settingsJae Hyun Yoo2-0/+14
Pinpad AF22,AF23,AE22 and AE24 are dedicated pins for I3C but pinmux setting should be set in SCU438 register accordingly otherwise I3C pins are not enabled. To fix this issue, this commit adds pinctrl settings for I3C1 and I3C2. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Change-Id: I53818abda31864391de41f8032b38a32e66ec6b4
2020-10-29ARM: dts: meson8: remove two invalid interrupt lines from the GPU nodeMartin Blumenstingl1-2/+0
[ Upstream commit 737e7610b545cc901a9696083c1824a7104b8d1b ] The 3.10 vendor kernel defines the following GPU 20 interrupt lines: #define INT_MALI_GP AM_IRQ(160) #define INT_MALI_GP_MMU AM_IRQ(161) #define INT_MALI_PP AM_IRQ(162) #define INT_MALI_PMU AM_IRQ(163) #define INT_MALI_PP0 AM_IRQ(164) #define INT_MALI_PP0_MMU AM_IRQ(165) #define INT_MALI_PP1 AM_IRQ(166) #define INT_MALI_PP1_MMU AM_IRQ(167) #define INT_MALI_PP2 AM_IRQ(168) #define INT_MALI_PP2_MMU AM_IRQ(169) #define INT_MALI_PP3 AM_IRQ(170) #define INT_MALI_PP3_MMU AM_IRQ(171) #define INT_MALI_PP4 AM_IRQ(172) #define INT_MALI_PP4_MMU AM_IRQ(173) #define INT_MALI_PP5 AM_IRQ(174) #define INT_MALI_PP5_MMU AM_IRQ(175) #define INT_MALI_PP6 AM_IRQ(176) #define INT_MALI_PP6_MMU AM_IRQ(177) #define INT_MALI_PP7 AM_IRQ(178) #define INT_MALI_PP7_MMU AM_IRQ(179) However, the driver from the 3.10 vendor kernel does not use the following four interrupt lines: - INT_MALI_PP3 - INT_MALI_PP3_MMU - INT_MALI_PP7 - INT_MALI_PP7_MMU Drop the "pp3" and "ppmmu3" interrupt lines. This is also important because there is no matching entry in interrupt-names for it (meaning the "pp2" interrupt is actually assigned to the "pp3" interrupt line). Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU") Reported-by: Thomas Graichen <thomas.graichen@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: thomas graichen <thomas.graichen@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200815181957.408649-1-martin.blumenstingl@googlemail.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: iwg20d-q7-common: Fix touch controller probe failureBiju Das1-1/+14
[ Upstream commit 08d7a73fffb6769b1cf2278bf697e692daba3abf ] As per the iWave RZ/G1M schematic, the signal LVDS_PPEN controls the supply voltage for the touch panel, LVDS receiver and RGB LCD panel. Add a regulator for these device nodes and remove the powerdown-gpios property from the lvds-receiver node as it results in a touch controller driver probe failure. Fixes: 6f89dd9e9325 ("ARM: dts: iwg20d-q7-common: Add LCD support") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200924080535.3641-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: stm32: Fix DH PDK2 display PWM channelMarek Vasut1-1/+1
[ Upstream commit 57592d2a98dbc3bde3ddc062e91a8486bdcb211e ] The display PWM channel is number 3 (PWM2 CH4), make it so. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: stm32: Swap PHY reset GPIO and TSC2004 IRQ on DHCOM SOMMarek Vasut1-2/+2
[ Upstream commit 9ad98319e95263469d8ca2cb543c37c5a2f40980 ] On the production revision of the SoM, 587-200, the PHY reset GPIO and touchscreen IRQs are swapped to prevent collision between EXTi IRQs, reflect that in DT. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: stm32: Move ethernet PHY into DH SoM DTMarek Vasut2-33/+36
[ Upstream commit b0a07f609600b6fa4c30f783db50c38456804485 ] The PHY and the VIO regulator is populated on the SoM, move it into the SoM DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: stm32: lxa-mc1: Fix kernel warning about PHY delaysHolger Assmann1-2/+0
[ Upstream commit 42a31ac6698681363363d48335559d212a26a7ca ] The KSZ9031 PHY skew timings for rxc/txc, originally set to achieve the desired phase shift between clock- and data-signal, now trigger a kernel warning when used in rgmii-id mode: *-skew-ps values should be used only with phy-mode = "rgmii" This is because commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY") now configures own timings when phy-mode = "rgmii-id". Device trees wanting to set their own delays should use phy-mode "rgmii" instead as the warning prescribes. The "standard" timings now used with "rgmii-id" work fine on this board, so drop the explicit timings in the device tree and thereby silence the warning. Fixes: 666b5ca85cd3 ("ARM: dts: stm32: add STM32MP1-based Linux Automation MC-1 board") Signed-off-by: Holger Assmann <h.assmann@pengutronix.de> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: stm32: Fix sdmmc2 pins on AV96Marek Vasut1-3/+3
[ Upstream commit 1ad6e36ec266cedb0d274aa13253ff1fb2eed4ba ] The AV96 uses sdmmc2_d47_pins_c and sdmmc2_d47_sleep_pins_c, which differ from sdmmc2_d47_pins_b and sdmmc2_d47_sleep_pins_b in one pin, SDMMC2_D5, which is PA15 in the former and PA9 in the later. The PA15 is correct on AV96, so fix this. This error is likely a result of rebasing across the stm32mp1 DT pinctrl rework. Fixes: 611325f68102 ("ARM: dts: stm32: Add eMMC attached to SDMMC2 on AV96") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: OMAP2+: Restore MPU power domain if cpu_cluster_pm_enter() failsTony Lindgren1-1/+3
[ Upstream commit 8f04aea048d56f3e39a7e543939450246542a6fc ] If cpu_cluster_pm_enter() fails, we need to set MPU power domain back to enabled to prevent the next WFI from potentially triggering an undesired MPU power domain state change. We already do this for omap_enter_idle_smp() but are missing it for omap_enter_idle_coupled(). Fixes: 55be2f50336f ("ARM: OMAP2+: Handle errors for cpu_pm") Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: owl-s500: Fix incorrect PPI interrupt specifiersCristian Ciocaltea1-3/+3
[ Upstream commit 55f6c9931f7c32f19cf221211f099dfd8dab3af9 ] The PPI interrupts for cortex-a9 were incorrectly specified, fix them. Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Peter Korsgaard <peter@korsgaard.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix dcdc1 regulatorJernej Skrabec1-5/+5
[ Upstream commit 3658a2b7f3e16c7053eb8d70657b94bb62c5a0f4 ] DCDC1 regulator powers many different subsystems. While some of them can work at 3.0 V, some of them can not. For example, VCC-HDMI can only work between 3.24 V and 3.36 V. According to OS images provided by the board manufacturer this regulator should be set to 3.3 V. Set DCDC1 and DCDC1SW to 3.3 V in order to fix this. Fixes: da7ac948fa93 ("ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200824193649.978197-1-jernej.skrabec@siol.net Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: s3c24xx: fix mmc gpio lookup tablesArnd Bergmann5-9/+9
[ Upstream commit 3af4e8774b6d03683932b0961998e01355bccd74 ] The gpio controller names differ between s3c24xx and s3c64xx, and it seems that these all got the wrong names, using GPx instead of GPIOx. Fixes: d2951dfa070d ("mmc: s3cmci: Use the slot GPIO descriptor") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20200806182059.2431-3-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: at91: pm: of_node_put() after its usageClaudiu Beznea1-0/+1
[ Upstream commit e222f943519564978e082c152b4140a47e93392c ] Put node after it has been used. Fixes: 13f16017d3e3f ("ARM: at91: pm: Tie the USB clock mask to the pmc") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1596616610-15460-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: dts: imx6sl: fix rng nodeHoria Geantă1-0/+2
[ Upstream commit 82ffb35c2ce63ef8e0325f75eb48022abcf8edbe ] rng DT node was added without a compatible string. i.MX driver for RNGC (drivers/char/hw_random/imx-rngc.c) also claims support for RNGB, and is currently used for i.MX25. Let's use this driver also for RNGB block in i.MX6SL. Fixes: e29fe21cff96 ("ARM: dts: add device tree source for imx6sl SoC") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-29ARM: 9007/1: l2c: fix prefetch bits init in L2X0_AUX_CTRL using DT valuesGuillaume Tucker1-4/+12
[ Upstream commit 8e007b367a59bcdf484c81f6df9bd5a4cc179ca6 ] The L310_PREFETCH_CTRL register bits 28 and 29 to enable data and instruction prefetch respectively can also be accessed via the L2X0_AUX_CTRL register. They appear to be actually wired together in hardware between the registers. Changing them in the prefetch register only will get undone when restoring the aux control register later on. For this reason, set these bits in both registers during initialisation according to the devicetree property values. Link: https://lore.kernel.org/lkml/76f2f3ad5e77e356e0a5b99ceee1e774a2842c25.1597061474.git.guillaume.tucker@collabora.com/ Fixes: ec3bd0e68a67 ("ARM: 8391/1: l2c: add options to overwrite prefetching behavior") Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-10-28ARM: dts: Fix label address for 64MiB OpenBMC flash layoutGeorge Liu1-4/+4
Signed-off-by: George Liu <liuxiwei@inspur.com> Reviewed-by: John Wang <wangzhiqiang.bj@bytedance.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20201022081002.2665132-1-liuxiwei@inspur.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-27Add a WA to defer flash writes on PS_ALERT_N assertionJae Hyun Yoo2-1/+10
To prevent SPI flash corruption, this commit adds a WA which monitors PS_ALERT_N signal for detecting AC loss and it defers flash writes when the signal is asserted. Actually, the PS_ALERT_N is asserted even when PSU is in an unhealthy state so it also adds 10 seconds of timeout for the deferring that covers AC loss case effectively. If PSU gets back to healthy state, flash writes will be continued immediately. Note: It's still not a complete solution since an AC loss could happen while a previous event is still asserted from >=10 seconds ago. We would miss it. Note: This would be a customization for some specific platforms and this is a WA to cover a defect of H/W design. Do not try upstream it. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Change-Id: I3d0c18d46e6b7dac2aa472acf742add8336244da
2020-10-21ARM: dts: aspeed: g220a: Add some gpiosJohn Wang1-2/+2
Add GPIO STRAP_BMC_BATTERY_GPIOS5, which is used for battery adc sensor. Change the INTRUDER_N to CHASSIS_INTRUSION, to make it more meaningful OpenBMC-Staging-Count: 1 Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20201014083057.1026-1-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-10hwmon: peci: dimmpower implementationZbigniew Lukwinski1-0/+1
1. Peci dimmpower module implementation. 2. Enable DIMM avarage power, power limit, power limit max setting, power limit min setting reading and expose them under power1_avarage, power1_cap, power1_cap_max, power1_cap_min in sysfs. 3. Enable DIMM power limit writing through power1_cap. Tested: * on WilsonCity platform, * power1_avarage, power1_cap, power1_cap_max and power1_cap_min work as expected Signed-off-by: Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com>
2020-10-10AST2600: enable UART routing.Kuiying Wang1-6/+6
Enable UART routing. Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
2020-10-10arm: dts: aspeed-g6: Add ast2600-mctp nodeIwona Winiarska1-0/+15
AST2600 provides MCTP over PCIe controller allowing BMC to communicate with devices on host PCIe bus. We are also adding syscon node describing PCIe Host controller device which can be used to gather information on PCIe enumeration (and assigned address). Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
2020-10-10enable AST2600 I3CJae Hyun Yoo1-6/+13
This commit ports I3C related changes from Aspeed SDK v00.05.05. It also includes Vitor's I3C cdev implementation which isn't upstreamed yet so it should be refined later. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Vitor Soares <soares@synopsys.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
2020-10-10Add peci-cpupower driverZhikuiRen1-0/+1
peci-cpupower reads CPU energy counter through peci and computes average power in mW since last read. Signed-off-by: ZhikuiRen <zhikui.ren@intel.com>
2020-10-10ARM: dts: aspeed-g6: add video nodeJae Hyun Yoo1-0/+10
This commit adds video node. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
2020-10-10ADC linux driver for AST2600Chen Yugang1-2/+12
Tested: it's tested with DC input. Signed-off-by: Chen Yugang <yugang.chen@linux.intel.com>
2020-10-10ARM: dts: aspeed-g6: add GFX nodeJae Hyun Yoo1-0/+9
This commit adds GFX node for AST2600 SoC. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
2020-10-10arm: ast2600: add pwm_tacho driver from aspeedVernon Mauery1-0/+10
Add the pwm_tacho driver from Aspeed to get pwm working until an upstream PWM/Tacho driver is available. This was copied from the v5.02 BSP from Aspeed. Signed-off-by: Vernon Mauery <vernon.mauery@intel.com>
2020-10-10i2c: aspeed: add buffer mode transfer supportJae Hyun Yoo3-54/+72
Byte mode currently this driver uses makes lots of interrupt call which isn't good for performance and it makes the driver very timing sensitive. To improve performance of the driver, this commit adds buffer mode transfer support which uses I2C SRAM buffer instead of using a single byte buffer. AST2400: It has 2 KBytes (256 Bytes x 8 pages) of I2C SRAM buffer pool from 0x1e78a800 to 0x1e78afff that can be used for all busses with buffer pool manipulation. To simplify implementation for supporting both AST2400 and AST2500, it assigns each 128 Bytes per bus without using buffer pool manipulation so total 1792 Bytes of I2C SRAM buffer will be used. AST2500: It has 16 Bytes of individual I2C SRAM buffer per each bus and its range is from 0x1e78a200 to 0x1e78a2df, so it doesn't have 'buffer page selection' bit field in the Function control register, and neither 'base address pointer' bit field in the Pool buffer control register it has. To simplify implementation for supporting both AST2400 and AST2500, it writes zeros on those register bit fields but it's okay because it does nothing in AST2500. It provides buffer based master and slave data transfer. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
2020-10-10Add AST2500 and AST2600 JTAG deviceErnesto Corona2-0/+29
Adding aspeed jtag device Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
2020-10-09ARM: kprobes: Avoid fortify_panic() when copying optprobe templateAndrew Jeffery2-20/+20
Setting both CONFIG_KPROBES=y and CONFIG_FORTIFY_SOURCE=y on ARM leads to a panic in memcpy() when injecting a kprobe despite the fixes found in commit e46daee53bb5 ("ARM: 8806/1: kprobes: Fix false positive with FORTIFY_SOURCE") and commit 0ac569bf6a79 ("ARM: 8834/1: Fix: kprobes: optimized kprobes illegal instruction"). arch/arm/include/asm/kprobes.h effectively declares the target type of the optprobe_template_entry assembly label as a u32 which leads memcpy()'s __builtin_object_size() call to determine that the pointed-to object is of size four. However, the symbol is used as a handle for the optimised probe assembly template that is at least 96 bytes in size. The symbol's use despite its type blows up the memcpy() in ARM's arch_prepare_optimized_kprobe() with a false-positive fortify_panic() when it should instead copy the optimised probe template into place: ``` $ sudo perf probe -a aspeed_g6_pinctrl_probe [ 158.457252] detected buffer overflow in memcpy ``` OpenBMC-Staging-Count: 1 Fixes: e46daee53bb5 ("ARM: 8806/1: kprobes: Fix false positive with FORTIFY_SOURCE") Fixes: 0ac569bf6a79 ("ARM: 8834/1: Fix: kprobes: optimized kprobes illegal instruction") Suggested-by: Kees Cook <keescook@chromium.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: Luka Oreskovic <luka.oreskovic@sartura.hr> Tested-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Cc: Luka Oreskovic <luka.oreskovic@sartura.hr> Cc: Juraj Vijtiuk <juraj.vijtiuk@sartura.hr> Link: https://lore.kernel.org/r/20201001042927.2147800-1-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-07ARM: dts: aspeed: rainier: Don't shout addressesAndrew Jeffery1-2/+2
Make them lowercase. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20201002063414.275161-4-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-07ARM: config: Enable PSTORE in aspeed_g5_defconfigAndrew Jeffery1-0/+4
We're making use of it on IBM's Rainier system. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20201002063414.275161-3-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-07ARM: dts: aspeed: Add Bytedance g220a BMC machineLotus Xu2-0/+932
The g220a is a server platform with an ASPEED AST2500 BMC. OpenBMC-Staging-Count: 1 Signed-off-by: Lotus Xu <xuxiaohan@bytedance.com> Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200929063955.1206-2-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-07ARM: dts: Add 64MiB OpenBMC flash layoutJohn Wang1-0/+35
This is an alternate layout used by OpenBMC systems The division of space is as follows: u-boot + env: 0.5MB kernel/FIT: 5MB rofs: 42.5MB rwfs: 16MB OpenBMC-Staging-Count: 1 Signed-off-by: John Wang <wangzhiqiang.bj@bytedance.com> Link: https://lore.kernel.org/r/20200929063955.1206-1-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-07ARM: dts: aspeed: amd-ethanolx: Update KCS nodes to use v2 bindingKonstantin Aladyshev1-3/+3
KCS nodes compatible property in the 'aspeed-g5.dtsi' file was changed to use v2 binding in the commit fa4c8ec6feaa (ARM: dts: aspeed: Change KCS nodes to v2 binding). For the proper initialization of /dev/ipmi-kcs* devices KCS node variables also need to be changed to use v2 binding. OpenBMC-Staging-Count: 1 Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com> Link: https://lore.kernel.org/r/20200930075153.2115-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-10-06char: ipmi: Add clock control logic into Aspeed LPC KCS driverJae Hyun Yoo2-1/+11
If LPC KCS driver is registered ahead of lpc-ctrl module, LPC KCS block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupt in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub-nodes should enable LCLK individually so this patch adds clock control logic into the LPC KCS driver. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
2020-10-06misc: Add clock control logic into Aspeed LPC SNOOP driverJae Hyun Yoo3-0/+3
If LPC SNOOP driver is registered ahead of lpc-ctrl module, LPC SNOOP block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupt in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub-nodes should enable LCLK individually so this patch adds clock control logic into the LPC SNOOP driver. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
2020-10-06char: ipmi: Add clock control logic into Aspeed LPC BT driverJae Hyun Yoo3-0/+3
If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT block will be enabled without heart beating of LCLK until lpc-ctrl enables the LCLK. This issue causes improper handling on host interrupts when the host sends interrupt in that time frame. Then kernel eventually forcibly disables the interrupt with dumping stack and printing a 'nobody cared this irq' message out. To prevent this issue, all LPC sub-nodes should enable LCLK individually so this patch adds clock control logic into the LPC BT driver. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
2020-10-06Add Aspeed PWM driver which uses FTTMR010 timer IPJae Hyun Yoo1-1/+1
This commit adds Aspeed PWM driver which uses timer pulse output feature in Aspeed SoCs. The timer IP is derived from Faraday Technologies FTTMR010 IP but has some customized register structure changes only for Aspeed SoCs. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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