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2020-08-31Merge tag 'v5.8.5' into dev-5.8dev-5.8Joel Stanley11-89/+130
This is the 5.8.5 stable release Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-19ARM: 8992/1: Fix unwind_frame for clang-built kernelsNathan Huckleberry1-0/+24
commit b4d5ec9b39f8b31d98f65bc5577b5d15d93795d7 upstream. Since clang does not push pc and sp in function prologues, the current implementation of unwind_frame does not work. By using the previous frame's lr/fp instead of saved pc/sp we get valid unwinds on clang-built kernels. The bounds check on next frame pointer must be changed as well since there are 8 less bytes between frames. This fixes /proc/<pid>/stack. Link: https://github.com/ClangBuiltLinux/linux/issues/912 Reported-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Miles Chen <miles.chen@mediatek.com> Cc: stable@vger.kernel.org Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-19ARM: dts: exynos: Extend all Exynos5800 A15's OPPs with max voltage dataMarek Szyprowski1-3/+3
commit d644853ff8fcbb7a4e3757f9d8ccc39d930b7e3c upstream. On Exynos5422/5800 the regulator supply for the A15 cores ("vdd_arm") is coupled with the regulator supply for the SoC internal circuits ("vdd_int"), thus all operating points that modify one of those supplies have to specify a triplet of the min/target/max values to properly work with regulator coupling. Fixes: eaffc4de16c6 ("ARM: dts: exynos: Add missing CPU frequencies for Exynos5422/5800") Cc: <stable@vger.kernel.org> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-19ARM: exynos: clear L310_AUX_CTRL_FULL_LINE_ZERO in default l2c_aux_valGuillaume Tucker1-1/+1
[ Upstream commit 5b17a04addc29201dc142c8d2c077eb7745d2e35 ] This "alert" error message can be seen on exynos4412-odroidx2: L2C: platform modifies aux control register: 0x02070000 -> 0x3e470001 L2C: platform provided aux values permit register corruption. Followed by this plain error message: L2C-310: enabling full line of zeros but not enabled in Cortex-A9 To fix it, don't set the L310_AUX_CTRL_FULL_LINE_ZERO flag (bit 0) in the default value of l2c_aux_val. It may instead be enabled when applicable by the logic in l2c310_enable() if the attribute "arm,full-line-zero-disable" was set in the device tree. The initial commit that introduced this default value was in v2.6.38 commit 1cf0eb799759 ("ARM: S5PV310: Add L2 cache init function in cpu.c"). However, the code to set the L310_AUX_CTRL_FULL_LINE_ZERO flag and manage that feature was added much later and the default value was not updated then. So this seems to have been a subtle oversight especially since enabling it only in the cache and not in the A9 core doesn't actually prevent the platform from running. According to the TRM, the opposite would be a real issue, if the feature was enabled in the A9 core but not in the cache controller. Reported-by: "kernelci.org bot" <bot@kernelci.org> Signed-off-by: Guillaume Tucker <guillaume.tucker@collabora.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: socfpga: PM: add missing put_device() call in ↵Yu Kuai1-3/+5
socfpga_setup_ocram_self_refresh() [ Upstream commit 3ad7b4e8f89d6bcc9887ca701cf2745a6aedb1a0 ] if of_find_device_by_node() succeed, socfpga_setup_ocram_self_refresh doesn't have a corresponding put_device(). Thus add a jump target to fix the exception handling for this function implementation. Fixes: 44fd8c7d4005 ("ARM: socfpga: support suspend to ram") Signed-off-by: Yu Kuai <yukuai3@huawei.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: stm32: Fix spi4 pins in stm32mp15-pinctrlPatrick Delaunay1-14/+14
[ Upstream commit 4fe663890ac5b3b099f458b20cce13fe8efec12b ] Move spi4_pins_a nodes from pinctrl_z to pinctrl as the associated pins are not in BANK Z. Fixes: 498a7014989d ("ARM: dts: stm32: Add missing pinctrl entries for STM32MP15") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltagesChen-Yu Tsai1-3/+3
[ Upstream commit e4dae01bf08b754de79072441c357737220b873f ] The Bananapi M2+ uses a GPIO line to change the effective resistance of the CPU supply regulator's feedback resistor network. The voltages described in the device tree were given directly by the vendor. This turns out to be slightly off compared to the real values. The updated voltages are based on calculations of the feedback resistor network, and verified down to three decimal places with a multi-meter. Fixes: 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200717160053.31191-4-wens@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: sunxi: bananapi-m2-plus-v1.2: Add regulator supply to all CPU coresChen-Yu Tsai1-0/+12
[ Upstream commit 55b271af765b0e03d1ff29502f81644b1a3c87fd ] The device tree currently only assigns the a supply for the first CPU core, when in reality the regulator supply is shared by all four cores. This might cause an issue if the implementation does not realize the sharing of the supply. Assign the same regulator supply to the remaining CPU cores to address this. Fixes: 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200717160053.31191-3-wens@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: at91: sama5d3_xplained: change phy-modeAlexandre Belloni1-1/+1
[ Upstream commit 7dbf4bbf1c320d82058878bd44805724d171e1e8 ] Since commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY"), networking is broken on sama5d3 xplained. The device tree has phy-mode = "rgmii" and this worked before, because KSZ9031 PHY started with default RGMII internal delays configuration (TX off, RX on 1.2 ns) and MAC provided TX delay. After above commit, the KSZ9031 PHY starts handling phy mode properly and disables RX delay, as result networking is become broken. Fix it by switching to phy-mode = "rgmii-rxid" to reflect previous behavior. Fixes: bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200717233644.841080-1-alexandre.belloni@bootlin.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: exynos: Disable frequency scaling for FSYS bus on Odroid XU3 familyMarek Szyprowski1-6/+0
[ Upstream commit 9ff416cf45a08f28167b75045222c762a0347930 ] Commit 1019fe2c7280 ("ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids") changed the parameters of the OPPs for the FSYS bus. Besides the frequency adjustments, it also removed the 'shared-opp' property from the OPP table used for FSYS_APB and FSYS busses. This revealed that in fact the FSYS bus frequency scaling never worked. When one OPP table is marked as 'opp-shared', only the first bus which selects the OPP sets the rate of its clock. Then OPP core assumes that the other busses have been changed to that OPP and no change to their clock rates are needed. Thus when FSYS_APB bus, which was registered first, set the rate for its clock, the OPP core did not change the FSYS bus clock later. The mentioned commit removed that behavior, what introduced a regression on some Odroid XU3 boards. Frequency scaling of the FSYS bus causes instability of the USB host operation, what can be observed as network hangs. To restore old behavior, simply disable frequency scaling for the FSYS bus. Reported-by: Willy Wolff <willy.mh.wolff.ml@gmail.com> Fixes: 1019fe2c7280 ("ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: at91: pm: add missing put_device() call in at91_pm_sram_init()yu kuai1-3/+8
[ Upstream commit f87a4f022c44e5b87e842a9f3e644fba87e8385f ] if of_find_device_by_node() succeed, at91_pm_sram_init() doesn't have a corresponding put_device(). Thus add a jump target to fix the exception handling for this function implementation. Fixes: d2e467905596 ("ARM: at91: pm: use the mmio-sram pool to access SRAM") Signed-off-by: yu kuai <yukuai3@huawei.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200604123301.3905837-1-yukuai3@huawei.com Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: gose: Fix ports node name for adv7612Niklas Söderlund1-1/+1
[ Upstream commit 59692ac5a7bb8c97ff440fc8917828083fbc38d6 ] When adding the adv7612 device node the ports node was misspelled as port, fix this. Fixes: bc63cd87f3ce924f ("ARM: dts: gose: add HDMI input") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200713111016.523189-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: gose: Fix ports node name for adv7180Niklas Söderlund1-1/+1
[ Upstream commit d344234abde938ae1062edb6c05852b0bafb4a03 ] When adding the adv7180 device node the ports node was misspelled as port, fix this. Fixes: 8cae359049a88b75 ("ARM: dts: gose: add composite video input") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200704155856.3037010-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: exynos: MCPM: Restore big.LITTLE cpuidle supportMarek Szyprowski1-3/+7
[ Upstream commit ea9dd8f61c8a890843f68e8dc0062ce78365aab8 ] Call exynos_cpu_power_up(cpunr) unconditionally. This is needed by the big.LITTLE cpuidle driver and has no side-effects on other code paths. The additional soft-reset call during little core power up has been added to properly boot all cores on the Exynos5422-based boards with secure firmware (like Odroid XU3/XU4 family). This however broke big.LITTLE CPUidle driver, which worked only on boards without secure firmware (like Peach-Pit/Pi Chromebooks). Apply the workaround only when board is running under secure firmware. Fixes: 833b5794e330 ("ARM: EXYNOS: reset Little cores when cpu is up") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: stm32: fix uart7_pins_a comments in stm32mp15-pinctrlErwan Le Ray1-4/+4
[ Upstream commit 391e437eedc0dab0a9f2c26997e68e040ae04ea3 ] Fix uart7_pins_a comments to indicate UART7 pins instead of UART4 pins. Fixes: bf4b5f379fed ("ARM: dts: stm32: Add missing pinctrl definitions for STM32MP157") Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-19ARM: dts: stm32: fix uart nodes ordering in stm32mp15-pinctrlErwan Le Ray1-51/+51
[ Upstream commit f6b43d89d3b5a31bf4251a26c61e92bf659e74c5 ] Fix usart and uart nodes ordering. Several usart nodes didn't respect expecting ordering. Fixes: 077e0638fc83 ("ARM: dts: stm32: Add alternate pinmux for USART2 pins on stm32mp15") Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-18ARM: dts: Aspeed: Rainier: Enable XDMA engineEddie James1-3/+9
Fix the VGA reserved memory node, and add the XDMA engine node, enable it, and point it's memory region to the VGA memory. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-14ARM: dts: aspeed: rainier: Add directly controlled LEDsVishwanatha Subbanna1-2/+22
These LEDs are directly connected to the BMC's GPIO bank. OpenBMC-Staging-Count: 1 Signed-off-by: Vishwanatha Subbanna <vishwa@linux.vnet.ibm.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-14ARM: dts: aspeed: rainier: Add Operator Panel LEDsVishwanatha Subbanna1-0/+82
These LEDs are on the op-panel and are connected via a pca9551 i2c LED expander. OpenBMC-Staging-Count: 1 Signed-off-by: Vishwanatha Subbanna <vishwa@linux.vnet.ibm.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-13ARM: aspeed: g5: Do not set sirq polarityJoel Stanley1-1/+0
A feature was added to the aspeed vuart driver to configure the vuart interrupt (sirq) polarity according to the LPC/eSPI strapping register. Systems that depend on a active low behaviour (sirq_polarity set to 0) such as OpenPower boxes also use LPC, so this relationship does not hold. The property was added for a Tyan S7106 system which is unfortuantly not supported in the kernel tree. Should other systems wish to use this feature of the driver they should add it to the machine device tree. OpenBMC-Staging-Count: 1 Fixes: c791fc76bc72 ("arm: dts: aspeed: Add vuart aspeed,sirq-polarity-sense...") Cc: stable@vger.kernel.org Alexander A. Filippov <a.filippov@yadro.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: config: aspeed: Fix selection of video deviceJoel Stanley1-1/+2
The reorganisation left VIDEO_ASPEED disabled. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: config: aspeed-g5: Enable I2C GPIO mux driverJoel Stanley1-0/+1
Used by rainier and q71l. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: configs: aspeed: Update defconfigsJoel Stanley2-21/+52
OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: aspeed: witherspoon-128: Remove checkstop GPIO from gpio-keys ↵Ben Tyner1-0/+6
definitions Attention handler will monitor the checkstop gpio via the character device interface so it needs to not be defined. OpenBMC-Staging-Count: 2 Signed-off-by: Ben Tyner <bentyner@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: aspeed: ast2600evb: Add MAC0Joel Stanley1-0/+20
MAC0 was not functional in the AST2600A0 SoC. This has been resolved with the A1, so allow use of this port on EVBs with the A1. A0 EVBs will still boot with this change, but the first ethernet device will not be functional. OpenBMC-Staging-Count: 3 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: aspeed: Add witherspoon-128 machineEddie James2-0/+60
Create a witherspoon machine with 128MB flash chips. OpenBMC-Staging-Count: 3 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: rainier: Add KCS node for LPC MCTPEddie James1-0/+5
OpenBMC-Staging-Count: 3 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: tacoma: Add KCS node for LPC MCTPAndrew Geissler1-0/+5
OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Geissler <geisonator@yahoo.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: witherspoon: Add KCS node for LPC MCTPAndrew Jeffery1-0/+5
The compatible is terrible, but we need a way to describe how we want to drive the hardware, and it's not in a fashion that's integrated into IPMI. OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: aspeed: Add PECI nodeJae Hyun Yoo3-0/+75
This commit adds PECI bus/adapter node into aspeed-g4, aspeed-g5 and aspeed-g6. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: nuvoton: evb: Rework enabling of nodesJoel Stanley1-443/+393
The Nuvoton device trees previously would describe a bunch of common devices in the board file. They are now described in a common dtsi, which was fine until the dtsi was updated and the board dts started conflicting. Move to using phandles to enable and configure common devices. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: nuvoton: Update EVB for new PECI layoutJoel Stanley1-12/+13
The PECI device tree layout changed, breaking the EVB. OpenBMC-Staging-Count: 3 Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06arm: dts: Add NPCM7xx RunBMC Olympus Quanta machine.Tomer Maimon3-1/+1681
Add Nuvoton NPCM7xx RunBMC Olympus Quanta board device tree. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au> olympus Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: nuvoton: Add Quanta GSJ BMCFran Hsu2-1/+525
The Quanta GSJ BMC uses the Nuvoton NPCM730 SoC. Included features: 1. Image partitions 2. PWM fan controller 3. USB device 4. Serial port 5. FIU 6. LEDs and GPIOs OpenBMC-Staging-Count: 6 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: nuvoton: Add Quanta GSJ BMC pinctrlFran Hsu1-0/+477
Add pinctrl definition for the Quanta GSJ BMC machine. OpenBMC-Staging-Count: 6 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: nuvoton: Add NPCM730 common device treeFran Hsu1-0/+57
Describe the common components of the NPCM730 SoC. OpenBMC-Staging-Count: 6 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: nuvoton: Fix warnings in NPCM7xx common device treeJoel Stanley1-9/+55
Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: npcm7xx: Update device treeTomer Maimon4-33/+3833
FIU, ADC, RST, VCD and SPI, PECI, regulator and HGPIO pins nodes. OpenBMC-Staging-Count: 8 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: configs: add defconfig for Nuvoton NPCM7xx BMCTomer Maimon1-0/+127
OpenBMC-Staging-Count: 8 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: aspeed-g6: Expose SuperIO scratch registersBrad Bishop1-0/+4
OpenBMC-Staging-Count: 4 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: aspeed-g4: Expose SuperIO scratch registersJoel Stanley1-0/+87
OpenBMC-Staging-Count: 10 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: aspeed-g5: Expose VGA and SuperIO scratch registersAndrew Jeffery1-0/+139
OpenBMC-Staging-Count: 11 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ARM: dts: aspeed: witherspoon: Update max31785 nodeAndrew Jeffery1-0/+52
Witherspoon contains four dual-tach fans. We configure them go to 100% when the fault pin is asserted, and disable the fan ramp watchdog. This preserves the behaviour of the previous driver. OpenBMC-Staging-Count: 12 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-04ARM: dts: Aspeed: tacoma: Enable EHCI controllerEddie James1-1/+5
Enable the second EHCI controller on the AST2600. Also add a line-name for the GPIO that controls power to the USB port. The power control is in place to allow the port to be disabled, for those that are worried about rogue USB sticks. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-04ARM: dts: aspeed: rainier: Enable EHCI controllerEddie James1-1/+5
Enable the second EHCI controller on the AST2600. Also add a line-name for the GPIO that controls power to the USB port. The power control is in place to allow the port to be disabled, for those that are worried about rogue USB sticks. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-04ARM: dts: aspeed: rainier: Switch OCCs to P10Eddie James1-3/+3
Rainier uses the P10 processor so the OCC binding should reflect that. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-04ARM: dts: aspeed: rainier: Add FSI I2C mastersJoel Stanley1-0/+21
The host processor contains i2c masters on each cfam. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-04ARM: dts: aspeed: rainier: Add CFAM SPI controllersEddie James1-0/+226
Add the four SPI masters on each CFAM. Each master has four 128KB EEPROM devices attached to it. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-04ARM: dts: aspeed: rainier: Add I2C buses for NVMe useJet Li1-0/+105
Adding pca9552 exposes the presence detect lines for the cards and tca9554 exposes the presence details for the cards. Signed-off-by: Jet Li <Jet.Li@ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-04ARM: dts: aspeed: Initial device tree for AMD EthanolXSupreeth Venkatesh2-0/+220
Initial introduction of AMD EthanolX platform equipped with an Aspeed ast2500 BMC manufactured by AMD. AMD EthanolX platform is an AMD customer reference board with an Aspeed ast2500 BMC manufactured by AMD. This adds AMD EthanolX device tree file including the flash layout used by EthanolX BMC machines. Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@amd.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-17 23:09:21 +0300