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2017-06-13arm64: dts: nvidia: fix PCI bus dtc warningsRob Herring3-3/+7
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-13arm64: tegra: Add CCPLEX_CLUSTER area in Tegra186Mikko Perttunen1-0/+7
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04arm64: tegra: Update the Tegra132 flowctrl compatible stringJon Hunter1-1/+1
Update the Tegra132 flowctrl compatible string to include "nvidia,tegra132-flowctrl" so it is aligned with the flowctrl binding documentation. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04arm64: tegra: Add GPU node for Tegra186Alexandre Courbot1-0/+19
Add the DT node for the GP10B GPU on Tegra186. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20arm64: tegra: Enable IOMMU for host1x on Tegra210Mikko Perttunen1-0/+2
The host1x driver now supports operation behind an IOMMU, so add its IOMMU domain to the device tree. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-20arm64: tegra: Enable VIC on Tegra210Mikko Perttunen1-1/+16
Enable the VIC (Video Image Compositor) host1x unit on Tegra210 systems. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-10arm64: tegra: Add GPIO expanders on P2771Thierry Reding1-0/+22
The P2771 development board expands the number of GPIOs via two I2C chips. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-10arm64: tegra: Add power monitors on P2771Thierry Reding1-0/+12
The P2771 development board comes with two power monitors that can be used to determine power consumption in different parts of the board. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-10arm64: tegra: Add GPIO keys on P2771Thierry Reding1-0/+34
The P2771 has three keys (power, volume up and volume down) that are connected to pins on the AON GPIO controller. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-10arm64: tegra: Enable current monitors on P3310Thierry Reding1-0/+10
The P3310 processor module contains two current monitors that can be used to determine the current flow across various parts of the board design. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-10arm64: tegra: Enable SD/MMC slot on P2771Thierry Reding1-0/+23
The P3310 processor module makes provisions for exposing the SDMMC1 controller via a standard SD/MMC slot, which the P2771 supports. Hook up the power supply provided on the P2771 carrier board and enable the device tree node. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-10arm64: tegra: Enable SDHCI controllers on P3110Thierry Reding1-0/+25
The P3110 processor module wires one of the SDHCI controllers to an on- board eMMC and exposes another set of SD/MMC signals on the connector to support an external SD/MMC card. A third controller is connected to the SDIO pins of an M.2 KEY E connector. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-10arm64: tegra: Add initial power tree for P3310Thierry Reding1-0/+220
Enable the Maxim MAX77620 PMIC found on P3310 and add some fixed regulators to model the power tree. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-08arm64: tegra: Enable ethernet on P3310Thierry Reding1-0/+20
The P3310 processor module provides networking via the ethernet controller found on NVIDIA Tegra186 SoCs. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-08arm64: tegra: Enable I2C controllers on P3310Thierry Reding1-1/+39
The P3310 processor modules use seven I2C controllers for various peripherals. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-08arm64: tegra: Invert the PMC interrupt on P3310Thierry Reding1-0/+4
The PMC interrupt is inverted on P3310, so mark it as such in the device tree to avoid a flood of interrupts when the PMIC is enabled. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-08arm64: tegra: Add ethernet support for Tegra186Thierry Reding1-0/+31
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data transfer rates. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-03-08arm64: tegra: Add PMC controller on Tegra186Thierry Reding1-0/+9
The NVIDIA Tegra186 SoC has a Power Management Controller that performs various tasks related to system power, boot as well as suspend/resume. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-27arm64: tegra: Use symbolic reset identifiersThierry Reding1-20/+21
Now that the corresponding device tree binding include has been merged, convert the DTS files to use symbolic names instead of numeric ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25arm64: tegra: Use symbolic clock identifiersThierry Reding1-20/+21
Now that the corresponding device tree binding include has been merged, convert the DTS files to use symbolic names instead of numeric ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25arm64: tegra: Use symbolic HSP identifiersThierry Reding1-1/+3
Now that the corresponding device tree binding include has been merged, convert the DTS files to use symbolic names instead of numeric ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-12-16Merge tag 'armsoc-dt64' of ↵Linus Torvalds4-0/+471
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "A couple of interesting new SoC platforms are now supported, these are the respective DTS sources: - Samsung Exynos5433 mobile phone platform, including an (almost) fully supported phone reference board. - Hisilicon Hip07 server platform and D05 board, the latest iteration of their product line, now with 64 Cortex-A72 cores across two sockets. - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product line, used in Android tablets and ultra-cheap development boards - NXP LS1046A Communication processor, improving on the earlier LS1043A with faster CPU cores - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810) mobile phone SoCs - Early support for the Nvidia Tegra Tegra186 SoC - Amlogic S905D is a minor variant of their existing Android consumer product line - Rockchip PX5 automotive platform, a close relative of their popular rk3368 Android tablet chips Aside from the respective evaluation platforms for the above chips, there are only a few consumer devices and boards added this time: - Huawei Nexus 6P (Angler) mobile phone - LG Nexus 5x (Bullhead) mobile phone - Nexbox A1 and A95X Android TV boxes - Pine64 development board based on Allwinner A64 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board For the existing platforms, we get bug fixes and new peripheral support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin, and ZTE" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits) arm64: dts: fix build errors from missing dependencies ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM: dts: artpec: add pcie support arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node arm64: dts: qcom: msm8916: Add ddr support to sdhc1 arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 ARM: dts: Add xo to sdhc clock node on qcom platforms ARM64: dts: Add support for Meson GXM dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 ...
2016-12-16Merge tag 'armsoc-fixes-nc' of ↵Linus Torvalds2-1/+20
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-urgent fixes from Arnd Bergmann: "As usual, we queue up a few fixes that don't seem urgent enough to go in through -rc, or that just came a little too late given their size. The zx fixes make the platform finally boot on real hardware, the davinci and imx31 get the DT support working better for some of the machines that are still normally used with classic board files. One tegra fix is important for new bootloader versions, but the bug has been around for a while without anyone noticing. The other changes are mostly cosmetic" * tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits) arm64: tegra: Add missing Smaug revision arm64: tegra: Add VDD_GPU regulator to Jetson TX1 arm64: dts: zte: clean up gic-v3 redistributor properties arm64: dts: zx: Fix gic GICR property bus: vexpress-config: fix device reference leak soc: ti: qmss: fix the case when !SMP ARM: lpc32xx: drop duplicate header device.h ARM: ixp4xx: drop duplicate header gpio.h ARM: socfpga: fix spelling mistake in error message ARM: dts: imx6q-cm-fx6: fix fec pinctrl ARM: dts: imx7d-pinfunc: fix UART pinmux defines ARM: dts: imx6qp: correct LDB clock inputs ARM: OMAP2+: pm-debug: Use seq_putc() in two functions ARM: OMAP2+: Remove the omapdss_early_init_of() function mfd: tps65217: Fix mismatched interrupt number ARM: zx: Fix error handling ARM: spear: Fix error handling ARM: davinci: da850: Fix pwm name matching ARM: clk: imx31: properly init clocks for machines with DT clk: imx31: fix rewritten input argument of mx31_clocks_init() ...
2016-12-08arm64: tegra: Add missing Smaug revisionAlexandre Courbot1-1/+2
The "google,smaug-rev2" string is missing from the compatible list of Smaug's DT. The differences of rev2 are not relevant at our current level of support and it boots just fine, so add it. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-12-08arm64: tegra: Add VDD_GPU regulator to Jetson TX1Alexandre Courbot1-0/+18
Add the VDD_GPU regulator (a GPIO-enabled PWM regulator) to the Jetson TX1 board. This addition allows the GPU to be used provided the bootloader properly enabled the GPU node. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [as pointed out by Thierry on IRC, nobody has reported a bug in the field, but using a new bootloader with a .dtb that has the incorrect data, it will crash on boot] Fixes: 336f79c7b6d7 ("arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit support") Cc: stable@vger.kernel.org #v4.5+ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-12-07arm64: tegra: Enable PCIe on Jetson TX1Thierry Reding1-0/+26
Enable the x4 PCIe and M.2 Key E slots on Jetson TX1. The Key E slot is currently untested due to lack of hardware. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-12-07arm64: tegra: Add PCIe host bridge on Tegra210Thierry Reding1-0/+63
Add the PCIe host bridge found on Tegra X1. It implements two root ports that support x4 and x1 configurations, respectively. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
2016-11-21arm64: tegra: Add NVIDIA P2771 board supportJoseph Lo2-0/+9
The NVIDIA P2771 is composed of a P3310 processor module that connects to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is connected via the P2597's display connector and has several connectors such as HDMI, USB 3.0, PCIe and ethernet. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21arm64: tegra: Enable PSCI on P3310Thierry Reding1-0/+32
The P3310 processor module comes ships with a firmware that implements PSCI 1.0. Enable and use it to bring up all CPUs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21arm64: tegra: Add NVIDIA P3310 processor module supportJoseph Lo1-0/+32
The NVIDIA P3310 is a processor module used in several reference designs that features a Tegra186 SoC, 8 GiB of LPDDR4 RAM, 32 GiB eMMC and other essentials such as ethernet, WiFi and a PMIC. It is typically connected to an I/O board (such as the P2597) that provides the connecters needed to hook it up to the outside world. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21arm64: tegra: Add GPIO controllers on Tegra186Thierry Reding1-0/+30
Tegra186 has two GPIO controllers that are no longer compatible with the controller found on earlier generations. One of these controllers exists in an always-on partition of the SoC whereas the other can be clock- and powergated. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21arm64: tegra: Add SDHCI controllers on Tegra186Thierry Reding1-0/+44
Tegra186 has a total of four SDHCI controllers that each support SD 4.2 (up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and SDHOST 4.1 (up to UHS-I speed). Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21arm64: tegra: Add I2C controllers on Tegra186Thierry Reding1-0/+120
Tegra186 has a total of nine I2C controllers that are compatible with the I2C controllers introduced in Tegra114. Two of these controllers share pads with two DPAUX controllers (for AUX transactions). Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21arm64: tegra: Add serial ports on Tegra186Thierry Reding1-0/+76
The initial patch only added UARTA, but there's no reason we shouldn't be adding all of them. While at it, also specify the missing clocks and resets for UARTA. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21arm64: tegra: Add CPU nodes for Tegra186Thierry Reding1-0/+41
Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that support ARMv8 and four CPUs are Cortex-A57 CPUs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-21arm64: tegra: Add Tegra186 supportJoseph Lo1-0/+87
This adds the initial support of Tegra186 SoC. It provides enough to enable the serial console and boot from an initial ramdisk. Signed-off-by: Joseph Lo <josephl@nvidia.com> [treding@nvidia.com: remove leading 0 from unit-addresses] [treding@nvidia.com: remove unused nvidia,bpmp property] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-10-12Merge branch 'next' of ↵Linus Torvalds2-2/+244
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux Pull thermal managament updates from Zhang Rui: - Enhance thermal "userspace" governor to export the reason when a thermal event is triggered and delivered to user space. From Srinivas Pandruvada - Introduce a single TSENS thermal driver for the different versions of the TSENS IP that exist, on different qcom msm/apq SoCs'. Support for msm8916, msm8960, msm8974 and msm8996 families is also added. From Rajendra Nayak - Introduce hardware-tracked trip points support to the device tree thermal sensor framework. The framework supports an arbitrary number of trip points. Whenever the current temperature is changed, the trip points immediately below and above the current temperature are found, driver callback is invoked to program the hardware to get notified when either of the two trip points are triggered. Hardware-tracked trip points support for rockchip thermal driver is also added at the same time. From Sascha Hauer, Caesar Wang - Introduce a new thermal driver, which enables TMU (Thermal Monitor Unit) on QorIQ platform. From Jia Hongtao - Introduce a new thermal driver for Maxim MAX77620. From Laxman Dewangan - Introduce a new thermal driver for Intel platforms using WhiskeyCove PMIC. From Bin Gao - Add mt2701 chip support to MTK thermal driver. From Dawei Chien - Enhance Tegra thermal driver to enable soctherm node and set "critical", "hot" trips, for Tegra124, Tegra132, Tegra210. From Wei Ni - Add resume support for tango thermal driver. From Marc Gonzalez - several small fixes and improvements for rockchip, qcom, imx, rcar, mtk thermal drivers and thermal core code. From Caesar Wang, Keerthy, Rocky Hao, Wei Yongjun, Peter Robinson, Bui Duc Phuc, Axel Lin, Hugh Kang * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (48 commits) thermal: int3403: Process trip change notification thermal: int340x: New Interface to read trip and notify thermal: user_space gov: Add additional information in uevent thermal: Enhance thermal_zone_device_update for events arm64: tegra: set hot trips for Tegra210 arm64: tegra: set critical trips for Tegra210 arm64: tegra: add soctherm node for Tegra210 arm64: tegra: set hot trips for Tegra132 arm64: tegra: set critical trips for Tegra132 arm64: tegra: use tegra132-soctherm for Tegra132 arm: tegra: set hot trips for Tegra124 arm: tegra: set critical trips for Tegra124 thermal: tegra: add hw-throttle for Tegra132 thermal: tegra: add hw-throttle function of: Add bindings of hw throttle for Tegra soctherm thermal: mtk_thermal: Check return value of devm_thermal_zone_of_sensor_register thermal: Add Mediatek thermal driver for mt2701. dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: max77620: Add thermal driver for reporting junction temp thermal: max77620: Add DT binding doc for thermal driver ...
2016-09-27arm64: tegra: set hot trips for Tegra210Wei Ni1-9/+32
Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: set critical trips for Tegra210Wei Ni1-0/+60
Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: add soctherm node for Tegra210Wei Ni1-0/+44
Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: set hot trips for Tegra132Wei Ni1-9/+32
Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: set critical trips for Tegra132Wei Ni1-0/+60
Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra132, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-09-27arm64: tegra: use tegra132-soctherm for Tegra132Wei Ni1-2/+34
The Tegra132 has the specific settings for soctherm, so change to use campatible "nvidia,tegra132-soctherm" for it. And adds cpu, gpu, mem and pllx thermal zones. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2016-08-24arm64: tegra: Enable XUSB controller on Tegra210 SmaugJon Hunter1-0/+57
Enable the XUSB controller on Tegra210 Smaug. The Smaug has a USB Type-C connector with one of the USB2.0 lanes and one of the USB3.0 lanes populated. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add the various audio devices for Tegra210 SmaugJon Hunter1-0/+45
The Tegra210 Smaug includes the Realtek RT5677 audio codec, Nuvoton NAU8825 headset codec and the Maxim MAX98357a audio amplifier. Add the nodes for these devices for the Tegra210 Smaug. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> [treding@nvidia.com: use interrupts property consistently] Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Enable DPAUX for Tegra210 SmaugJon Hunter1-0/+6
The Tegra210 Smaug uses I2C6 for interfacing to various audio chips. I2C6 shares pads with the DPAUX interface and to allow I2C6 to request the pads owned by DPAUX, the DPAUX device needs to be enabled. Enable DPAUX for Tegra210 Smaug. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add ACONNECT, ADMA and AGIC nodes Tegra210 SmaugJon Hunter1-0/+12
Populate the ACONNECT, ADMA and AGIC nodes for Tegra210 Smaug which are used for audio use-cases. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add SOR power-domain for Tegra210Jon Hunter1-0/+27
Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add ADMA node for Tegra210Jon Hunter1-0/+32
Populate the ADMA node for Tegra210. The ADMA is used by the Audio Processing Engine (APE) on Tegra210 for moving data between the APE and system memory. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24arm64: tegra: Add AGIC node for Tegra210Jon Hunter1-0/+12
Populate the Audio GIC (AGIC) node for Tegra210. This interrupt controller is used by the Audio Processing Engine to route interrupts to the main CPU interrupt controller. The AGIC is based on the ARM GIC400 and so uses the clock name "clk" as specified by the GIC binding document for GIC400 devices. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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