| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-02-06 | ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant | Vineet Gupta | 1 | -1/+0 | |
| A typical SMP system expects cache coherency. Initial NPS platform support was slated to be SMP w/o cache coherency. However it seems the platform now selects that option, so there is no point in keeping it around. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> | |||||
| 2015-06-19 | ARC: [plat_arcfpga]->[plat_sim] | Vineet Gupta | 1 | -0/+14 | |
| * Remove remanants of legacy ARC FPGA platforms (AA4, ML509...) * Only nsim simulation platform is left, rename platform accordingly * AA4 DT stuff is compatible with nsim for ARC700 so rename it too Signed-off-by: Vineet Gupta <vgupta@synopsys.com> | |||||
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index : BMC/Intel-BMC/linux.git | |
| Intel OpenBMC Linux kernel source tree (mirror) | Andrey V.Kosteltsev |
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