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2021-11-01ARM: dts: olympus: Add non-mainline nodesTomer Maimon1-0/+112
This is the remaining non-mainline component of the patch that adds the Opympus machine. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: nuvoton: gsj: Add non-mainline nodesFran Hsu1-0/+36
This is the remaining non-mainline component of the patch that adds the GSJ machine. OpenBMC-Staging-Count: 4 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: nuvoton: npcm730: Add UDC deviceFran Hsu1-1/+14
This is the remaining non-mainline component of the patch that adds the NPCM730 common device tree. OpenBMC-Staging-Count: 4 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: npcm7xx: Add out of tree nodesTomer Maimon4-6/+2579
FIU, ADC, RST, VCD and SPI, PECI, regulator and HGPIO pins nodes. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: aspeed: witherspoon: Update max31785 nodeAndrew Jeffery1-0/+52
Witherspoon contains four dual-tach fans. We configure them go to 100% when the fault pin is asserted, and disable the fan ramp watchdog. This preserves the behaviour of the previous driver. OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01net: npcm: Support for fixed PHYsWilliam A. Kennington III1-1/+30
Most of our machines don't have PHYs between the NIC and the BMC over their NC-SI port. We don't want to use the kernel NC-SI machinery, but we do want phyless support. OpenBMC-Staging-Count: 3 Signed-off-by: William A. Kennington III <wak@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210327004920.388957-1-wak@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01net: npcm: add NPCM7xx Ethernet MAC controllerTomer Maimon5-0/+2122
Add Nuvoton BMC NPCM7xx Ethernet MAC controller (EMC) driver. OpenBMC-Staging-Count: 11 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-binding: net: document NPCM7xx EMC DT bindingsTomer Maimon1-0/+36
Added device tree binding documentation for Nuvoton NPCM7xx Ethernet MAC Controller (EMC). OpenBMC-Staging-Count: 11 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01misc: mbox: add npcm7xx pci mailbox driverTomer Maimon3-0/+296
Add Nuvoton BMC NPCM7XX PCI Mailbox driver. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [v5.0: Fix access_ok for API change] Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-binding: bmc: add npcm7xx pci mailbox documentTomer Maimon1-0/+19
Added device tree binding documentation for Nuvoton BMC NPCM7XX PCI mailbox. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01misc: npcm7xx-lpc-bpc: add NPCM7xx BIOS post code driverTomer Maimon3-0/+403
Add NPCM7xx BIOS post code (BPC) driver, the BPC monitoring two I/O address written by the host on the LPC. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-binding: bmc: Add NPCM7xx LPC BPC documentationTomer Maimon1-0/+26
Added device tree binding documentation for Nuvoton BMC NPCM7xx BIOS Post Code (BPC). The NPCM7xx BPC monitoring two configurable I/O addresses written by the host on Low Pin Count (LPC) bus. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01/dev/mem: add a devmem kernel parameter to activate the deviceCédric Le Goater3-0/+23
For security reasons, some configuration needs to run without /dev/mem but on some occasions, to debug HW for instance, it's still useful to be able to reboot the system with access to physical memory. Add a kernel parameter which activates the /dev/mem device only when 'mem.devmem' is enabled. OpenBMC-Staging-Count: 12 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01pmbus (max31785): Wrap all I2C accessors in one-shot failure handlersAndrew Jeffery1-42/+165
The MAX31785(A) has shown erratic behaviour across multiple system designs, unexpectedly clock stretching and NAKing transactions. Perform a one-shot retry if necessary for all access attempts. OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01pmbus (core): One-shot retries for failure to set pageAndrew Jeffery1-2/+12
Work around the shonky behaviour seen with the MAX31785 where we fail to set the page register in some circumstances. There's no real elegant way to do this. We can propagate the error up, but that forces us to retry the operation way up the call tree in any number of places. It also forces callers to split out pmbus_set_page() from the pmbus_{read,write}_{byte,word}_data() functions in order to differentiate between a failure to set the page and a failure to read a register (that might not exist, in which case an error is anticiptated). OpenBMC-Staging-Count: 15 Cc: Eddie James <eajames@linux.vnet.ibm.com> Cc: Matt Spinler <mspinler@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01pmbus (core): Use driver callbacks in pmbus_get_fan_rate()Andrew Jeffery1-4/+4
The driver may have overridden the pmbus_read_byte_data() callback, so make sure we use that to achieve expected behaviour. This helps in the MAX31785 case where we may need to perform a one-shot retry of transfers in the face of a failure. OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01pmbus (max31785): Add support for devicetree configurationAndrew Jeffery1-0/+318
OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-bindings: hwmon: pmbus: Add Maxim MAX31785 documentationAndrew Jeffery1-0/+158
OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: add support for AST2600 trainingCédric Le Goater1-0/+69
The training consists of finding the appropriate read timing delays for the HCLK dividers 2, 3, 4, and 5 and store the results in the Read Timing Compensation register. The previous SoC AST2500 and AST2400 were covering a broader HCLK range [ 1 - 5 ] because the AHB frequency was lower. The algorithm first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find a breaking point. This selects the default clock frequency for the CEx control register. The current settings are bit optimistic as we pick the first delay giving good results. A safer approach would be to determine an interval and choose the middle value. We might change the approach depending on the results on other systems. Only CS0 is taken into account for the moment. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: check upper freq limit when doing trainingCédric Le Goater1-1/+1
OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: Introduce a HCLK mask for trainingCédric Le Goater1-1/+6
The AST2600 handles more HCLK divisors than its predecessors. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: Introduce training operations per platformCédric Le Goater1-4/+22
The read timing compensation register is different on the AST2600 and training will be slightly more complex. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: Check for disabled segments on the AST2600Cédric Le Goater1-4/+11
The segments can be disabled on the AST2600 (zero register value). CS0 is open by default but not the other CS. This is closing the access to the flash device in user mode and forbids scanning. For multiple CS, we will need firmware or a DT property to reopen the flash AHB window. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: add initial support for ast2600Cédric Le Goater1-0/+77
The Segment Registers of the AST2600 have a different encoding. A 1MB unit is used and the address range of a flash SPI slave is encoded with offsets in the overall controller window. The previous SoC AST2400 and AST2500 used absolute addresses. Only bits [27:20] are relevant and the end address is an upper bound limit. SPI training yet to come. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: Introduce segment operationsCédric Le Goater1-20/+56
AST2600 will use a different encoding for the addresses defined in the Segment Register. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: Introduce a field for the AHB physical addressCédric Le Goater1-12/+6
On the AST2600, we will use it to compute the address of the chip AHB window from the Segment Register value. It also removes the need of aspeed_smc_ahb_base_phy() helper. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: Add support for w25q512jvCédric Le Goater1-0/+2
OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: add support for the 4B opcodesCédric Le Goater1-2/+9
Switch the default controller value to use the read mode in order to customize the command and use SPINOR_OP_READ_4B (0x13) when the chip supports 4B opcodes. OpenBMC-Staging-Count: 10 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2021-11-01mtd: spi-nor: aspeed: use memcpy_fromio() to capture the optimization bufferCédric Le Goater1-4/+2
aspeed_smc_read_from_ahb() only reads the first word which is not what we want. We want to capture a CALIBRATE_BUF_SIZE size window of the flash contents to optimize the read. OpenBMC-Staging-Count: 10 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2021-11-01mtd: spi-nor: aspeed: clarify 4BYTE address mode maskCédric Le Goater1-1/+9
OpenBMC-Staging-Count: 10 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2021-11-01mtd: spi-nor: aspeed: introduce a aspeed_smc_default_read() helperCédric Le Goater1-7/+12
OpenBMC-Staging-Count: 10 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2021-11-01mtd: spi-nor: aspeed: limit the maximum SPI frequencyCédric Le Goater1-4/+13
The optimize read algo can choose a 100MHz SPI frequency which might be a bit too high for dual output IO on some chips, for the W25Q256 on palmetto for instance. The MX66L1G45G on witherspoon should be fine though. Also, the second chip of the FMC controller does not get any optimize settings for reads. Only the first is configured by U-Boot. To fix these two issues, we introduce a "spi-max-frequency" property in the device tree which will be used to cap the optimize read algorithm and we run the algo on the FMC controller chips as well. By default, the frequency setting is 50MHz. OpenBMC-Staging-Count: 13 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: optimize read modeCédric Le Goater1-0/+191
This is only for SPI controllers as U-Boot should have done it already for the FMC controller using DMAs. The algo is based on the one found in the OpenPOWER pflash tool. It first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find the fastest configuration for the chip. It can be deactivated at boot time with the kernel parameter : aspeed_smc.optimize_read=0 OpenBMC-Staging-Count: 14 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: link controller with the ahb clockCédric Le Goater1-0/+10
We will need the AHB frequency to set the HCLK settings in the SMC controller to optimize the reads. OpenBMC-Staging-Count: 14 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: add support for SPI dual IO read modeCédric Le Goater1-11/+43
Implements support for the dual IO read mode on aspeed SMC/FMC controllers which uses both MISO and MOSI lines for data during a read to double the read bandwidth. Still to be done SNOR_PROTO_1_2_2 Based on work from Robert Lippert <roblip@gmail.com> OpenBMC-Staging-Count: 14 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01mtd: spi-nor: aspeed: use command mode for readsCédric Le Goater1-1/+27
When reading flash contents, try to use the "command mode" if the AHB window configured for the flash module is big enough. Else, just fall back to the "user mode" to perform the read. OpenBMC-Staging-Count: 14 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01soc: aspeed: xdma: Add reset ioctlEddie James2-0/+36
Users of the XDMA engine need a way to reset it if something goes wrong. Problems on the host side, or user error, such as incorrect host address, may result in the DMA operation never completing and no way to determine what went wrong. Therefore, add an ioctl to reset the engine so that users can recover in this situation. Signed-off-by: Eddie James <eajames@linux.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/1588697905-23444-5-git-send-email-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01soc: aspeed: xdma: Add user interfaceEddie James1-0/+217
This commits adds a miscdevice to provide a user interface to the XDMA engine. The interface provides the write operation to start DMA operations. The DMA parameters are passed as the data to the write call. The actual data to transfer is NOT passed through write. Note that both directions of DMA operation are accomplished through the write command; BMC to host and host to BMC. The XDMA driver reserves an area of physical memory for DMA operations, as the XDMA engine is restricted to accessing certain physical memory areas on some platforms. This memory forms a pool from which users can allocate pages for their usage with calls to mmap. The space allocated by a client will be the space used in the DMA operation. For an "upstream" (BMC to host) operation, the data in the client's area will be transferred to the host. For a "downstream" (host to BMC) operation, the host data will be placed in the client's memory area. Poll is also provided in order to determine when the DMA operation is complete for non-blocking IO. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/1588697905-23444-4-git-send-email-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01soc: aspeed: Add XDMA Engine DriverEddie James5-0/+1014
The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI DMA operations between the SOC (acting as a BMC) and a host processor in a server. This commit adds a driver to control the XDMA engine and adds functions to initialize the hardware and memory and start DMA operations. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/1588697905-23444-3-git-send-email-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-bindings: hwmon/pmbus: Add ti,lm25066 power-management ICZev Weiss1-0/+54
Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210928092242.30036-9-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01hwmon: (pmbus/lm25066) Support configurable sense resistor valuesZev Weiss1-0/+11
The appropriate mantissa values for the lm25066 family's direct-format current and power readings are a function of the sense resistor employed between the SENSE and VIN pins of the chip. Instead of assuming that resistance is always the same 1mOhm as used in the datasheet, allow it to be configured via a device-tree property ("shunt-resistor-micro-ohms"). Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-8-zev@bewilderbeest.net [groeck: Fixed checkpatch warnings] Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01hwmon: (pmbus/lm25066) Add OF device ID tableZev Weiss1-2/+23
The driver doesn't have a struct of_device_id table but supported devices are registered via Device Trees. This is working on the assumption that a I2C device registered via OF will always match a legacy I2C device ID and that the MODALIAS reported will always be of the form i2c:<device>. But this could change in the future so the correct approach is to have an OF device ID table if the devices are registered via OF. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-7-zev@bewilderbeest.net [groeck: Replaced reference to reasoning with reasoning, fixed checkpatch warnings, fixed compile warning comparing of_id->data w/ i2c_id->driver_data] Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01hwmon: (pmbus/lm25066) Mark lm25066_coeff array constZev Weiss1-2/+2
lm25066_coeff is read-only. Mark it as such. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-6-zev@bewilderbeest.net [groeck: Added description] Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01hwmon: (pmbus/lm25066) Let compiler determine outer dimension of lm25066_coeffZev Weiss1-1/+1
Maintaining this manually is error prone (there are currently only five chips supported, not six); gcc can do it for us automatically. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Fixes: 666c14906b49 ("hwmon: (pmbus/lm25066) Drop support for LM25063") Link: https://lore.kernel.org/r/20210928092242.30036-5-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01hwmon: (pmbus/lm25066) Avoid forward declaration of lm25066_idZev Weiss1-13/+10
Reordering things to put the table before the probe function eliminates the need for it. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-4-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01hwmon: (pmbus/lm25066) Adjust lm25066 PSC_CURRENT_IN_L mantissaZev Weiss1-1/+1
At least as of Revision J, the datasheet has a slightly different value than what we'd had in the driver. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-3-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01hwmon: (pmbus/lm25066) Add offset coefficientsZev Weiss1-0/+23
With the exception of the lm5066i, all the devices handled by this driver had been missing their offset ('b') coefficients for direct format readings. Cc: stable@vger.kernel.org Fixes: 58615a94f6a1 ("hwmon: (pmbus/lm25066) Add support for LM25056") Fixes: e53e6497fc9f ("hwmon: (pmbus/lm25066) Refactor device specific coefficients") Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-2-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-bindings: soc: Add Aspeed XDMA EngineEddie James2-0/+109
Document the bindings for the Aspeed AST25XX and AST26XX XDMA engine. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/1588697905-23444-2-git-send-email-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01iio: adc: aspeed: Fix spelling mistake "battey" -> "battery"Colin Ian King1-1/+1
There is a spelling mistake in a dev_warn message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20211001120018.17570-1-colin.king@canonical.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01iio: adc: aspeed: Get and set trimming data.Billy Tsai1-0/+71
The ADC controller has a trimming register for fine-tune the reference voltage. The trimming value comes from the OTP register which will be written during chip production. This patch will read this OTP value and configure it to the ADC register when the ADC controller probes and using dts property "aspeed,trim-data-valid" to determine whether to execute this flow. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-12-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
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