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2012-03-22drm/nouveau: bump version to 1.0.0Ben Skeggs1-4/+4
The time has come to get a proper version number that we can change to indicate new features etc, rather than the lock-step 0.0.XX that we previously had. libdrm has recognised this version as compatible with 0.0.16 since 2.4.22, so hopefully any breakage people see should be very minimal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nvd0/disp: ignore clock set if no pclkBen Skeggs1-1/+3
This happens somehow during init on a machine I have, and leads to a divide-by-zero. Lets avoid that... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: oops, increase channel dispc_vma to 4Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: inform userspace of new kernel subchannel requirementsBen Skeggs2-13/+6
All available subchannels are now available for userspace to do with as it pleases on NVC0+. On all earlier chipsets, the kernel still uses a software object on subc 0 to implement the page flip completion method. I hope to find some decent way of addressing this too, but it's a tad tricker prior to fermi. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: remove m2mf creation on userspace channelsBen Skeggs4-81/+93
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nvc0-/disp: reimplement flip completion method as fifo methodBen Skeggs4-18/+42
Removes need for M2MF subchannel usage on NVC0+. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: move fence sequence check to start of loopBen Skeggs1-6/+5
I want to be able to use REF_CNT from other places in the kernel without pushing a fence object onto the list of emitted fences. The current code makes an assumption that every time the acked sequence is bumped that there's at least one fence on the list that'll be signalled. This will no longer be true in the near future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: remove subchannel names from places where it doesn't matterBen Skeggs4-25/+38
These are FIFO methods, it doesn't matter what subchannel is being used. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau/ttm: always do buffer moves on kernel channelBen Skeggs3-19/+4
There was once good reasons for wanting the drm to be able to use M2MF etc on user channels, but they're not relevant anymore. For the general buffer move case, we've already lost by transferring between vram/sysmem already so the context switching overhead is minimal in comparison. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau: map first page of mmio early and determine chipset earlierBen Skeggs2-63/+62
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: disconnect encoders before reprogramming themBen Skeggs1-33/+33
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: move syncs/magic setup to or mode_setBen Skeggs1-20/+39
NVIDIA appear to do these around the same place they do the MODE_CTRL methods, and for DP at least we need to bash some extra bits in "syncs" to keep EVO happy. It's a bit of a guess as to the 6/8bpc, but i have no better idea yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: account for channel coding overhead in link trainingBen Skeggs1-0/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: fix dcb sor link matching in supervisor handlerBen Skeggs1-8/+9
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: initial implementation of displayportBen Skeggs2-4/+171
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: make dp dpms function common, call from sor code insteadBen Skeggs3-22/+31
GF119 will use this too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/hwsq: some nv92 fixesMartin Peres1-2/+3
The shift from hwsq_data = 0x1400 to 0x080000 actually happened in nv94, not nv92 This fixes some reclocking issues on my newly acquired nv92 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: move all nv50/sor-specific code out of nouveau_dp.cBen Skeggs5-228/+231
Off-chip encoders (which we don't support yet anyway), and newer chipsets (such as NVD9...), will need their own code for this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: make functions for executing various bios tablesBen Skeggs1-9/+46
More code to do the same thing, but will make it easier to handle various changes that could possibly happen the the VBIOS tables. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: fix oops if chipset has no pm support at allBen Skeggs1-3/+5
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/bios: rework vbios shadowingBen Skeggs2-121/+158
Refactored to allow shadowing of VBIOS images longer than 64KiB, which allows us to pass the VBIOS checksum test on certain boards. There's also a workaround for reading the PROM VBIOS on some chipsets. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/bios: attempt acpi rom fetch before pciromBen Skeggs1-1/+1
There's cards out there with completely messed up PCIROM images that have a perfectly valid signature.. Sigh! Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: attempt to handle more than 2 crtcs if possibleBen Skeggs1-19/+14
Theoretically handles CRTC2/CRTC3, should any GF119 out there actually have them enabled. The room is there for the regs etc, so why not :) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/vram: get part count from PUNITSBen Skeggs1-16/+14
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv40/pm: fix fanspeed regressionBen Skeggs1-0/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: several fixes for nvc0 memory timingsRoy Spliet1-3/+6
This patch fixes two small issues in timing generation as spotted on several NVCx cards. In addition, the header of the file is updated to also contain (some of) the current developers of this code. Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/pm: restrict pll mode to clocks that can actually use itBen Skeggs1-1/+1
Fixes reclocking failure on some chips where we attempted to set PDAEMON to PLL mode. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: fix bad comparison in dp_link_train_commit()Xi Wang1-1/+1
The comparison (lpre == DP_TRAIN_PRE_EMPHASIS_9_5) is always false: lpre is initialized as (lane & 0x0c) >> 2, which is at most 3, while DP_TRAIN_PRE_EMPHASIS_9_5 is defined as (3 << 3). Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/mxm: call mxmi to determine revision before calling mxmsBen Skeggs1-1/+38
There's a HP laptop out there where the MXM version in the VBIOS doesn't match what the ACPI implementation is expecting. These tables will accept 0x00 to MXMS to return latest version, but *only* if MXMI has been called first.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: init only after display subsystem has been createdBen Skeggs1-7/+5
This patch fixes an oops cause by pm_trigger accessing the (uninitialised) crtc list. Reported-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/fb: detect presense of second rankBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/display: expose color vibrance controlChristoph Bumiller6-3/+85
Signed-off-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50-nvc0/vm: support unsnooped system memoryBen Skeggs3-17/+17
v2 (Emil Velikov <emil.l.velikov@gmail.com>): - Fixed a regression on certain nv50 IGP due to not passing the correct target type to nv50_vm_addr() Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Tested-by: Johannes Obermayr <johannesobermayr@gmx.de>
2012-03-13drm/nouveau: recognise DCB connector type for DP+DVI+VGA DMS-59Ben Skeggs2-1/+7
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/mem: handle dll_off for ddr2/ddr3Ben Skeggs1-11/+23
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: extend profile interface for destroy/init/finiBen Skeggs2-0/+25
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: rework to allow selecting separate profiles for ac/batteryBen Skeggs4-46/+120
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: fix dll off -> dll on transitionsBen Skeggs1-2/+7
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: detect when we need dll disabled for gddr3Ben Skeggs3-1/+12
Fixes minor flickering on NVS295 when at perflvl 0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50: fix detection of second vram rankBen Skeggs1-1/+1
Goes a long way to correcting NVS295 memory reclocking issues. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: track mr2 for gddr3Ben Skeggs1-1/+4
There's some "extended" GDDR3 chipsets out there with EMRS2 settings that change the layout of MRS/EMRS1 bitmaps.. Sigh.. Still need to track down how exactly we're supposed to handle this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/pm: wait for all fifo-connected engines to idle before reclockingMartin Peres1-0/+2
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/pm: use hwsq for engine reclocking tooBen Skeggs1-87/+98
Idea from Martin Peres, different implementation by me. v2: Martin Peres: - fix mast calculation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/disp: more accurate function to determine active crtcsBen Skeggs3-8/+28
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/pm: initial work towards proper memory reclocking, with timingsBen Skeggs1-46/+154
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: introduce ram reclocking helperBen Skeggs2-0/+114
This will probably result in more lines of code, however, we're going to have at least 3 slightly different implementations of this very soon and I'd rather keep the ram reclocking logic separate from the hw specifics. DDR2/DDR3/GDDR3 implemented thus far, others will be added as necessary. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: embed timings into perflvl structsBen Skeggs4-58/+54
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: calculate memory timings at perflvl creation timeBen Skeggs5-298/+132
Statically generating the PFB register and MR values for each timing set turns out to be insufficient. There's at least one (so far) known piece of information which effects MR values which is stored in the perflvl entry on some chipsets (and in another table on later ones), which is disconnected from the timing table entries. After this change we will generate a timing set based on an input clock frequency instead, and have this data stored in the performance level data. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: readback boot perflvl *before* parsing vbiosBen Skeggs1-11/+19
We might want/need the boot data to generate the other perflevels. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validationRoy Spliet4-152/+476
Roy Spliet: - Implement according to specs - Simplify - Make array for mc latency registers Martin Peres: - squash and split all the commits from Roy - rework following Ben Skeggs comments - add a form of timings validation - store the initial timings for later use Ben Skeggs - merge slightly modified tidy-up patch with this one - remove perflvl-dropping logic for the moment Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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