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2016-09-07clk: bcm2835: Mark GPIO clocks enabled at boot as criticalEric Anholt1-1/+9
These divide off of PLLD_PER and are used for the ethernet and wifi PHYs source PLLs. Neither of them is currently represented by a phy device that would grab the clock for us. This keeps other drivers from killing the networking PHYs when they disable their own clocks and trigger PLLD_PER's refcount going to 0. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-07clk: bcm2835: Mark the VPU clock as criticalEric Anholt1-1/+4
The VPU clock is also the clock for our AXI bus, so we really can't disable it. This might have happened during boot if, for example, uart1 (aux_uart clock) probed and was then disabled before the other consumers of the VPU clock had probed. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-07Merge tag 'v4.9-rockchip-clk1' of ↵Stephen Boyd9-20/+278
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: The biggest addition is probably the special clock-type for ddr clock control. While reading that clock is done the normal way from the registers, setting it always requires some sort of special handling to let the system survive this addition. As the commit message explains, there are currently 3 handling-types known. General SRAM-based code on rk3288 and before (which is waiting essentially for the PIE support that is currently being worked on), SCPI-based clk setting on the rk3368 through a coprocessor, which we might support once the support for legacy scpi-variants has matured and now on the rk3399 (and probably later) using a dcf controller that is controlled from the arm-trusted-firmware and gets accessed through firmware calls from the kernel. This is the variant we currently support, but the clock type is made to support the other variants in the future as well. Apart from that slightly bigger chunk, we have a mix of PLL rates, clock-ids and flags mainly for the rk3399. And interestingly an iomap fix for the legacy gate driver, where I hopefully could deter the submitter from actually using that in any new works. * tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: use the dclk_vop_frac clock ids on rk3399 clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers clk: rockchip: add 2016M to big cpu clk rate table on rk3399 clk: rockchip: add rk3399 ddr clock support clk: rockchip: add dclk_vop_frac ids for rk3399 vop clk: rockchip: add new clock-type for the ddrclk soc: rockchip: add header for ddr rate SIP interface clk: rockchip: add SCLK_DDRC id for rk3399 ddrc clk: rockchip: handle of_iomap failures in legacy clock driver clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical clk: rockchip: use general clock flag when registering pll clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399 clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
2016-09-07MAINTAINERS: Add section for Renesas clock driversGeert Uytterhoeven1-0/+6
Add a section for Renesas clock drivers, as found on Renesas ARM SoCs, and list myself as the maintainer. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-05clk: rockchip: use the dclk_vop_frac clock ids on rk3399Yakir Yang1-2/+2
Export the dclk_vop_frac out, so we can set the dclk_vop as the child of dclk_vop_frac, and then we can start to take use of the fractional dividers. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-05clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividersDouglas Anderson1-13/+13
Currently the fractional divider clock time can't handle the CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers, there is no clk_divider_bestdiv() function to try speeding up the parent to see if it helps things. Eventually someone could try to figure out how to make fractional dividers able to use CLK_SET_RATE_PARENT, but until they do let's not confuse the common clock framework (and anyone using it) by setting the flag. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-04clk: rockchip: add 2016M to big cpu clk rate table on rk3399Shunqian Zheng1-0/+1
We would prefer the 2016M as 2.0G than 1992M which seems odd, adding it to big cpu clk rate table then we can set 2016M in dts. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-04clk: rockchip: add rk3399 ddr clock supportLin Huang1-0/+19
add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-04Merge branch 'v4.9-shared/clkids' into v4.9-clk/nextHeiko Stuebner1-0/+3
2016-09-04clk: rockchip: add dclk_vop_frac ids for rk3399 vopYakir Yang1-0/+2
Export the dclk_vop_frac out, so we can set the dclk_vop as the child of dclk_vop_frac, and then we can start to take use of the fractional dividers. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-03Merge branch 'clk-meson-gxbb' into clk-nextMichael Turquette8-121/+506
2016-09-03clk: meson-gxbb: Export PWM related clocks for DTNeil Armstrong2-3/+6
Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com
2016-09-02meson: clk: Add support for clock gatesAlexander Müller2-0/+254
This patch adds support for the meson8b clock gates. Most of them are disabled by Amlogic U-Boot, but need to be enabled for ethernet, USB and many other components. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-7-git-send-email-serveralex@gmail.com
2016-09-02gxbb: clk: Adjust MESON_GATE macro to be shared with meson8bAlexander Müller2-85/+85
The macro used gxbb_ prefix for clock definitions. In order to share the macro between gxbb and meson8b, the prefix must be moved to gxbb.c. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-6-git-send-email-serveralex@gmail.com
2016-09-02clk: meson: Copy meson8b CLKID defines to private header fileAlexander Müller3-3/+107
Only expose future CLKID constants if necessary. This patch removes CLK_NR_CLKS from the DT bindings but leaves all previously defined CLKIDs there to keep backward compatibility. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-5-git-send-email-serveralex@gmail.com
2016-09-02meson: clk: Rename register names according to Amlogic datasheetAlexander Müller2-19/+18
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-4-git-send-email-serveralex@gmail.com
2016-09-02meson: clk: Move register definitions to meson8b.hAlexander Müller2-16/+41
Move the register definitions into a separate header file to reflect the gxbb implementation. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-3-git-send-email-serveralex@gmail.com
2016-09-02clk: meson: Rename meson8b-clkc.c to reflect gxbb naming conventionAlexander Müller2-1/+1
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-2-git-send-email-serveralex@gmail.com
2016-09-02Merge remote-tracking branch 'clk/clk-meson-gxbb-ao' into clk-meson-gxbbMichael Turquette5-1/+369
2016-09-01clk: rockchip: add new clock-type for the ddrclkLin Huang4-0/+197
Changing the rate of the DDR clock needs special care, as the DDR is of course in use and will react badly if the rate changes under it. Over time different approaches to handle that were used. Past SoCs like the rk3288 and before would store some code in SRAM while the rk3368 used a SCPI variant and let a coprocessor handle that. New rockchip platforms like the rk3399 have a dcf controller to do ddr frequency scaling, and support for this controller will be implemented in the arm-trusted-firmware. This new clock-type should over time handle all these methods for handling DDR rate changes, but right now it will concentrate on the SIP interface used to talk to ARM trusted firmware. The SIP interface counterpart was merged from pull-request #684 [0] into the upstream arm-trusted-firmware codebase. [0] https://github.com/ARM-software/arm-trusted-firmware/pull/684 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-01Merge branch 'v4.9-shared/sip-hdr' into v4.9-clk/nextHeiko Stuebner1-0/+27
2016-08-31soc: rockchip: add header for ddr rate SIP interfaceLin Huang1-0/+27
Add a header for the SIP interface defined to access the dcf controller handling ddr rate changes on rk3399 (and most likely later socs). This interface is shared between the clock driver as well as the devfreq driver. The SIP interface counterpart was merged from pull-request #684 [0] into the upstream arm-trusted-firmware codebase. [0] https://github.com/ARM-software/arm-trusted-firmware/pull/684 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-31clk: rockchip: add SCLK_DDRC id for rk3399 ddrcLin Huang1-0/+1
Add the needed id for the ddr clock. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-31clk: imx7d: Add PLL_AUDIO_TEST_DIV/POST_DIV clocksFabio Estevam1-40/+61
Currently we see the following error when using the SAI audio driver on mx7: Division by zero in kernel. CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0-rc3-next-20160823 Hardware name: Freescale i.MX7 Dual (Device Tree) Backtrace: [<c010b70c>] (dump_backtrace) from [<c010b8a8>] (show_stack+0x18) r6:60000013 r5:ffffffff r4:00000000 r3:00000000 [<c010b890>] (show_stack) from [<c03e9324>] (dump_stack+0xb0/0xe) [<c03e9274>] (dump_stack) from [<c010b578>] (__div0+0x18/0x20) r8:00000000 r7:ffffffff r6:ffffffff r5:00000000 r4:00000000 r3:0 [<c010b560>] (__div0) from [<c03e795c>] (Ldiv0_64+0x8/0x18) [<c06cd860>] (divider_get_val) from [<c06cda28>] (clk_divider_se) This error happens due to the lack of definition of the IMX7D_PLL_AUDIO_TEST_DIV/IMX7D_PLL_AUDIO_POST_DIV clocks. Add support for them. Tested on a imx7s-warp board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-31clk: core: Force setting the phase delay when no changeJean-Francois Moine1-5/+0
This patch reverts commit 023bd7166be0 ("clk: skip unnecessary set_phase if nothing to do"), fixing two problems: * in some SoCs, the hardware phase delay depends on the rate ratio of the clock and its parent. So, changing this ratio may imply to set new hardware values, even if the logical delay is the same. * when the delay was the same as previously, an error was returned. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Fixes: 023bd7166be0 ("clk: skip unnecessary set_phase if nothing to do") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-30Merge tag 'clk-renesas-for-v4.9-tag2' of ↵Stephen Boyd1-0/+18
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull renesas r8a7796 SDHI clock support from Geert Uytterhoeven: Add all clocks needed to use the SDHI interfaces on the Renesas R-Car M3-W (r8a7796) SoC. * tag 'clk-renesas-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add SDIF clocks clk: renesas: r8a7796: Add GPIO clocks
2016-08-30Merge branch 'clk-fixes' into clk-nextStephen Boyd1-5/+6
* clk-fixes: clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399 clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399 clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399 clk: rockchip: fix rk3399 aclk_vio gate bit
2016-08-30Merge tag 'v4.8-rockchip-clk-fixes1' of ↵Stephen Boyd1-5/+6
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Some fixes for rk3399 register errors that revealed themself during actual use. * tag 'v4.8-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399 clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399 clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399 clk: rockchip: fix rk3399 aclk_vio gate bit
2016-08-29clk: versatile/icst: support for AP baseboard clocksLinus Walleij1-0/+136
This adds support for the two ICST525-based clocks on the Integrator/AP baseboard, as documented in the board manual "Integrator/AP ASIC Development Motherboard", ARM DUI0098 B, pages 3-15 thru 3-18. Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [sboyd@codeaurora.org: fixed uninitialized val warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-26clk: Simplify __of_clk_get_hw_from_provider()Stephen Boyd1-11/+6
__of_clk_get_hw_from_provider() is confusing because it will return EPROBE_DEFER if there isn't a ->get() or ->get_hw() function pointer in a provider. That's just a bug though, and we used to NULL pointer exception when ->get() was missing anyway, so let's make this more obvious that they're not optional. The assumption is that most providers will implement ->get_hw() so we only fallback to the ->get() function if necessary. This clarifies the intent and removes any possibility of probe defer happening if clk providers are buggy. Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-26clk: return unsigned int in dummy non-OF of_clk_get_parent_count()Rafał Miłecki1-1/+1
In the commit 929e7f3bc7b82 ("clk: Make of_clk_get_parent_count() return unsigned ints") of_clk_get_parent_count has been modified to return unsigned int. There is also a dummy implementation of the same function for configs without CONFIG_OF. For the consistency it should be updated as well. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: versatile/icst: add Integrator core module clocksLinus Walleij1-14/+160
The Integrator/AP and Integrator/CP have special derivatives of the ICST525 control registers, where some bits have been hardwired but others are possible to adjust, resulting in a control register that makes it possible to set an even, desired megahertz value. The Integrator/AP and Integrator/CP have slightly different layout so we support them using different compatible strings. After adding these clocks, the Integrator-specific cpufreq driver can be switched over to use the generic operating point device tree cpufreq driver. Instead of simply writing a value to the oscillator control register we switch to the more elaborate method of providing a bitmask and use regmap_update_bits() to poke the right bits for the desired frequency, this is needed since these control registers sometimes control more than one clock. Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: versatile add DT bindings for the ICST CM variantsLinus Walleij1-2/+32
The Integrator/AP and Integrator/CP core modules have special versions of the ICST525 interface hardcoding some bits. Create special compatible strings to identify these variants, also explain a bit what is going on. Cc: devicetree@vger.kernel.org Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: gcc-msm8996: add missing pcie phy reset linesSrinivas Kandagatla2-0/+5
This patch adds missing 2 PCIE common reset lines. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: gcc-msm8996: Fix pcie 2 pipe register offsetSrinivas Kandagatla1-2/+2
This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: qcom: select GDSC for msm8996 gcc and mmccSrinivas Kandagatla1-0/+2
This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock controllers, as these provide some of the gdscs on the SOC. Also selecting this config will make it align with other drivers which do the same. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 52111672f791 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC") Fixes: 7e824d507909 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25Merge branch 'clk-fixes' into clk-nextStephen Boyd1-2/+2
* clk-fixes: clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2
2016-08-25clk: h8300: Migrate to clk_hw based registration APIsStephen Boyd2-11/+11
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: qcom: Migrate to clk_hw based registration and OF APIsStephen Boyd6-45/+47
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: wm831x: Migrate to clk_hw based registration APIsStephen Boyd1-12/+9
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: vt8500: Migrate to clk_hw based registration APIsStephen Boyd1-10/+12
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: twl6040: Migrate to clk_hw based registration APIsStephen Boyd1-6/+7
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: si570: Migrate to clk_hw based OF and registration APIsStephen Boyd1-7/+6
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Guenter Roeck <linux@roeck-us.net> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: si5351: Migrate to clk_hw based OF and registration APIsStephen Boyd1-30/+41
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: si514: Migrate to clk_hw based OF and registration APIsStephen Boyd1-6/+5
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: scpi: Migrate to clk_hw based OF and registration APIsStephen Boyd1-19/+14
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: rk808: Migrate to clk_hw based OF and registration APIsStephen Boyd1-22/+22
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: pwm: Migrate to clk_hw based OF and registration APIsStephen Boyd1-5/+4
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Janusz Uzycki <j.uzycki@elproma.com.pl> Cc: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: palmas: Migrate to clk_hw based OF and registration APIsStephen Boyd1-8/+4
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-25clk: nspire: Migrate to clk_hw based OF and registration APIsStephen Boyd1-9/+10
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Daniel Tang <dt.tangr@gmail.com> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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