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AgeCommit message (Expand)AuthorFilesLines
2019-10-18drm/i915: treat stolen as a regionMatthew Auld4-23/+61
2019-10-18drm/i915: treat shmem as a regionMatthew Auld11-47/+149
2019-10-18drm/i915: enumerate and init each supported regionAbdiel Janulgue5-7/+68
2019-10-18drm/i915/execlists: Don't merely skip submission if maybe timeslicingChris Wilson4-29/+196
2019-10-18drm/i915/pmu: Fix uninitialized variable on error pathTvrtko Ursulin1-4/+2
2019-10-18drm/i915: Pass in intel_gt at some for_each_engine sitesTvrtko Ursulin15-67/+67
2019-10-18drm/i915: Make for_each_engine_masked work on intel_gtTvrtko Ursulin11-32/+37
2019-10-17drm/i915: Don't disable interrupts independently of the lockSebastian Andrzej Siewior1-8/+4
2019-10-17drm/i915/selftests: Teach requests to use all available enginesChris Wilson1-112/+175
2019-10-17drm/i915/huc: improve documentationDaniele Ceraolo Spurio3-21/+45
2019-10-17drm/i915/guc: improve documentationDaniele Ceraolo Spurio4-13/+49
2019-10-17drm/i915: Add microcontrollers documentation sectionDaniele Ceraolo Spurio1-0/+18
2019-10-17drm/i915: Fix MST oops due to MSA changesVille Syrjälä1-1/+3
2019-10-17drm/i915/pmu: Support multiple GPUsTvrtko Ursulin2-2/+31
2019-10-17drm/i915/tgl: Enable DDI/Port GKhaled Almahallawy5-0/+16
2019-10-16drm/i915: Move swizzle_bit under i915_ggttChris Wilson6-24/+25
2019-10-16drm/i915: Store i915_ggtt as the backpointer on fence registersChris Wilson7-41/+54
2019-10-16drm/i915: Do initial mocs configuration directlyChris Wilson3-220/+66
2019-10-16drm/i915/selftests: Teach timelines to take intel_gt as its argumentChris Wilson1-23/+25
2019-10-16drm/i915/selftests: Teach workarounds to take intel_gt as its argumentChris Wilson1-63/+65
2019-10-16drm/i915/selftests: Teach guc to take intel_gt as its argumentChris Wilson1-28/+14
2019-10-16drm/i915/selftests: Teach execlists to take intel_gt as its argumentChris Wilson1-147/+143
2019-10-16drm/i915: Introduce Jasper Lake PCHMatt Roper3-3/+32
2019-10-16drm/i915/ehl: Don't forget to set TC long detect functionMatt Roper1-0/+1
2019-10-16drm/i915: Prepare the mode readout for hw vs. uapi state splitVille Syrjälä1-1/+1
2019-10-16drm/i915: Prepare the connector/encoder mask readout for hw vs. uapi state splitVille Syrjälä1-5/+9
2019-10-16drm/i915: Switch intel_legacy_cursor_update() to intel_ typesVille Syrjälä1-42/+42
2019-10-16drm/i915: Refactor timestamping constants updateVille Syrjälä1-7/+11
2019-10-16drm/i915/execlist: Trim immediate timeslice expiryChris Wilson3-11/+39
2019-10-16drm/i915/selftests: Drop stale struct_mutexChris Wilson1-8/+1
2019-10-15drm/i915/tgl: Wa_1607138340Mika Kuoppala1-0/+4
2019-10-15drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627Mika Kuoppala2-0/+9
2019-10-15drm/i915/tgl: Wa_1607138336Mika Kuoppala2-0/+7
2019-10-15drm/i915/tgl: Wa_1409600907Mika Kuoppala1-0/+4
2019-10-15drm/i915/tgl: Wa_1409170338Mika Kuoppala1-0/+6
2019-10-15drm/i915/tgl: Wa_1409420604Mika Kuoppala2-0/+8
2019-10-15drm/i915/tgl: Keep FF dop clock enabled for A0Mika Kuoppala2-1/+9
2019-10-15drm/i915/tgl: Add extra hdc flush workaroundMika Kuoppala1-0/+20
2019-10-15drm/i915/tgl: Add HDC Pipeline FlushMika Kuoppala2-1/+4
2019-10-15drm/i915/tgl: Include ro parts of l3 to invalidateMika Kuoppala2-0/+2
2019-10-15drm/i915/tgl: Add IS_TGL_REVIDMika Kuoppala1-0/+5
2019-10-15drm/i915/icl: Wa_1607087056Mika Kuoppala2-0/+7
2019-10-15drm/i915: Flush tasklet submission before sleeping on i915_request_waitChris Wilson1-0/+1
2019-10-15drm/i915: Use drm_rect_init()Ville Syrjälä2-12/+4
2019-10-15drm/i915: Use drm_rect_translate_to()Ville Syrjälä1-6/+4
2019-10-15drm/i915: Make .modeset_calc_cdclk() mandatoryVille Syrjälä2-11/+28
2019-10-15drm/i915: Stop using drm_atomic_helper_check_planes()Ville Syrjälä3-19/+50
2019-10-15drm/i915: Switch to using DP_MSA_MISC_* definesVille Syrjälä2-21/+9
2019-10-15drm/i915/dp: Attach HDR metadata property to DP connectorGwan-gyeong Mun1-0/+5
2019-10-15drm/i915/dp: Program an Infoframe SDP Header and DB for HDR Static MetadataGwan-gyeong Mun3-0/+96
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