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2016-01-24MAINTAINERS: Add KVM for MIPS entryJames Hogan1-0/+8
I've pretty much been maintaining KVM for MIPS for a while now. Lets make it more official (and make sure I get Cc'd on relevant patches). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11898/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: KVM: Add missing newline to kvm_err()James Hogan1-1/+1
Add missing newline to end of kvm_err string when guest PMAP couldn't be allocated. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11896/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Move KVM specific opcodes into asm/inst.hJames Hogan4-28/+5
The header arch/mips/kvm/opcode.h defines a few extra opcodes which aren't in arch/mips/include/uapi/asm/inst.h. There's nothing KVM specific about them, so lets move them into inst.h where they belong and delete the header. Note that mfmcz_op is renamed to mfmc0_op to match the instruction set manual, and wait_op was already added to inst.h in commit b0a3eae2b943 ("MIPS: inst.h: define COP0 wait op"), merged in v3.16-rc1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11895/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: KVM: Use cacheops.h definitionsJames Hogan1-22/+8
Drop the custom cache operation code definitions used by KVM for emulating guest CACHE instructions, and switch to use the existing definitions in <asm/cacheops.h>. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11893/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Break down cacheops.h definitionsJames Hogan1-42/+64
Most of the cache op codes defined in cacheops.h are split into a 2-bit cache identifier, and a 3-bit cache op code which does largely the same thing semantically regardless of the cache identifier. To allow the use of these definitions by KVM for decoding cache ops, break the definitions down into parts where it makes sense to do so, and add masks for the Cache and Op field within the cache op. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Use EXCCODE_ constants with set_except_vector()James Hogan2-30/+30
The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Update trap codesJames Hogan1-2/+10
Add a few missing trap codes. [ralf@linux-mips.org: Drop removal of exception codes. I don't care what the incomplete architecture spec says; it can't change existing hardware and VCEI is supported indeed.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11890/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Move Cause.ExcCode trap codes to mipsregs.hJames Hogan5-83/+80
Move the Cause.ExcCode trap code definitions from kvm_host.h to mipsregs.h, since they describe architectural bits rather than KVM specific constants, and change the prefix from T_ to EXCCODE_. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11891/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: KVM: Make kvm_mips_{init,exit}() staticJames Hogan1-2/+2
The module init and exit functions have no need to be global, so make them static. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11889/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: KVM: Refactor added offsetof()sJames Hogan1-7/+3
When calculating the offsets into the commpage for dynamically translated mtc0/mfc0 guest instructions, multiple offsetof()s are added together to find the offset of the specific register in the mips_coproc, within the commpage. Simplify each of these cases to a single offsetof() to find the offset of the specific register within the commpage. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11888/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: KVM: Convert EXPORT_SYMBOL to _GPLJames Hogan2-19/+19
Export symbols only to GPL modules to match other KVM symbols in virt/kvm/ and arch/*/kvm/. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11887/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: KVM: Drop unused kvm_mips_host_tlb_inv_index()James Hogan2-38/+0
The function kvm_mips_host_tlb_inv_index() is unused, so drop it completely. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Gleb Natapov <gleb@kernel.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11886/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Move definition of DC bit to mipsregs.hJames Hogan2-3/+2
The CAUSEB_DC and CAUSEF_DC definitions used by KVM are defined in asm/kvm_host.h, but all the other Cause register field definitions are found in asm/mipsregs.h. Lets reunite the DC bit definitions with its friends in mipsregs.h. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11885/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: KVM: Drop some unused definitions from kvm_host.hJames Hogan1-5/+0
Some definitions in the MIPS asm/kvm_host.h are completely unused, so lets drop them. MS_TO_NS is no longer used since commit e30492bbe95a ("MIPS: KVM: Rewrite count/compare timer emulation"). The others don't appear ever to have been used. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11884/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: KVM: Trivial whitespace and style fixesJames Hogan5-15/+14
A bunch of misc whitespace and style fixes within arch/mips/kvm/. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11883/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: pic32mzda: Add initial PIC32MZDA Starter Kit defconfigJoshua Henderson1-0/+89
This adds an initial default config that enables all available PIC32 drivers and is enough for booting a PIC32MZDA Starter Kit. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12105/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: dts: Add initial DTS for the PIC32MZDA Starter KitJoshua Henderson6-0/+697
This adds basic DTS configuration for the PIC32MZDA chip and in turn the PIC32MZDA Starter Kit. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12104/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Add support for PIC32MZDA platformJoshua Henderson22-0/+1476
This adds support for the Microchip PIC32 MIPS microcontroller with the specific variant PIC32MZDA. PIC32MZDA is based on the MIPS m14KEc core and boots using device tree. This includes an early pin setup and early clock setup needed prior to device tree being initialized. In additon, an interface is provided to synchronize access to registers shared across several peripherals. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12097/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24dt/bindings: Add bindings for PIC32/MZDA platformsJoshua Henderson1-0/+31
This adds support for the Microchip PIC32 platform along with the specific variant PIC32MZDA on a PIC32MZDA Starter Kit. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12096/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24IRQCHIP: irq-pic32-evic: Add support for PIC32 interrupt controllerCristian Birsan3-0/+330
This adds support for the interrupt controller present on PIC32 class devices. It handles all internal and external interrupts. This controller exists outside of the CPU core and is the arbitrator of all interrupts (including interrupts from the CPU itself) before they are presented to the CPU. The following features are supported: - DT properties for EVIC and for devices/peripherals that use interrupt lines - Persistent and non-persistent interrupt handling - irqdomain and generic chip support - Configuration of external interrupt edge polarity Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12092/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24dt/bindings: Add bindings for PIC32 interrupt controllerCristian Birsan1-0/+67
Document the devicetree bindings for the interrupt controller on Microchip PIC32 class devices. Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12093/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: bmips: Improve BCM6368 device treeÁlvaro Fernández Rojas1-0/+22
Add brcm,bcm6358-leds node to bcm6368.dtsi Add reboot support (syscon-reboot as defined in BCM6328) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: f.fainelli@gmail.com Cc: jogo@openwrt.org Cc: cernekee@gmail.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Álvaro Fernández Rojas <noltari@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/12117/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: bmips: Improve BCM6328 device treeÁlvaro Fernández Rojas1-0/+9
Adds bcm6328-leds node to bcm6328.dtsi Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: jogo@openwrt.org Cc: cernekee@gmail.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: Álvaro Fernández Rojas <noltari@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/12116/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: ptrace: Drop cp0_tcstatus from regoffset_table[]James Hogan1-3/+0
The cp0_tcstatus member of struct pt_regs was removed along with the rest of SMTC in v3.16, commit b633648c5ad3 ("MIPS: MT: Remove SMTC support"), however recent uprobes support in v4.3 added back a reference to it in the regoffset_table[] in ptrace.c. Remove it. Signed-off-by: James Hogan <james.hogan@imgtec.com> Fixes: 40e084a506eb ("MIPS: Add uprobes support.") Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11920/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: TXx9: iocled: Be sure to clamp return valueLinus Walleij1-1/+1
As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11925/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: RB532: Be sure to clamp return valueLinus Walleij1-1/+1
As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11924/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: TXx9: Be sure to clamp return valueLinus Walleij1-1/+1
As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11923/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: ar7: Be sure to clamp return valueLinus Walleij1-1/+1
As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Cc: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11922/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Alchemy: Be sure to clamp return valueLinus Walleij1-3/+3
As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: linux-mips@linux-mips.org Cc: linux-gpio@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11921/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Fix macro typoJaedon Shin1-1/+1
Change the CONFIG_MIPS_CMDLINE_EXTEND to CONFIG_MIPS_CMDLINE_DTB_EXTEND to resolve the EXTEND_WITH_PROM macro. Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Fixes: 2024972ef533 ("MIPS: Make the kernel arguments from dtb available") Reviewed-by: Alexander Sverdlin <alexander.svedlin@gmail.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11909/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: smp-cps: Ensure secondary cores start with EVA disabledMatt Redfearn2-0/+7
The kernel currently assumes that a core will start up in legacy mode using the exception base provided through the CM GCR registers. If a core has been configured in hardware to start in EVA mode, these assumptions will fail. This patch ensures that secondary cores are initialized to meet these assumptions. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11907/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: io.h: Define `ioremap_cache'Maciej W. Rozycki1-0/+1
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12040/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: math-emu: dsemul: Reduce `get_isa16_mode' clutterMaciej W. Rozycki1-8/+9
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12178/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: inst.h: Fix some instruction descriptionsMaciej W. Rozycki1-2/+2
Fix the description of the microMIPS NOP16 encoding or MM_NOP16, which is not equivalent to the MIPS16 NOP instruction. This is 0x0c00 and represents the microMIPS `MOVE16 $0, $0' operation, whereas MIPS16 NOP is encoded as 0x6500, representing `MOVE $0, $16'. Also fix a typo in `mm_fp0_format' description. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12177/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: math-emu: dsemul: Correct description of the emulation frameMaciej W. Rozycki1-7/+2
Remove irrelevant content from the description of the emulation frame in `mips_dsemul', referring to bare-metal configurations. Update the text, reflecting the change made with commit ba3049ed4086 ("MIPS: Switch FPU emulator trap to BREAK instruction."), where we switched from using an address error exception on an unaligned access to the use of a BREAK 514 instruction causing a breakpoint exception instead. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12176/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: math-emu: Correct the emulation of microMIPS ADDIUPC instructionMaciej W. Rozycki2-2/+30
Emulate the microMIPS ADDIUPC instruction directly in `mips_dsemul'. If executed in the emulation frame, this instruction produces an incorrect result, because the value of the PC there is not the same as where the instruction originated. Reshape code so as to handle all microMIPS cases together. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12175/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: math-emu: Make microMIPS branch delay slot emulation workMaciej W. Rozycki3-6/+9
Complement commit 102cedc32a6e ("MIPS: microMIPS: Floating point support.") which introduced microMIPS FPU emulation, but did not adjust the encoding of the BREAK instruction used to terminate the branch delay slot emulation frame. Consequently the execution of any such frame is indeterminate and, depending on CPU configuration, will result in random code execution or an offending program being terminated with SIGILL. This is because the regular MIPS BREAK instruction is encoded with the 0 major and the 0xd minor opcode, however in the microMIPS instruction set this major/minor opcode pair denotes an encoding reserved for the DSP ASE. Instead the microMIPS BREAK instruction is encoded with the 0 major and the 0x7 minor opcode. Use the correct BREAK encoding for microMIPS FPU emulation then. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12174/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: math-emu: dsemul: Fix ill formatting of microMIPS partMaciej W. Rozycki1-6/+12
Correct formatting breakage introduced with commit 102cedc32a6e ("MIPS: microMIPS: Floating point support."), so that further changes to this code can be consistent. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12173/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: math-emu: Correctly handle NOP emulationMaciej W. Rozycki2-6/+12
Fix an issue introduced with commit 9ab4471c9f1b ("MIPS: math-emu: Correct delay-slot exception propagation") where the emulation of a NOP instruction signals the need to terminate the emulation loop. This in turn, if the PC has not changed from the entry to the loop, will cause the kernel to terminate the program with SIGILL. Consider this program: static double div(double d) { do d /= 2.0; while (d > .5); return d; } int main(int argc, char **argv) { return div(argc); } which gets compiled to the following binary code: 00400490 <main>: 400490: 44840000 mtc1 a0,$f0 400494: 3c020040 lui v0,0x40 400498: d44207f8 ldc1 $f2,2040(v0) 40049c: 46800021 cvt.d.w $f0,$f0 4004a0: 46220002 mul.d $f0,$f0,$f2 4004a4: 4620103c c.lt.d $f2,$f0 4004a8: 4501fffd bc1t 4004a0 <main+0x10> 4004ac: 00000000 nop 4004b0: 4620000d trunc.w.d $f0,$f0 4004b4: 03e00008 jr ra 4004b8: 44020000 mfc1 v0,$f0 4004bc: 00000000 nop Where the FPU emulator is used, depending on the number of command-line arguments this code will either run to completion or terminate with SIGILL. If no arguments are specified, then BC1T will not be taken, NOP will not be emulated and code will complete successfully. If one argument is specified, then BC1T will be taken once and NOP will be emulated. At this point the entry PC value will be 0x400498 and the new PC value, set by `mips_dsemul' will be 0x4004a0, the target of BC1T. The emulation loop will terminate, but SIGILL will not be issued, because the PC has changed. The FPU emulator will be entered again and on the second execution BC1T will not be taken, NOP will not be emulated and code will complete successfully. If two or more arguments are specified, then the first execution of BC1T will proceed as above. Upon reentering the FPU emulator the emulation loop will continue to BC1T, at which point the branch will be taken and NOP emulated again. At this point however the entry PC value will be 0x4004a0, the same as the target of BC1T. This will make the emulator conclude that execution has not advanced and therefore an unsupported FPU instruction has been encountered, and SIGILL will be sent to the process. Fix the problem by extending the internal API of `mips_dsemul', making it return -1 if no delay slot emulation frame has been made, the instruction has been handled and execution of the emulation loop needs to continue as if nothing happened. Remove code from `mips_dsemul' to reproduce steps made by the emulation loop at the conclusion of each iteration, as those will be reached normally now. Adjust call sites accordingly. Document the API. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12172/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: Fix some missing CONFIG_CPU_MIPSR6 #ifdefsHuacai Chen2-3/+3
Commit be0c37c985eddc4 (MIPS: Rearrange PTE bits into fixed positions.) defines fixed PTE bits for MIPS R2. Then, commit d7b631419b3d230a4d383 (MIPS: pgtable-bits: Fix XPA damage to R6 definitions.) adds the MIPS R6 definitions in the same way as MIPS R2. But some R6 #ifdefs in the later commit are missing, so in this patch I fix that. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24MIPS: sync-r4k: reduce skew while synchronizationHuacai Chen1-24/+8
While synchronization, count register will go backwards for the master. If synchronise_count_master() runs before synchronise_count_slave(), skew becomes even more. The skew is very harmful for CPU hotplug (CPU0 do synchronization with CPU1, then CPU0 do synchronization with CPU2 and CPU0's count goes backwards, so it will be out of sync with CPU1). After the commit cf9bfe55f24973a8f40e2 (MIPS: Synchronize MIPS count one CPU at a time), we needn't evaluate count_reference at the beginning of synchronise_count_master() any more. Thus, we evaluate the initcount (It seems like count_reference is redundant) in the 2nd loop. Since we write the count register in the last loop, we don't need additional barriers (the existing memory barriers are enough). Moreover, I think we loop 3 times is enough to get a primed instruction cache, this can also get less skew than looping 5 times. Comments are also updated in this patch. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/12163/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-24Merge tag 'ntb-4.5' of git://github.com/jonmason/ntbLinus Torvalds13-12/+2183
Pull NTB updates from Jon Mason: "A new driver to support AMD NTB, a NTB performance test driver, NTB bugs fixes, and the ability to recover from running out of DMA descriptors" * tag 'ntb-4.5' of git://github.com/jonmason/ntb: NTB: Fix macro parameter conflict with field name NTB: Add support for AMD PCI-Express Non-Transparent Bridge ntb: ntb perf tool NTB: Address out of DMA descriptor issue with NTB NTB: Clear property bits in BAR value NTB: ntb_process_tx error path bug
2016-01-24mtd: atmel_nand: Use of_device_get_match_dataRomain Izard1-3/+1
Remove the need for forward declaration and the risk for a null pointer when accessing the private part of the compatible match table, by using the newly introduced of_device_get_match_data function. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-24mtd: atmel_nand: Simplify error messagesRomain Izard1-2/+2
The error messages when the ECC controller is misconfigured through the device tree are very precise. As a result they can (and will) get obsolete when new revisions of the controller appear. Simplify them before adding the support for the new revision. Signed-off-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-24mtd: nand: gpmi: may use minimum required ecc for 744 oobsize NANDHan Xu1-12/+14
By default NAND driver will choose the highest ecc strength that oob could contain, in this case, for some 8K+744 NAND flash, the ecc strength will be up to 52bit, which beyonds the i.MX6QDL BCH capability (40bit). This patch allows the NAND driver try to use minimum required ecc strength if it failed to use the highest ecc, even without explicitly claiming "fsl,use-minimum-ecc" in dts. Signed-off-by: Han Xu <b45815@freescale.com> Acked-by: Huang Shijie <shijie.huang@arm.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-24mtd: nand: gpmi: add gpmi dsm supend/resume supportHuang Shijie1-1/+46
i.MX6SX supports deep sleep mode(DSM) that may turn off GPMI/BCH power during suspend, add gpmi nand suspend/resume function to release DMA channel in suspend function and re-init GPMI/BCH controller during resume function. Although it is not necessary to restore GPMI/BCH registers value for i.MX6QDL, the code doesn't distinguish different platforms to keep the code simple. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Han Xu <han.xu@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-24mtd: bcm47xxpart: don't fail because of bit-flipsRafał Miłecki1-16/+22
Bit-flip errors may occur on NAND flashes and are harmless. Handle them gracefully as read content is still reliable and can be parsed. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-24mtd: bcm47xxpart: limit scanned flash area on BCM47XX (MIPS) onlyRafał Miłecki1-2/+2
We allowed using bcm47xxpart on BCM5301X arch with commit: 9e3afa5f5c7 ("mtd: bcm47xxpart: allow enabling on ARCH_BCM_5301X") BCM5301X devices may contain some partitions in higher memory, e.g. Netgear R8000 has board_data at 0x2600000. To detect them we should use size limit on MIPS only. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-24mtd: onenand: unexport onenand_default_bbt()Thomas Petazzoni1-2/+0
The onenand_default_bbt() function is only used by the OneNAND core and not by drivers, so there is no real need to export it. Additionally, the corresponding nand_default_bbt() for regular NANDs is not exported either, so for consistency reasons, this commit removes the EXPORT_SYMBOL on onenand_default_bbt(). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2016-01-24mtd: onenand: make onenand_scan_bbt() staticThomas Petazzoni2-3/+1
Like was done in commit 17799359e7b3fa6ef4f2bf926cd6821cf7903ecf ("mtd: nand_bbt: make nand_scan_bbt() static") for the NAND code, this commit makes the onenand_scan_bbt() function static in the OneNAND code, since it is only used in onenand_bbt.c itself. Consequently, the EXPORT_SYMBOL() and declaration in bbm.h are also removed. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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