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2016-04-19drm/i915: Wait for power cycle delay after turning off DSI panel powerVille Syrjälä1-1/+6
2016-04-19drm/i915: Define HSW/BDW display power domains the right way upVille Syrjälä1-19/+26
2016-04-19drm/i915: Define VLV/CHV display power well domains properlyVille Syrjälä1-2/+40
2016-04-19drm/i915: Set .domains=POWER_DOMAIN_MASK for the always-on wellVille Syrjälä1-16/+6
2016-04-19drm/i915: Fix oops in vlv_force_pll_on()Ville Syrjälä1-2/+2
2016-04-19drm/i915/gen9: Fix runtime PM refcounting in case DMC firmware isn't loadedImre Deak4-4/+50
2016-04-19drm/i915/ddi: Fix eDP VDD handling during booting and suspend/resumeImre Deak3-9/+7
2016-04-19drm/i915: Fix system resume if PCI device remained enabledImre Deak1-1/+31
2016-04-19drm/i915: Fix error path in i915_drm_resume_earlyImre Deak1-2/+2
2016-04-18drm/i915/kbl: Reset secondary power well requests left on by DMC/KVMRImre Deak1-1/+1
2016-04-18drm/i915: Replace nondescript 'WARN_ON(!lret)' with a sensible error messageVille Syrjälä1-1/+1
2016-04-18drm/i915: Avoid stalling on pending flips for legacy cursor updatesChris Wilson1-0/+3
2016-04-18drm/i915/dsi: fix CHV dsi encoder hardware state readout on port CJani Nikula1-4/+5
2016-04-15drm/i915: Show pin mapped counts and sizes in debugfsTvrtko Ursulin1-0/+22
2016-04-15drm/i915: Show pin mapped status in describe_objTvrtko Ursulin1-13/+21
2016-04-15drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platformsVille Syrjälä2-0/+10
2016-04-15drm/i915: Hook up pfit for DSIVille Syrjälä1-5/+68
2016-04-15drm/i915: Eliminate {vlv,bxt}_configure_dsi_pll()Ville Syrjälä1-22/+6
2016-04-15drm/i915: Compute DSI PLL parameters during .compute_config()Ville Syrjälä5-81/+112
2016-04-15drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHVVille Syrjälä2-68/+80
2016-04-15drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variationsDongwon Kim1-10/+2
2016-04-15drm/i915/bxt: Enable runtime PMImre Deak1-1/+1
2016-04-15Revert "drm/i915/bxt: Disable power well support"Imre Deak1-5/+0
2016-04-15drm/i915/bxt: Add HW state verification for DDI PHY and CDCLKImre Deak5-2/+138
2016-04-15drm/i915/bxt: Don't reprogram an already enabled DDI PHYImre Deak1-0/+40
2016-04-15drm/i915/bxt: Sanitize the DBUF HW state together with CDCLKImre Deak1-2/+26
2016-04-15drm/i915/bxt: Don't toggle power well 1 on-demandImre Deak5-48/+66
2016-04-15drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninitImre Deak1-3/+4
2016-04-15drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpersImre Deak5-31/+21
2016-04-15drm/i915/skl: Unexport skl_pw1_misc_io_initImre Deak2-33/+18
2016-04-15drm/i915/bxt: Suspend power domains during suspend-to-idleImre Deak1-2/+4
2016-04-15drm/i915/gen9: Fix DMC/DC state assertsImre Deak1-21/+11
2016-04-15drm/i915/gen9: Make power well disabling synchronousImre Deak1-4/+5
2016-04-15drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMRImre Deak1-0/+41
2016-04-15drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-onlyImre Deak1-0/+3
2016-04-15drm/i915/bxt: Fix GRC code register field definitionsImre Deak1-7/+3
2016-04-15drm/i915/bxt: Reject DMC firmware versions with known bugsImre Deak1-5/+15
2016-04-15drm/i915: use drm_crtc_send_vblank_event()Gustavo Padovan1-4/+2
2016-04-14drm/i915: Use fw_domains_put_with_fifo() on HSWVille Syrjälä1-1/+5
2016-04-14drm/i915: Split gen8_gt_irq_handler into ack+handleVille Syrjälä1-32/+47
2016-04-14drm/i915: Eliminate passing dev+dev_priv to {snb,ilk}_gt_irq_handler()Ville Syrjälä1-15/+12
2016-04-14drm/i915: Move gt/pm irq handling out from irq disabled section on VLVVille Syrjälä1-5/+5
2016-04-14drm/i915: Split VLV/CVH PIPESTAT handling into ack+handlerVille Syrjälä1-4/+17
2016-04-14drm/i915: Split PORT_HOTPLUG_STAT ack out from i9xx_hpd_irq_handler()Ville Syrjälä1-17/+30
2016-04-14drm/i915: Move variables to narrower scope in VLV/CHV irq handlersVille Syrjälä1-2/+2
2016-04-14drm/i915: Eliminate loop from VLV irq handlerVille Syrjälä1-4/+3
2016-04-14drm/i915: Clear VLV_IER around irq processingVille Syrjälä1-1/+35
2016-04-14drm/i915: Clear VLV_MASTER_IER around irq processingVille Syrjälä1-6/+10
2016-04-14drm/i915: Clear VLV_IIR after PIPESTATVille Syrjälä1-15/+21
2016-04-14drm/i915: Set up VLV_MASTER_IER consistentlyVille Syrjälä1-0/+5
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