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2020-07-09soc: aspeed-lpc-ctrl: Fix printf warningJoel Stanley1-4/+4
>> drivers/soc/aspeed/aspeed-lpc-ctrl.c:247:17: warning: format '%zu' expects argument of type 'size_t', but argument 3 has type 'resource_size_t' {aka 'unsigned int'} [-Wformat=] Documentation/core-api/printk-formats.rst suggests %pa should work for resouce_size_t, but it did not: %pa[p] 0x01234567 or 0x0123456789abcdef For printing a phys_addr_t type (and its derivatives, such as resource_size_t) which can vary based on build options, regardless of the width of the CPU data path. Instead cast to an integer which works as all aspeed processors are 32-bit. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-09hwmon (peci-dmmtemp): Fix 'sizeof' warningJoel Stanley1-1/+1
The 0day bot reported: >> drivers/hwmon/peci-dimmtemp.c:361:18: error: invalid application of 'sizeof' to an incomplete type 'const u8 []' for (i = 0; i < ARRAY_SIZE(support_model); i++) { ^~~~~~~~~~~~~~~~~~~~~~~~~ OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08Merge tag 'v5.7.7' into dev-5.7Joel Stanley1331-6555/+13146
Linux 5.7.7 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: configs: aspeed: Update defconfigsJoel Stanley2-21/+52
OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: tacoma: Enable XDMA engineEddie James1-0/+11
Add a reserved memory node for the VGA memory. Add the XDMA engine node, enable it, and point it's memory region to the VGA memory. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: witherspoon: Enable XDMA engineEddie James1-0/+11
Add a reserved memory node for the VGA memory. Add the XDMA engine node, enable it, and point it's memory region to the VGA memory. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: ast2500: Update XDMA engine nodeEddie James1-2/+3
Correct the pcie-device property, and add the Aspeed SCU interrupt controller include. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: ast2600: Update XDMA engine nodeEddie James1-12/+3
Add the PCI-E root complex reset, correct the pcie-device property, and add the Aspeed SCU interrupt controller include. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08soc: aspeed: xdma: Add reset ioctlEddie James2-0/+36
Users of the XDMA engine need a way to reset it if something goes wrong. Problems on the host side, or user error, such as incorrect host address, may result in the DMA operation never completing and no way to determine what went wrong. Therefore, add an ioctl to reset the engine so that users can recover in this situation. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08soc: aspeed: xdma: Add user interfaceEddie James1-0/+218
This commits adds a miscdevice to provide a user interface to the XDMA engine. The interface provides the write operation to start DMA operations. The DMA parameters are passed as the data to the write call. The actual data to transfer is NOT passed through write. Note that both directions of DMA operation are accomplished through the write command; BMC to host and host to BMC. The XDMA driver reserves an area of physical memory for DMA operations, as the XDMA engine is restricted to accessing certain physical memory areas on some platforms. This memory forms a pool from which users can allocate pages for their usage with calls to mmap. The space allocated by a client will be the space used in the DMA operation. For an "upstream" (BMC to host) operation, the data in the client's area will be transferred to the host. For a "downstream" (host to BMC) operation, the host data will be placed in the client's memory area. Poll is also provided in order to determine when the DMA operation is complete for non-blocking IO. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08soc: aspeed: Add XDMA Engine DriverEddie James5-0/+1004
The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI DMA operations between the SOC (acting as a BMC) and a host processor in a server. This commit adds a driver to control the XDMA engine and adds functions to initialize the hardware and memory and start DMA operations. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08dt-bindings: soc: Add Aspeed XDMA EngineEddie James2-0/+109
Document the bindings for the Aspeed AST25XX and AST26XX XDMA engine. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: ast2600evb: Add MAC0Joel Stanley1-0/+20
MAC0 was not functional in the AST2600A0 SoC. This has been resolved with the A1, so allow use of this port on EVBs with the A1. A0 EVBs will still boot with this change, but the first ethernet device will not be functional. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: rainier: Add second cfam on the hubEddie James1-0/+36
The hub FSI master can access the cfams on two other processors. Reflect this by adding a second cfam to the first hub description. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Tested-by: Andrew Geissler <geissonator@yahoo.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08i2c: fsi: Prevent adding adapters for ports without dts nodesEddie James1-1/+6
Ports should be defined in the devicetree if they are to be enabled on the system. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08i2c: fsi: Fix the port number field in status registerEddie James1-1/+1
The port number field in the status register was not correct, so fix it. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: tacoma: Remove checkstop gpio-keyBen Tyner1-6/+0
The attention handler will monitor the checkstop gpio via the character device interface so it needs to not be defined. OpenBMC-Staging-Count: 2 Signed-off-by: Ben Tyner <ben.tyner@ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: rainier: Add line-name checkstopBen Tyner1-1/+1
Rainier uses GPIO B6 as the checkstop GPIO. Define the line-name so that this GPIO can be found by name. OpenBMC-Staging-Count: 2 Signed-off-by: Ben Tyner <ben.tyner@ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: rainier: Configure ball Y23 as GPIOP7 for MCLR_VPPAndrew Jeffery1-0/+7
GPIOP7 is used in the Rainier design to manage the state of a microcontroller elsewhere in the system but its ball, Y23, is the driver of the heartbeat LED on the ast2600-evb and the SoC defaults Y23 at power-on to the pulse-train behaviour used to drive the LED. This causes much confusion for the micro in the Rainier system, so hog the line as early as possible. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08pinctrl: aspeed: Describe the heartbeat function on ball Y23Andrew Jeffery1-1/+6
The default pinmux configuration for Y23 is to route a heartbeat to drive a LED. Previous revisions of the AST2600 datasheet did not include a description of this function OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08hwmon: (occ) Add new temperature sensor typeEddie James1-0/+65
The latest version of the On-Chip Controller (OCC) has a different format for the temperature sensor data. Add a new temperature sensor version to handle this data. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08fsi: occ: Add support for P10Eddie James1-34/+92
The P10 OCC has a different SRAM address for the command and response buffers. In addition, the SBE commands to access the SRAM have changed format. Add versioning to the driver to handle these differences. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08dt-bindings: fsi: Add P10 OCC device documentationEddie James1-6/+6
Add the P10 compatible string. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08fsi: aspeed: Add module param for bus divisorJoel Stanley1-2/+6
For testing and hardware debugging a user may wish to override the divisor at runtime. By setting fsi_master_aspeed.bus_div=N, the divisor will be set to N, if 0 < N <= 0x3ff. This is a module parameter and not a device tree option as it will only need to be set when testing or debugging. OpenBMC-Staging-Count: 2 Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08fsi: aspeed: Run the bus at maximum speedJoel Stanley1-3/+14
Testing of Tacoma has shown that the ASPEED master can be run at maximum speed. The exception is when wired externally with a cable, in which case we use a divisor of two to ensure reliable operation. OpenBMC-Staging-Count: 2 Reviewed-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08clk: ast2600: Fix AHB clock divider for A1Eddie James1-6/+25
The latest specs for the AST2600 A1 chip include some different bit definitions for calculating the AHB clock divider. Implement these in order to get the correct AHB clock value in Linux. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08fsi: aspeed: Enable 23-bit addressingEddie James1-2/+4
In order to access more than the second hub link, 23-bit addressing is required. The core provides the highest two bits of address as the slave ID to the master. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Acked-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: Add witherspoon-128 machineEddie James2-0/+60
Create a witherspoon machine with 128MB flash chips. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: rainier: Add KCS node for LPC MCTPEddie James1-0/+5
OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: tacoma: Add KCS node for LPC MCTPAndrew Geissler1-0/+5
OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Geissler <geisonator@yahoo.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: witherspoon: Add KCS node for LPC MCTPAndrew Jeffery1-0/+5
The compatible is terrible, but we need a way to describe how we want to drive the hardware, and it's not in a fashion that's integrated into IPMI. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08misc: Add ASPEED KCS driver for MCTP purposesAndrew Jeffery3-0/+451
IBM have developed a vendor-defined MCTP binding that utilises LPC IO and FW interfaces to exchange MCTP messages. A KCS device in the IO space is used to send single-byte control messages initialising the MCTP channel and exchanging ownership of data buffers. This driver exposes the KCS message stream to userspace, allowing an MCTP-capable application to manipulate the data exposed via the FW space. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08fsi: aspeed: Support cabled FSIJoel Stanley1-0/+46
Some FSI development systems have internal FSI signals, and some have external cabled FSI. Software can detect which machine this is by reading a jumper GPIO, and also control which pins the signals are routed to through a mux GPIO. This attempts to find the GPIOs at probe time. If they are not present in the device tree the driver will not error and continue as before. The mux GPIO is owned by the FSI driver to ensure it is not modified at runtime. The routing jumper obtained as non-exclusive to allow other software to inspect it's state. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600Joel Stanley1-0/+17
The ast2600 disables the mapping of AHB memory regions by default, only allowing the LPC window to point to SPI NOR. In order to point the window to any AHB address, an ast2600 specific bit must be toggled. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08hwmon: Add PECI dimmtemp driverJae Hyun Yoo3-0/+440
This commit adds PECI dimmtemp hwmon driver. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08hwmon: Add PECI cputemp driverJae Hyun Yoo4-0/+535
This commit adds PECI cputemp hwmon driver. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08Documentation: hwmon: Add documents for PECI hwmon driversJae Hyun Yoo3-0/+157
This commit adds hwmon documents for PECI cputemp and dimmtemp drivers. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08mfd: intel-peci-client: Add Intel PECI client driverJae Hyun Yoo4-0/+285
This commit adds Intel PECI client driver. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08dt-bindings: mfd: Add Intel PECI client bindings documentJae Hyun Yoo1-0/+67
This commit adds Intel PECI client bindings document. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08peci: npcm: add NPCM PECI driverTomer Maimon3-0/+421
Add support for the Nuvoton NPCM BMC hardware to the Platform Environment Control Interface (PECI) subsystem. OpenBMC-Staging-Count: 2 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08dt-bindings: peci: add NPCM PECI documentationTomer Maimon1-0/+102
Added device tree binding documentation for Nuvoton BMC NPCM Platform Environment Control Interface(PECI). OpenBMC-Staging-Count: 2 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08peci: Add Aspeed PECI adapter driverJae Hyun Yoo3-0/+499
This commit adds Aspeed PECI adapter driver for Aspeed AST24xx/25xx/26xx SoCs. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08ARM: dts: aspeed: Add PECI nodeJae Hyun Yoo3-0/+75
This commit adds PECI bus/adapter node into aspeed-g4, aspeed-g5 and aspeed-g6. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08dt-bindings: Add bindings document of Aspeed PECI adapterJae Hyun Yoo1-0/+124
This commit adds bindings document of Aspeed PECI adapter for ASPEED AST24xx/25xx/26xx SoCs. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08peci: Add support for PECI bus driver coreJae Hyun Yoo10-0/+3311
This commit adds driver implementation for PECI bus core into linux driver framework. PECI (Platform Environment Control Interface) is a one-wire bus interface that provides a communication channel from Intel processors and chipset components to external monitoring or control devices. PECI is designed to support the following sideband functions: * Processor and DRAM thermal management - Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS) thermal readings acquired via PECI against the processor-specific fan speed control reference point, or TCONTROL. Both TCONTROL and DTS thermal readings are accessible via the processor PECI client. These variables are referenced to a common temperature, the TCC activation point, and are both defined as negative offsets from that reference. - PECI based access to the processor package configuration space provides a means for Baseboard Management Controllers (BMC) or other platform management devices to actively manage the processor and memory power and thermal features. * Platform Manageability - Platform manageability functions including thermal, power, and error monitoring. Note that platform 'power' management includes monitoring and control for both the processor and DRAM subsystem to assist with data center power limiting. - PECI allows read access to certain error registers in the processor MSR space and status monitoring registers in the PCI configuration space within the processor and downstream devices. - PECI permits writes to certain registers in the processor PCI configuration space. * Processor Interface Tuning and Diagnostics - Processor interface tuning and diagnostics capabilities (Intel Interconnect BIST). The processors Intel Interconnect Built In Self Test (Intel IBIST) allows for infield diagnostic capabilities in the Intel UPI and memory controller interfaces. PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities. * Failure Analysis - Output the state of the processor after a failure for analysis via Crashdump. PECI uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes variable data transfer rate established with every message. In this way, it is highly flexible even though underlying logic is simple. The interface design was optimized for interfacing between an Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information. This implementation provides the basic framework to add PECI extensions to the Linux bus and device models. A hardware specific 'Adapter' driver can be attached to the PECI bus to provide sideband functions described above. It is also possible to access all devices on an adapter from userspace through the /dev interface. A device specific 'Client' driver also can be attached to the PECI bus so each processor client's features can be supported by the 'Client' driver through an adapter connection in the bus. OpenBMC-Staging-Count: 2 Signed-off-by: Jason M Biils <jason.m.bills@linux.intel.com> Signed-off-by: Yunge Zhu <yunge.zhu@linux.intel.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08Documentation: ioctl: Add ioctl numbers for PECI subsystemJae Hyun Yoo1-0/+2
This commit updates ioctl-number.rst to reflect ioctl numbers used by the PECI subsystem. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08dt-bindings: Add PECI subsystem documentJae Hyun Yoo2-0/+183
This commit adds PECI subsystem document. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08clk: ast2600: enable BCLK for PCI/PCIe bus alwaysJae Hyun Yoo1-1/+1
BCLK for PCI/PCIe bus should be enabled always with having the CLK_IS_CRITICAL flag otherwise it will be disabled at kernel late initcall phase as an unused clock, and eventually it causes unexpected behavior on BMC features that are connected to the host through PCI/PCIe bus. OpenBMC-Staging-Count: 2 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08soc: aspeed: Fail probe of lpc-ctrl if reserved memory is not alignedAndrew Jeffery1-0/+13
Alignment is a hardware constraint of the LPC2AHB bridge, and misaligned reserved memory will present as corrupted data. OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-08pinctrl: aspeed: Improve debug outputAndrew Jeffery1-3/+22
We need to iterate over each pin in a group for a function and disable higher priority mux configurations on the pin before finally muxing the relevant function's signal. With the current debug output it is hard to track what register output is relevant to which operation, so break up the actions in the debug output by providing some more context. Before: [ 5.446656] aspeed-g6-pinctrl 1e6e2000.syscon:pinctrl: request pin 37 (B26) for 1e780000.gpio:341 [ 5.447377] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.447854] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.448340] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 After: [ 5.298053] Muxing pin 37 for GPIO [ 5.298294] Disabling signal NRI4 for NRI4 [ 5.298593] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.298983] Disabling signal RGMII4RXD1 for RGMII4 [ 5.299309] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.299694] Disabling signal RMII4RXD1 for RMII4 [ 5.300014] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.300396] Enabling signal GPIOE5 for GPIOE5 [ 5.300687] Muxed pin 37 as GPIOE5 OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 21:13:03 +0300