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2018-04-20drm: Add ASPEED GFX driverJoel Stanley8-0/+681
This driver is for the ASPEED BMC SoC's GFX display hardware. This driver runs on the ARM based BMC systems, unlike the ast driver which runs on a host CPU and is is for a PCI graphics device. The AST2500 supports a total of 3 output paths: 1. VGA output, the output target can choose either or both to the DAC or DVO interface. 2. Graphics CRT output, the output target can choose either or both to the DAC or DVO interface. 3. Video input from DVO, the video input can be used for video engine capture or DAC display output. Output options are selected in SCU2C. The "VGA mode" device is the PCI attached controller. The "Graphics CRT" is the ARM's internal display controller. The driver only supports a simple configuration consisting of a 40MHz pixel clock, fixed by hardware limitations, and the VGA output path. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-19drm/simple_kms_helper: Add {enable|disable}_vblank callback supportOleksandr Andrushchenko2-0/+42
If simple_kms_helper based driver needs to work with vblanks, then it has to provide drm_driver.{enable|disable}_vblank callbacks, because drm_simple_kms_helper.drm_crtc_funcs does not provide any. At the same time drm_driver.{enable|disable}_vblank callbacks are marked as deprecated and shouldn't be used by new drivers. Fix this by extending drm_simple_kms_helper.drm_crtc_funcs to provide the missing callbacks. Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1518425574-32671-2-git-send-email-andr2000@gmail.com (cherry picked from commit ac86cba96e2a439883d452772013049f54df2042) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-19drm: introduce drm_dev_{get/put} functionsAishwarya Pant4-22/+41
Reference counting functions in the kernel typically use get/put suffixes. For maintaining coding style consistency, introduce drm_dev_{get/put} functions. All callers of drm_dev_ref() API have been converted in this patch and hence it has been dropped while the drm_dev_unref() API with non-trivial number of users remains for compatibility. The semantic patch scripts/coccinelle/api/drm-get-put.cocci has been updated with the new helper for conversion of drm_dev_unref() to drm_dev_put() Signed-off-by: Aishwarya Pant <aishpant@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/6babda56134035a98220d5d37a4fd4048df214ce.1506413698.git.aishpant@gmail.com (cherry picked from commit 9a96f55034e41b4e002b767e9218d55f03bdff7d) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-19clk: aspeed: Support second reset registerJoel Stanley2-8/+37
The ast2500 has an additional reset register that contains resets not present in the ast2400. This enables support for this register, and adds the one reset line that is controlled by it. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-19dts: aspeed-g5: Expose SuperIO scratch registersAndrew Jeffery1-0/+88
OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-19dts: aspeed-g5: Expose VGA scratch registersAndrew Jeffery1-0/+48
OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-19soc: aspeed: Miscellaneous control interfacesAndrew Jeffery5-0/+204
The ASPEED BMC SoCs have many knobs and switches that are sometimes design-specific and often defy any approach to unify them under an existing subsystem. Add a driver to translate a devicetree table into sysfs entries to expose bits and fields for manipulation from userspace. This encompasses concepts from scratch registers to boolean conditions to enable or disable host interface features. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-19Merge tag 'drm-for-v4.14' into dev-4.13Joel Stanley855-45903/+28842
This is the DRM tree that was merged into the mainline 4.14 kernel. The ASPEED GFX DRM driver requires functionaliy that was included in this tree, so we merge it back into the 4.13 OpenBMC tree. This should have no impact on other parts of the BMC. Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-17aspeed: watchdog: Set bootstatus during probeEddie James1-0/+7
Check the aspeed timeout status register to see if the system has booted from the secondary boot source. If so, set the watchdog device bootstatus flag for "Card previously reset the CPU." OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-17ARM: dts: aspeed: romulus: Add id-button gpio keyLei YU1-0/+6
OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-17net/ncsi: Refactor MAC, VLAN filtersSamuel Mendoza-Jonas4-311/+147
The NCSI driver defines a generic ncsi_channel_filter struct that can be used to store arbitrarily formatted filters, and several generic methods of accessing data stored in such a filter. However in both the driver and as defined in the NCSI specification there are only two actual filters: VLAN ID filters and MAC address filters. The splitting of the MAC filter into unicast, multicast, and mixed is also technically not necessary as these are stored in the same location in hardware. To save complexity, particularly in the set up and accessing of these generic filters, remove them in favour of two specific structs. These can be acted on directly and do not need several generic helper functions to use. This also fixes a memory error found by KASAN on ARM32 (which is not upstream yet), where response handlers accessing a filter's data field could write past allocated memory. [ 114.926512] ================================================================== [ 114.933861] BUG: KASAN: slab-out-of-bounds in ncsi_configure_channel+0x4b8/0xc58 [ 114.941304] Read of size 2 at addr 94888558 by task kworker/0:2/546 [ 114.947593] [ 114.949146] CPU: 0 PID: 546 Comm: kworker/0:2 Not tainted 4.16.0-rc6-00119-ge156398bfcad #13 ... [ 115.170233] The buggy address belongs to the object at 94888540 [ 115.170233] which belongs to the cache kmalloc-32 of size 32 [ 115.181917] The buggy address is located 24 bytes inside of [ 115.181917] 32-byte region [94888540, 94888560) [ 115.192115] The buggy address belongs to the page: [ 115.196943] page:9eeac100 count:1 mapcount:0 mapping:94888000 index:0x94888fc1 [ 115.204200] flags: 0x100(slab) [ 115.207330] raw: 00000100 94888000 94888fc1 0000003f 00000001 9eea2014 9eecaa74 96c003e0 [ 115.215444] page dumped because: kasan: bad access detected [ 115.221036] [ 115.222544] Memory state around the buggy address: [ 115.227384] 94888400: fb fb fb fb fc fc fc fc 04 fc fc fc fc fc fc fc [ 115.233959] 94888480: 00 00 00 fc fc fc fc fc 00 04 fc fc fc fc fc fc [ 115.240529] >94888500: 00 00 04 fc fc fc fc fc 00 00 04 fc fc fc fc fc [ 115.247077] ^ [ 115.252523] 94888580: 00 04 fc fc fc fc fc fc 06 fc fc fc fc fc fc fc [ 115.259093] 94888600: 00 00 06 fc fc fc fc fc 00 00 04 fc fc fc fc fc [ 115.265639] ================================================================== OpenBMC-Staging-Count: 1 Reported-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: npcm: enable L2 cache in NPCM7xx architectureTomer Maimon1-0/+2
This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure. At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments regarding the flags use in L2 cache module. - https://www.spinics.net/lists/arm-kernel/msg613212.html After checking again the L2 cache use in the NPCM7xx, the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE and it is done in the device tree: https://patchwork.kernel.org/patch/10063497/ L2 cache flag mask allowed all the flag option. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit d893c4de012ad586400d9ccf5143884eafd8d841) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11clk: npcm7xx: add clock controllerTali Perry2-0/+723
Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which generates and supplies clocks to all modules within the BMC. OpenBMC-Staging-Count: 1 Signed-off-by: Tali Perry <tali.perry1@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11dt-binding: clk: npcm750: add bindingTali Perry2-0/+144
Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which generates and supplies clocks to all modules within the BMC. OpenBMC-Staging-Count: 1 Signed-off-by: Tali Perry <tali.perry1@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11watchdog: Add Nuvoton NPCM watchdog driverJoel Stanley3-0/+266
The Nuvoton NPCM750 has a watchdog implemented as a single register inside the timer peripheral. This driver exposes that watchdog as a standard watchdog device with coarse timeout intervals, limited by the combination of prescaler and counter that is provided by the hardware. The calculation is taken from the Nuvoton vendor tree. The watchdog is left running if a bootloader had it going. The rate is the one specified in the device tree, or the default value (obtained from the datasheet). There is a pre-timeout IRQ that is wired up. This timeout always occurs 1024 clocks before the timeout. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11dt-bindings: watchdog: Add Nuvoton NPCM descriptionJoel Stanley1-0/+28
These bindings describe the watchdog IP as used by the Nuvoton NPCM750 (Poleg) BMC SoC. OpenBMC-Staging-Count: 1 Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11clocksource/drivers/npcm: Add NPCM7xx timer driverTomer Maimon3-0/+224
Add Nuvoton BMC NPCM7xx timer driver. The clocksource Enable 24-bit TIMER0 and TIMER1 counters, while TIMER0 serve as clockevent and TIMER1 serve as clocksource. OpenBMC-Staging-Count: 1 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Brendan Higgins <brendanhiggins@xxxxxxxxxx> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11dt-binding: timer: document NPCM7xx timer DT bindingsTomer Maimon1-0/+21
Added device tree binding documentation for Nuvoton NPCM7xx timer. OpenBMC-Staging-Count: 1 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: npcm: modify configuration for the NPCM7xx BMC.Tomer Maimon2-30/+13
Modify configuration and MakeFile for the Nuvoton NPCM and NPCM7xx BMC. [arnd: took this one late, since it fixes some build problems with the original commit] Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit cd903711fd9dce808b5cc07e509135886d962b0c) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify Nuvoton NPCM7xx device tree structureTomer Maimon3-178/+190
Modify Nuvoton NPCM7xx device tree structure by adding nuvoton common nNPCM7xx device tree structure that include all common modules. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 518d2f43c358da2072948f64df99b1bd417288dc) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify Makefile NPCM750 configuration nameTomer Maimon1-1/+1
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 82e9f1d1f87d23ae943f8508a720f482bc2de256) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify clock binding in NPCM750 device treeTomer Maimon1-14/+44
Modify clock binding in a common device tree for all Nuvoton NPCM750 BMCs. Modify NPCM750 modules clock numbers accourding the new clock driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 016c366f505f96dce2a4d0e1e9075fe6e0dfad3e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify timer register size in NPCM750 device treeTomer Maimon1-1/+1
Modify timer register size in a common device tree for all Nuvoton NPCM750 BMCs. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 4828b20a0b89efba524eb34b3234d98683dbe108) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: modify UART compatible name in NPCM750 device treeTomer Maimon1-4/+4
Modify UART compatible name in a common device tree for all Nuvoton NPCM750 BMCs. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 33a5365900e9cf914cd1d2bdde1457b79b3e9ed9) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: add watchdog device to NPCM750 device treeTomer Maimon2-0/+28
Add watchdog device node to a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 1c4937eec91426014247b9ae8cb3f04935cd4865) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11serial: 8250: Add Nuvoton NPCM UARTJoel Stanley4-0/+38
The Nuvoton UART is almost compatible with the 8250 driver when probed via the 8250_of driver, however it requires some extra configuration at startup. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit f597fbce38d230af95384f4a04e0a13a1d0ad45d) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: dts: add Nuvoton NPCM750 device treeBrendan Higgins5-0/+250
Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit d6bdd009c21db3f677dd1d1bbb8c20bc819074bc) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11arm: npcm: add basic support for Nuvoton BMCsBrendan Higgins7-0/+172
Adds basic support for the Nuvoton NPCM750 BMC. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 7bffa14c9aed5f788d3126271f0fd8758fbd129e) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-11MAINTAINERS: Add entry for the Nuvoton NPCM architectureBrendan Higgins1-0/+14
Add maintainers and reviewers for the Nuvoton NPCM architecture. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> (cherry picked from commit 6a498e06ba22872d3a27cc0dae77b9314b1de48b) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-05serial/aspeed-vuart: Implement quick throttle mechanismJeremy Kerr1-4/+99
Although we populate the ->throttle and ->unthrottle UART operations, these may not be called until the ldisc has had a chance to schedule and check buffer space. This means that we may overflow the flip buffers without ever hitting the ldisc's throttle threshold. This change implements an interrupt-based throttle, where we check for space in the flip buffers before reading characters from the UART's FIFO. If there's no space available, we disable the RX interrupt and schedule a timer to check for space later. This prevents a case where we drop characters under heavy RX load. OpenBMC-Staging-Count: 1 Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Tested-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-05serial/aspeed-vuart: Implement rx throttlingJeremy Kerr1-0/+27
The aspeed VUART runs at LPC bus frequency, rather than being restricted to a typical UART baud rate. This means that the VUART can receive a lot of data, which can overrun tty flip buffers, and/or cause a large amount of interrupt traffic. This change implements the uart_port->throttle & unthrottle callbacks, implemented by disabling the receiver line status & received data available IRQs. OpenBMC-Staging-Count: 1 Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Tested-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-05serial/8250: export serial8250_read_charJeremy Kerr2-1/+3
Currently, we export serial8250_rx_chars, which does a whole bunch of reads from the 8250 data register, without any form of flow control between reads. An upcoming change to the aspeed vuart driver implements more fine-grained flow control in the interrupt handler, requiring character-at-a-time control over the rx path. This change exports serial8250_read_char to allow this. OpenBMC-Staging-Count: 1 Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Tested-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-05serial: Introduce UPSTAT_SYNC_FIFO for synchronised FIFOsJeremy Kerr2-2/+3
This change adds a flag to indicate that a UART is has an external means of synchronising its FIFO, without needing CTSRTS or XON/XOFF. This allows us to use the throttle/unthrottle callbacks, without having to claim other methods of flow control. OpenBMC-Staging-Count: 1 Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Tested-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-05serial: expose buf_overrun count through proc interfaceJeremy Kerr1-0/+2
The buf_overrun count is only every written, and not exposed to userspace anywhere. This means that dropped characters due to flip buffer overruns are never visible to userspace. The /proc/tty/driver/serial file exports a bunch of metrics (including hardware overruns) already, so add the buf_overrun (as "bo:") to this file. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Tested-by: Eddie James <eajames@linux.vnet.ibm.com> (cherry picked from commit 4f794097797f551917b68797e39f25fcb17d5b3a) Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-04-04pmbus (max31785): Wrap all I2C accessors in one-shot failure handlersAndrew Jeffery1-42/+165
The MAX31785(A) has shown erratic behaviour across multiple system designs, unexpectedly clock stretching and NAKing transactions. Perform a one-shot retry if necessary for all access attempts. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com>
2018-04-04pmbus (core): Use driver callbacks in pmbus_get_fan_rate()Andrew Jeffery1-4/+4
The driver may have overridden the pmbus_read_byte_data() callback, so make sure we use that to achieve expected behaviour. This helps in the MAX31785 case where we may need to perform a one-shot retry of transfers in the face of a failure. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com>
2018-04-04pmbus (core): One-shot retries for failure to set pageAndrew Jeffery1-2/+10
Work around the shonky behaviour seen with the MAX31785 where we fail to set the page register in some circumstances. There's no real elegant way to do this. We can propagate the error up, but that forces us to retry the operation way up the call tree in any number of places. It also forces callers to split out pmbus_set_page() from the pmbus_{read,write}_{byte,word}_data() functions in order to differentiate between a failure to set the page and a failure to read a register (that might not exist, in which case an error is anticiptated). OpenBMC-Staging-Count: 2 Cc: Eddie James <eajames@linux.vnet.ibm.com> Cc: Matt Spinler <mspinler@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com>
2018-04-04pmbus (max31785): Add support for devicetree configurationAndrew Jeffery1-0/+318
OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com>
2018-04-04dt-bindings: hwmon: pmbus: Add Maxim MAX31785 documentationAndrew Jeffery1-0/+158
OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
2018-03-28clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as criticalJoel Stanley1-2/+2
This is used by the host to talk to the BMC's PCIe slave device. The BMC is not involved, but the clock needs to be enabled so the host can use the device. OpenBMC-Staging-Count: 1 Acked-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: Lei YU <mine260309@gmail.com> Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-28ARM: dts: aspeed: Describe random number deviceJoel Stanley2-0/+14
There is a random number generator that updates a register in the SCU every second. This is compatible with the timeriomem rng driver in the kernel. From the timeriomem_rng bindings: quality: estimated number of bits of true entropy per 1024 bits read from the rng. Defaults to zero which causes the kernel's default quality to be used instead. Note that the default quality is usually zero which disables using this rng to automatically fill the kernel's entropy pool. As to the recommended value for us to use: Rick Altherr <raltherr@google.com> wrote: > Quality is #bit of entropy per 1000 bits read. 100 is a > conservative value that was suggested by those in the know. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-21hwmon (occ): Fix an infinite for loop issueLei YU1-1/+1
The for loop without ++i cause either infinite loop or random memory access issues, e.g. unable to handle kernel NULL or kernel oops in snprintf. Fix it by adding ++i in the for loop. OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-19hwmon: (ucd9000) Add debugfs attributes to provide mfr_statusChristopher Bostic1-1/+137
Expose the gpiN_fault fields of mfr_status as individual debugfs attributes. This provides a way for users to be easily notified of gpi faults. Also provide the whole mfr_status register in debugfs. Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit 72816cb06e7153c22aed8776949f558b635aa2c0) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-19hwmon: (ucd9000) Add gpio chip interfaceChristopher Bostic1-0/+212
Add a struct gpio_chip and define some methods so that this device's I/O can be accessed via /sys/class/gpio. Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit ca781fb7fd95ba90eda6936a27fc1e3202f99d6a) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-19watchdog: aspeed: Allow configuring for alternate bootMilton Miller1-0/+1
Allow the device tree to specify a watchdog to fallover to the alternate boot source. The aspeeed watchdog can set a latch directing flash chip select 0 to chip select 1, allowing boot from an alternate media if the watchdog is not reset in time. On the ast2400 bank 1 also goes to flash bank 1, while on the ast2500 the chip selects are swapped. Also clear the secondary boot bit during the machine restart operation. Otherwise, the system will switch to the alternate boot after every reboot, which is not desired. Signed-off-by: Milton Miller <miltonm@us.ibm.com> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit 6d2c9594b406b00101aa2b0c0c775e794c773c26) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-13ARM: dts: aspeed: witherspoon: set alternate bootEddie James1-0/+4
Set watchdog 2 to boot from the alternate flash chip when the watchdog timer expires and the system is reset. This enables "brick protection." OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-13clk: aspeed: Fix is_enabled for certain clocksEddie James1-1/+2
Some of the Aspeed clocks are disabled by setting the relevant bit in the "clock stop control" register to one, while others are disabled by setting their bit to zero. The driver already uses a flag per gate to identify this behavior, but doesn't apply it in the clock is_enabled function. Use the existing gate flag to correctly return whether or not a clock is enabled in the aspeed_clk_is_enabled function. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
2018-03-13watchdog: aspeed: Allow configuring for alternate bootMilton Miller1-0/+3
Allow the device tree to specify a watchdog to fallover to the alternate boot source. The aspeeed watchdog can set a latch directing flash chip select 0 to chip select 1, allowing boot from an alternate media if the watchdog is not reset in time. On the ast2400 bank 1 also goes to flash bank 1, while on the ast2500 the chip selects are swapped. OpenBMC-Staging-Count: 2 Signed-off-by: Milton Miller <miltonm@us.ibm.com> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-13watchdog: aspeed: Fix translation of reset mode to ctrl registerMilton Miller1-3/+6
Assert RESET_SYSTEM bit for any reset and set MODE field from reset type. The watchdog control register has a RESET_SYSTEM bit that is really closer to activate a reset, and RESET_SYSTEM_MODE field that chooses how much to reset. Before this patch, a node without these optional property would do a SOC reset, but a node with properties requesting a cpu or SOC reset would do nothing and a node requesting a system reset would do a SOC reset. OpenBMC-Staging-Count: 2 Fixes: dc36d8707159 ("drivers/watchdog: ASPEED reference dev tree properties for config") Signed-off-by: Milton Miller <miltonm@us.ibm.com> Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-03-08clk: aspeed: Prevent reset if clock is enabledEddie James1-2/+13
According to the ASPEED specification, the reset and enable sequence should be done when the clock is stopped. The specification doesn't define behavior if the reset is done while the clock is enabled. From testing on the AST2500 and AST2400, the LPC Controller has problems if the clock is reset while enabled. Therefore, check whether the clock is enabled or not before performing the reset and enable sequence in the ASPEED clock driver. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-26 12:55:45 +0300