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2010-12-02drm/i915: Kill the get_fence tracepointChris Wilson2-25/+0
As the tracepoint is now decoupled from when the actual register is assigned and was never complemented by detailing when the object lost its fence, it has outlived its limited usefulness. Profiling the actual stalls is a far more profitable venture anyway. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-02drm/i915: Remove inactive LRU tracking from set_domain_ioctlChris Wilson1-17/+0
As the userspace mappings are torn down on every GPU write, we prefer to track when the buffer is activated (via a fresh i915_gem_fault). This makes the LRU conceptually simpler. With coherent mappings, the remaining use-case for set_domain_ioctl is GPU synchronisation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-02drm/i915: Pipelined fencing [infrastructure]Chris Wilson6-166/+274
With this change, every batchbuffer can use all available fences (save pinned and scanout, of course) without ever stalling the gpu! In theory. Currently the actual pipelined update of the register is disabled due to some stability issues. However, just the deferred update is a significant win. Based on a series of patches by Daniel Vetter. The premise is that before every access to a buffer through the GTT we have to declare whether we need a register or not. If the access is by the GPU, a pipelined update to the register is made via the ringbuffer, and we track the last seqno of the batches that access it. If by the CPU we wait for the last GPU access and update the register (either to clear or to set it for the current buffer). One advantage of being able to pipeline changes is that we can defer the actual updating of the fence register until we first need to access the object through the GTT, i.e. we can eliminate the stall on set_tiling. This is important as the userspace bo cache does not track the tiling status of active buffers which generate frequent stalls on gen3 when enabling tiling for an already bound buffer. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-12-02drm/i915: Prevent stalling for a GTT read back from a read-only GPU targetChris Wilson3-3/+13
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-01drm/i915/lvds: Disable panel-fitter on gen4 for 1:1 scale factorsChris Wilson1-12/+15
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-30drm/i915/ringbuffer: Handle cliprects in the callerChris Wilson5-79/+67
This makes the various rings more consistent by removing the anomalous handing of the rendering ring execbuffer dispatch. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-30drm/i915: Move instruction state invalidation from execbuffer to flushChris Wilson1-11/+4
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-28drm/i915: Release fenced GTT mapping on suspendChris Wilson1-2/+9
... so that upon first use after resume we will reacquire the fence reg. Reported-by: Keith Packard <keithp@keithp.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-28Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson3-85/+28
Conflicts: drivers/gpu/drm/i915/i915_gem.c
2010-11-28drm/i915/execbuffer: On error, starting unwinding from the previous objectChris Wilson1-0/+3
As the error occurred on the current object, it means that its state was not changed and so it should be excluded from the unwind. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-28drm/i915: fix regression due to ba3d8d749b01548b9Daniel Vetter1-25/+18
We don't track gpu flush request in any special way. So even with obj->write_domain == 0, a gpu flush might be outstanding but no yet executed. Even worse, the latest request might use the object only for reading. So and unconditional call to object_wait_rendering is needed for !pipelined. Hence revert that patch fully and untangle the flushing from the synchronization again. Reported-by: Keith Packard <keithp@keithp.com> Tested-by: Keith Packard <keithp@keithp.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-26drm/i915: Avoid allocation for execbuffer object listChris Wilson4-229/+199
Besides the minimal improvement in reducing the execbuffer overhead, the real benefit is clarifying a few routines. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-26drm/i915: Split i915_gem_execbuffer into its own file.Chris Wilson4-1152/+1188
A number of dragons have been seen lurking within the execbuffer code. The first step is then to isolate them from the rest and begin to scrutinise them in depth. Suggested by Daniel Vetter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25drm/i915: Defer accounting until read from debugfsChris Wilson3-128/+95
Simply remove our accounting of objects inside the aperture, keeping only track of what is in the aperture and its current usage. This removes the over-complication of BUGs that were attempting to keep the accounting correct and also removes the overhead of the accounting on the hot-paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25drm/i915: Mark a few functions as __must_checkChris Wilson2-56/+58
... to benefit from the compiler checking that we remember to handle and propagate errors. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25drm/i915: Tweak on-error bbaddr parsing for clarityChris Wilson1-11/+8
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25drm/i915: Only save and restore fences for UMSChris Wilson2-53/+61
With KMS, we can simply relinquish the fence when we idle the GPU and reassign it upon first use. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25drm/i915: Add a mechanism for pipelining fence register updatesDaniel Vetter2-43/+98
Not employed just yet... Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-24drm/i915/sdvo: Always add a 30ms delay to make SDVO TV detection reliableChris Wilson1-3/+5
Commit d09c23de intended to add a 30ms delay to give the ADD time to detect any TVs connected. However, it used the sdvo->is_tv flag to do so which is dependent upon the previous detection result and not whether the output supports TVs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2010-11-24drm/i915: More accurately track last fence usage by the GPUChris Wilson3-52/+78
Based on a patch by Daniel Vetter. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-24drm/i915: Rework execbuffer pinningChris Wilson1-23/+58
Avoid evicting buffers that will be used later in the batch in order to make room for the initial buffers by pinning all bound buffers in a single pass before binding (and evicting for) fresh buffer. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-24MAINTAINERS: INTEL DRM DRIVERS list (intel-gfx) is subscribers-onlyJoe Perches1-1/+1
Mark it so. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-24drm/i915/sdvo: Always fallback to querying the shared DDC lineChris Wilson1-45/+6
On a few devices, like the Mac Mini, the CRT DDC pins are shared between the analog connector and the digital connector. In this scenario, rely on the EDID to determine if a digital panel is connected to the digital connector. Reported-and-tested-by: Tino Keitel <tino.keitel@tikei.de> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Thread the pipelining ring through the callers.Chris Wilson4-20/+18
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Extend hangcheck timeoutChris Wilson1-1/+1
... reduce the frequency of checking to further reduce the wakeups and CPU overhead. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Remove a defunct BUG_ONChris Wilson1-1/+0
This used to check the precondition that all fences were to be located in a mappable area, redundant now as those two parameters are combined into one. After pinning, we assert that the buffer is bound into the desired region. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Move the implementation details of PIPE_CONTROL to the ringbufferChris Wilson3-81/+97
The pipe control object is allocated by the device for the sole use of the render ringbuffer. Move this detail from the general code to the render ring buffer initialisation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Record fence registers on error.Chris Wilson3-0/+34
Having seen the effects of erroneous fencing on the batchbuffer, a useful sanity check is to record the fence registers at the time of an error. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp/intel: Remove duplicate constChris Wilson1-1/+1
drivers/char/agp/intel-gtt.c:340:48: warning: duplicate const Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Not all mappable regions require GTT fence regionsChris Wilson1-31/+22
Combining map_and_fenceable revealed a bug in i915_gem_object_gtt_size() in that it always computed the appropriate fence size for the object regardless of tiling state which caused us to over-allocate linear buffers when binding to the GTT. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: Use drm_i915_gem_object as the preferred typeChris Wilson16-1157/+1019
A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and many characters! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: no more agp for gemDaniel Vetter2-22/+50
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: export api for drm/i915Daniel Vetter2-52/+80
Just some minor shuffling to get rid of any agp traces in the exported functions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: move gtt handling to i915_gem_gtt.cDaniel Vetter3-11/+33
No more drm_*_agp in i915_gem.c! Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp: kill agp_rebind_memoryDaniel Vetter2-21/+0
Its only user, intel-gtt.c is now gone. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: restore gtt on resume in the drm instead of in intel-gtt.koDaniel Vetter5-5/+54
This still uses the agp functions to actually reinstate the mappings (with a gross hack to make agp cooperate), but it wires everything up correctly for the switchover. The call to agp_rebind_memory can be dropped because all non-kms drivers do all their rebinding on EnterVT. v2: Be more paranoid and flush the chipset cache after restoring gtt mappings. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915: track objects in the gttDaniel Vetter2-0/+8
This is required to restore gtt mappings on resume when agp is gone. The right way to do this would be to make sturct drm_mm_node embeddable and use the allocation list maintained by the drm memory manager. But that's a bigger project. Getting rid of the per bo agp_mem will save more memory than this wastes, anyway. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp: kill agp_flush_chipset and corresponding ioctlDaniel Vetter7-25/+0
The intel drm calls the chipset functions now directly. Userspace never called the corresponding ioctl, hence it can be killed, too. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm: kill drm_agp_chipset_flushDaniel Vetter2-7/+0
No longer used. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915/gtt: call chipset flush directlyDaniel Vetter3-6/+12
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23drm/i915|intel-gtt: consolidate intel-gtt.h headersDaniel Vetter4-26/+12
... and a few other defines. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: fold i81x-only dcache support into the generic driverDaniel Vetter1-89/+61
Now the intel-gtt.c rewrite is complete! Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: switch i81x to the common initialization helpersDaniel Vetter1-127/+71
Still a separate agp_bridge_driver because of the i81x-only dedicated vram support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: switch i81x to the write_entry helpersDaniel Vetter1-92/+60
Initialization is still done with the old code with a few added things sprinkled in to make the intel_fake_agp helper functions work. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: kill unneeded sandybridge memory typesDaniel Vetter1-6/+0
Used for the now dead agp type_to_mask stuff. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23intel-gtt: drop dcache support for i830 and laterDaniel Vetter1-7/+1
i830_check_flags already disallows it, so no need to implement it in the write_entry function. Seems to be a remnant from i810 support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2-179/+307
2010-11-23drm/i915: Handle pagefaults in execbuffer user relocationsChris Wilson1-168/+293
Currently if we hit a pagefault when applying a user relocation for the execbuffer, we bail and return EFAULT to the application. Instead, we need to unwind, drop the dev->struct_mutex, copy all the relocation entries to a vmalloc array (to avoid any potential circular deadlocks when resolving the pagefault), retake the mutex and then apply the relocations. Afterwards, we need to again drop the lock and copy the vmalloc array back to userspace. v2: Incorporate feedback from Daniel Vetter. Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-11-23drm/i915: Contract the magic IPS constants into a direct LUTChris Wilson1-160/+144
... and no need to perform a linear search for the index. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23agp/intel: Remove confusion of stolen entries not stolen memoryChris Wilson4-42/+15
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>