diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-powerpc/cpm.h | 73 | ||||
| -rw-r--r-- | include/asm-powerpc/cpm1.h (renamed from include/asm-powerpc/commproc.h) | 77 | ||||
| -rw-r--r-- | include/asm-powerpc/cpm2.h | 64 | ||||
| -rw-r--r-- | include/asm-powerpc/irq.h | 212 | ||||
| -rw-r--r-- | include/asm-powerpc/mpc8xx.h | 20 | ||||
| -rw-r--r-- | include/asm-ppc/cpm1.h (renamed from include/asm-ppc/commproc.h) | 12 | ||||
| -rw-r--r-- | include/asm-ppc/cpm2.h | 2 | ||||
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 126 | ||||
| -rw-r--r-- | include/asm-ppc/mmu_context.h | 5 | ||||
| -rw-r--r-- | include/asm-ppc/mpc83xx.h | 107 | ||||
| -rw-r--r-- | include/asm-ppc/mpc85xx.h | 192 | ||||
| -rw-r--r-- | include/asm-ppc/pgtable.h | 46 | ||||
| -rw-r--r-- | include/asm-ppc/ppc_sys.h | 4 | ||||
| -rw-r--r-- | include/asm-ppc/ppcboot.h | 8 | ||||
| -rw-r--r-- | include/asm-ppc/reg_booke.h | 26 | ||||
| -rw-r--r-- | include/asm-ppc/serial.h | 4 |
16 files changed, 86 insertions, 892 deletions
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h index fae83b137337..77e39dad9728 100644 --- a/include/asm-powerpc/cpm.h +++ b/include/asm-powerpc/cpm.h @@ -4,6 +4,79 @@ #include <linux/compiler.h> #include <linux/types.h> +/* Buffer descriptors used by many of the CPM protocols. */ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; + +/* Buffer descriptor control/status used by serial + */ + +#define BD_SC_EMPTY (0x8000) /* Receive is empty */ +#define BD_SC_READY (0x8000) /* Transmit is ready */ +#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT (0x1000) /* Interrupt on change */ +#define BD_SC_LAST (0x0800) /* Last buffer in frame */ +#define BD_SC_TC (0x0400) /* Transmit CRC */ +#define BD_SC_CM (0x0200) /* Continous mode */ +#define BD_SC_ID (0x0100) /* Rec'd too many idles */ +#define BD_SC_P (0x0100) /* xmt preamble */ +#define BD_SC_BR (0x0020) /* Break received */ +#define BD_SC_FR (0x0010) /* Framing error */ +#define BD_SC_PR (0x0008) /* Parity error */ +#define BD_SC_NAK (0x0004) /* NAK - did not respond */ +#define BD_SC_OV (0x0002) /* Overrun */ +#define BD_SC_UN (0x0002) /* Underrun */ +#define BD_SC_CD (0x0001) /* */ +#define BD_SC_CL (0x0001) /* Collision */ + +/* Buffer descriptor control/status used by Ethernet receive. + * Common to SCC and FCC. + */ +#define BD_ENET_RX_EMPTY (0x8000) +#define BD_ENET_RX_WRAP (0x2000) +#define BD_ENET_RX_INTR (0x1000) +#define BD_ENET_RX_LAST (0x0800) +#define BD_ENET_RX_FIRST (0x0400) +#define BD_ENET_RX_MISS (0x0100) +#define BD_ENET_RX_BC (0x0080) /* FCC Only */ +#define BD_ENET_RX_MC (0x0040) /* FCC Only */ +#define BD_ENET_RX_LG (0x0020) +#define BD_ENET_RX_NO (0x0010) +#define BD_ENET_RX_SH (0x0008) +#define BD_ENET_RX_CR (0x0004) +#define BD_ENET_RX_OV (0x0002) +#define BD_ENET_RX_CL (0x0001) +#define BD_ENET_RX_STATS (0x01ff) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. + * Common to SCC and FCC. + */ +#define BD_ENET_TX_READY (0x8000) +#define BD_ENET_TX_PAD (0x4000) +#define BD_ENET_TX_WRAP (0x2000) +#define BD_ENET_TX_INTR (0x1000) +#define BD_ENET_TX_LAST (0x0800) +#define BD_ENET_TX_TC (0x0400) +#define BD_ENET_TX_DEF (0x0200) +#define BD_ENET_TX_HB (0x0100) +#define BD_ENET_TX_LC (0x0080) +#define BD_ENET_TX_RL (0x0040) +#define BD_ENET_TX_RCMASK (0x003c) +#define BD_ENET_TX_UN (0x0002) +#define BD_ENET_TX_CSL (0x0001) +#define BD_ENET_TX_STATS (0x03ff) /* All status bits */ + +/* Buffer descriptor control/status used by Transparent mode SCC. + */ +#define BD_SCC_TX_LAST (0x0800) + +/* Buffer descriptor control/status used by I2C. + */ +#define BD_I2C_START (0x0400) + int cpm_muram_init(void); unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); int cpm_muram_free(unsigned long offset); diff --git a/include/asm-powerpc/commproc.h b/include/asm-powerpc/cpm1.h index 9e3b8648648c..b2ebd6ac6dae 100644 --- a/include/asm-powerpc/commproc.h +++ b/include/asm-powerpc/cpm1.h @@ -14,8 +14,8 @@ * IDMA1 space. The remaining DP RAM is available for buffer descriptors * or other use. */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ +#ifndef __CPM1__ +#define __CPM1__ #include <asm/8xx_immap.h> #include <asm/ptrace.h> @@ -82,42 +82,14 @@ extern int cpm_dpfree(unsigned long offset); extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); extern void cpm_dpdump(void); extern void *cpm_dpram_addr(unsigned long offset); -extern uint cpm_dpram_phys(u8* addr); +extern uint cpm_dpram_phys(u8 *addr); #endif extern void cpm_setbrg(uint brg, uint rate); -extern uint m8xx_cpm_hostalloc(uint size); -extern int m8xx_cpm_hostfree(uint start); -extern void m8xx_cpm_hostdump(void); - extern void cpm_load_patch(cpm8xx_t *cp); -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_UN ((ushort)0x0002) /* Underrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ -#define BD_SC_CL ((ushort)0x0001) /* Collision */ +extern void cpm_reset(void); /* Parameter RAM offsets. */ @@ -448,41 +420,6 @@ typedef struct scc_enet { #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - /* SCC as UART */ typedef struct scc_uart { @@ -551,8 +488,6 @@ typedef struct scc_trans { uint st_cmask; /* Constant mask for CRC */ } scc_trans_t; -#define BD_SCC_TX_LAST ((ushort)0x0800) - /* IIC parameter RAM. */ typedef struct iic { @@ -576,8 +511,6 @@ typedef struct iic { char res2[2]; /* Reserved */ } iic_t; -#define BD_IIC_START ((ushort)0x0400) - /* SPI parameter RAM. */ typedef struct spi { @@ -749,4 +682,4 @@ enum cpm_clk { int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode); -#endif /* __CPM_8XX__ */ +#endif /* __CPM1__ */ diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h index f1112c15ef96..b93a53eb55c1 100644 --- a/include/asm-powerpc/cpm2.h +++ b/include/asm-powerpc/cpm2.h @@ -132,29 +132,6 @@ extern void cpm_setbrg(uint brg, uint rate); extern void cpm2_fastbrg(uint brg, uint rate, int div16); extern void cpm2_reset(void); - -/* Buffer descriptors used by many of the CPM protocols. -*/ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; - -#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* ?? */ - /* Function code bits, usually generic to devices. */ #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ @@ -456,43 +433,6 @@ typedef struct scc_enet { #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ -/* Buffer descriptor control/status used by Ethernet receive. - * Common to SCC and FCC. - */ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ -#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. - * Common to SCC and FCC. - */ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - /* SCC as UART */ typedef struct scc_uart { @@ -562,8 +502,6 @@ typedef struct scc_trans { uint st_cmask; /* Constant mask for CRC */ } scc_trans_t; -#define BD_SCC_TX_LAST ((ushort)0x0800) - /* How about some FCCs..... */ #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) @@ -769,8 +707,6 @@ typedef struct spi { #define SPI_EB ((u_char)0x10) /* big endian byte order */ -#define BD_IIC_START ((ushort)0x0400) - /* IDMA parameter RAM */ typedef struct idma { diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 1392db456523..b5c03127a9b9 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -483,218 +483,6 @@ static __inline__ int irq_canonicalize(int irq) */ #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) -#elif defined(CONFIG_83xx) -#include <asm/mpc83xx.h> - -#define NR_IRQS (NR_IPIC_INTS) - -#elif defined(CONFIG_85xx) -/* Now include the board configuration specific associations. -*/ -#include <asm/mpc85xx.h> - -/* The MPC8548 openpic has 48 internal interrupts and 12 external - * interrupts. - * - * We are "flattening" the interrupt vectors of the cascaded CPM - * so that we can uniquely identify any interrupt source with a - * single integer. - */ -#define NR_CPM_INTS 64 -#define NR_EPIC_INTS 60 -#ifndef NR_8259_INTS -#define NR_8259_INTS 0 -#endif -#define NUM_8259_INTERRUPTS NR_8259_INTS - -#ifndef CPM_IRQ_OFFSET -#define CPM_IRQ_OFFSET 0 -#endif - -#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS) - -/* Internal IRQs on MPC85xx OpenPIC */ - -#ifndef MPC85xx_OPENPIC_IRQ_OFFSET -#ifdef CONFIG_CPM2 -#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) -#else -#define MPC85xx_OPENPIC_IRQ_OFFSET 0 -#endif -#endif - -/* Not all of these exist on all MPC85xx implementations */ -#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) - -/* The 12 external interrupt lines */ -#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET) -#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET) - -/* CPM related interrupts */ -#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) -#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) -#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) -#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) -#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) -#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) -#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) -#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) -#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) -#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) -#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) -#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) -#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) -#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) -#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) -#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) -#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) -#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) -#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) -#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) -#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) -#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) -#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) -#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) -#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) -#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) -#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) -#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) -#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) -#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) -#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) -#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) -#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) - -#elif defined(CONFIG_PPC_86xx) -#include <asm/mpc86xx.h> - -#define NR_EPIC_INTS 48 -#ifndef NR_8259_INTS -#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */ -#endif -#define NUM_8259_INTERRUPTS NR_8259_INTS - -#ifndef I8259_OFFSET -#define I8259_OFFSET 0 -#endif - -#define NR_IRQS 256 - -/* Internal IRQs on MPC86xx OpenPIC */ - -#ifndef MPC86xx_OPENPIC_IRQ_OFFSET -#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS -#endif - -/* The 48 internal sources */ -#define MPC86xx_IRQ_NULL ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_MCM ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DDR ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_LBC ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA0 ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA1 ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA2 ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_DMA3 ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET) - -/* no 10,11 */ -#define MPC86xx_IRQ_UART2 (12 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_TX (13 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_RX (14 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_TX (15 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_RX (16 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_TX (19 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_RX (20 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_TX (21 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_RX (22 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 25 */ -#define MPC86xx_IRQ_UART1 (26 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_IIC (27 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_PERFMON (28 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 29,30,31 */ -#define MPC86xx_IRQ_SRIO_ERROR (32 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_BELL (34 + MPC86xx_OPENPIC_IRQ_OFFSET) -/* no 35,36 */ -#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_MSG1 (38 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_SRIO_IN_MSG2 (40 + MPC86xx_OPENPIC_IRQ_OFFSET) - -/* The 12 external interrupt lines */ -#define MPC86xx_IRQ_EXT_BASE 48 -#define MPC86xx_IRQ_EXT0 (0 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT1 (1 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT2 (2 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT3 (3 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT4 (4 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT5 (5 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT6 (6 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT7 (7 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT8 (8 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT9 (9 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT10 (10 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) -#define MPC86xx_IRQ_EXT11 (11 + MPC86xx_IRQ_EXT_BASE \ - + MPC86xx_OPENPIC_IRQ_OFFSET) - #else /* CONFIG_40x + CONFIG_8xx */ /* * this is the # irq's for all ppc arch's (pmac/chrp/prep) diff --git a/include/asm-powerpc/mpc8xx.h b/include/asm-powerpc/mpc8xx.h index 2be014b6f57c..98f3c4f17328 100644 --- a/include/asm-powerpc/mpc8xx.h +++ b/include/asm-powerpc/mpc8xx.h @@ -4,29 +4,9 @@ * file that has to include MPC8xx configuration, they all include * this one and the configuration switching is done here. */ -#ifdef __KERNEL__ #ifndef __CONFIG_8xx_DEFS #define __CONFIG_8xx_DEFS - -#ifdef CONFIG_8xx - -#ifdef CONFIG_FADS -#include <platforms/fads.h> -#endif - -#if defined(CONFIG_MPC86XADS) -#include <platforms/8xx/mpc86xads.h> -#endif - -#if defined(CONFIG_MPC885ADS) -#include <platforms/8xx/mpc885ads.h> -#endif - -#ifdef CONFIG_PCMCIA_M8XX extern struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops; -#endif -#endif /* CONFIG_8xx */ #endif /* __CONFIG_8xx_DEFS */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/cpm1.h index 462abb185f07..03035acd85c6 100644 --- a/include/asm-ppc/commproc.h +++ b/include/asm-ppc/cpm1.h @@ -14,8 +14,8 @@ * IDMA1 space. The remaining DP RAM is available for buffer descriptors * or other use. */ -#ifndef __CPM_8XX__ -#define __CPM_8XX__ +#ifndef __CPM1__ +#define __CPM1__ #include <asm/8xx_immap.h> #include <asm/ptrace.h> @@ -72,13 +72,9 @@ extern int cpm_dpfree(unsigned long offset); extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); extern void cpm_dpdump(void); extern void *cpm_dpram_addr(unsigned long offset); -extern uint cpm_dpram_phys(u8* addr); +extern uint cpm_dpram_phys(u8 *addr); extern void cpm_setbrg(uint brg, uint rate); -extern uint m8xx_cpm_hostalloc(uint size); -extern int m8xx_cpm_hostfree(uint start); -extern void m8xx_cpm_hostdump(void); - extern void cpm_load_patch(volatile immap_t *immr); /* Buffer descriptors used by many of the CPM protocols. @@ -689,4 +685,4 @@ typedef struct risc_timer_pram { extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); extern void cpm_free_handler(int vec); -#endif /* __CPM_8XX__ */ +#endif /* __CPM1__ */ diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h index 12a2860f9a9c..4c538228e42f 100644 --- a/include/asm-ppc/cpm2.h +++ b/include/asm-ppc/cpm2.h @@ -90,7 +90,7 @@ */ #define CPM_DATAONLY_BASE ((uint)128) #define CPM_DP_NOSPACE ((uint)0x7fffffff) -#if defined(CONFIG_8272) || defined(CONFIG_MPC8555) +#if defined(CONFIG_8272) #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) #else diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h deleted file mode 100644 index 9383d0c13ff8..000000000000 --- a/include/asm-ppc/immap_85xx.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * include/asm-ppc/immap_85xx.h - * - * MPC85xx Internal Memory Map - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IMMAP_85XX_H__ -#define __ASM_IMMAP_85XX_H__ - -/* Eventually this should define all the IO block registers in 85xx */ - -/* PCI Registers */ -typedef struct ccsr_pci { - uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */ - uint cfg_data; /* 0x.004 - PCI Configuration Data Register */ - uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ - char res1[3060]; - uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */ - uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */ - uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */ - char res2[4]; - uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */ - char res3[12]; - uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */ - uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */ - uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */ - char res4[4]; - uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */ - char res5[12]; - uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */ - uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */ - uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */ - char res6[4]; - uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */ - char res7[12]; - uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */ - uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */ - uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */ - char res8[4]; - uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */ - char res9[12]; - uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */ - uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */ - uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */ - char res10[4]; - uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */ - char res11[268]; - uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */ - char res12[4]; - uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */ - uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */ - uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */ - char res13[12]; - uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */ - char res14[4]; - uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */ - uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */ - uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */ - char res15[12]; - uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */ - char res16[4]; - uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */ - char res17[4]; - uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */ - char res18[12]; - uint err_dr; /* 0x.e00 - PCI Error Detect Register */ - uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */ - uint err_en; /* 0x.e08 - PCI Error Enable Register */ - uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */ - uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */ - uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */ - uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */ - uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */ - uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */ - uint pci_timr; /* 0x.e24 - PCI Timer Register */ - char res19[472]; -} ccsr_pci_t; - -/* Global Utility Registers */ -typedef struct ccsr_guts { - uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ - uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ - uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ - uint pordevsr; /* 0x.000c - POR I/O Device Status Register */ - uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ - char res1[12]; - uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */ - char res2[12]; - uint gpiocr; /* 0x.0030 - GPIO Control Register */ - char res3[12]; - uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ - char res4[12]; - uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */ - char res5[12]; - uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ - char res6[12]; - uint devdisr; /* 0x.0070 - Device Disable Control */ - char res7[12]; - uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ - char res8[12]; - uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */ - char res9[12]; - uint pvr; /* 0x.00a0 - Processor Version Register */ - uint svr; /* 0x.00a4 - System Version Register */ - char res10[3416]; - uint clkocr; /* 0x.0e00 - Clock Out Select Register */ - char res11[12]; - uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ - char res12[12]; - uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ - char res13[61916]; -} ccsr_guts_t; - -#endif /* __ASM_IMMAP_85XX_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h index b2e25d8997bf..9f097e25b169 100644 --- a/include/asm-ppc/mmu_context.h +++ b/include/asm-ppc/mmu_context.h @@ -64,11 +64,6 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) #define LAST_CONTEXT 255 #define FIRST_CONTEXT 1 -#elif defined(CONFIG_E200) || defined(CONFIG_E500) -#define NO_CONTEXT 256 -#define LAST_CONTEXT 255 -#define FIRST_CONTEXT 1 - #else /* PPC 6xx, 7xx CPUs */ diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h deleted file mode 100644 index c3061972309b..000000000000 --- a/include/asm-ppc/mpc83xx.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * include/asm-ppc/mpc83xx.h - * - * MPC83xx definitions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2005 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_MPC83xx_H__ -#define __ASM_MPC83xx_H__ - -#include <asm/mmu.h> - -#ifdef CONFIG_83xx - -#ifdef CONFIG_MPC834x_SYS -#include <platforms/83xx/mpc834x_sys.h> -#endif - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern unsigned char __res[]; - -/* Internal IRQs on MPC83xx OpenPIC */ -/* Not all of these exist on all MPC83xx implementations */ - -#ifndef MPC83xx_IPIC_IRQ_OFFSET -#define MPC83xx_IPIC_IRQ_OFFSET 0 -#endif - -#define NR_IPIC_INTS 128 - -#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET) -#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET) - -#define MPC83xx_CCSRBAR_SIZE (1024*1024) - -/* Let modules/drivers get at immrbar (physical) */ -extern phys_addr_t immrbar; - -enum ppc_sys_devices { - MPC83xx_TSEC1, - MPC83xx_TSEC2, - MPC83xx_IIC1, - MPC83xx_IIC2, - MPC83xx_DUART, - MPC83xx_SEC2, - MPC83xx_USB2_DR, - MPC83xx_USB2_MPH, - MPC83xx_MDIO, - NUM_PPC_SYS_DEVS, -}; - -#endif /* CONFIG_83xx */ -#endif /* __ASM_MPC83xx_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h deleted file mode 100644 index d7e4a79d77fb..000000000000 --- a/include/asm-ppc/mpc85xx.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * include/asm-ppc/mpc85xx.h - * - * MPC85xx definitions - * - * Maintainer: Kumar Gala <galak@kernel.crashing.org> - * - * Copyright 2004 Freescale Semiconductor, Inc - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifdef __KERNEL__ -#ifndef __ASM_MPC85xx_H__ -#define __ASM_MPC85xx_H__ - -#include <asm/mmu.h> - -#ifdef CONFIG_85xx - -#ifdef CONFIG_MPC8540_ADS -#include <platforms/85xx/mpc8540_ads.h> -#endif -#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) -#include <platforms/85xx/mpc8555_cds.h> -#endif -#ifdef CONFIG_MPC85xx_CDS -#include <platforms/85xx/mpc85xx_cds.h> -#endif -#ifdef CONFIG_MPC8560_ADS -#include <platforms/85xx/mpc8560_ads.h> -#endif -#ifdef CONFIG_SBC8560 -#include <platforms/85xx/sbc8560.h> -#endif -#ifdef CONFIG_STX_GP3 -#include <platforms/85xx/stx_gp3.h> -#endif -#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \ - defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560) -#include <platforms/85xx/tqm85xx.h> -#endif - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern unsigned char __res[]; - -/* Offset from CCSRBAR */ -#define MPC85xx_CPM_OFFSET (0x80000) -#define MPC85xx_CPM_SIZE (0x40000) -#define MPC85xx_DMA_OFFSET (0x21000) -#define MPC85xx_DMA_SIZE (0x01000) -#define MPC85xx_DMA0_OFFSET (0x21100) -#define MPC85xx_DMA0_SIZE (0x00080) -#define MPC85xx_DMA1_OFFSET (0x21180) -#define MPC85xx_DMA1_SIZE (0x00080) -#define MPC85xx_DMA2_OFFSET (0x21200) -#define MPC85xx_DMA2_SIZE (0x00080) -#define MPC85xx_DMA3_OFFSET (0x21280) -#define MPC85xx_DMA3_SIZE (0x00080) -#define MPC85xx_ENET1_OFFSET (0x24000) -#define MPC85xx_ENET1_SIZE (0x01000) -#define MPC85xx_MIIM_OFFSET (0x24520) -#define MPC85xx_MIIM_SIZE (0x00018) -#define MPC85xx_ENET2_OFFSET (0x25000) -#define MPC85xx_ENET2_SIZE (0x01000) -#define MPC85xx_ENET3_OFFSET (0x26000) -#define MPC85xx_ENET3_SIZE (0x01000) -#define MPC85xx_GUTS_OFFSET (0xe0000) -#define MPC85xx_GUTS_SIZE (0x01000) -#define MPC85xx_IIC1_OFFSET (0x03000) -#define MPC85xx_IIC1_SIZE (0x00100) -#define MPC85xx_OPENPIC_OFFSET (0x40000) -#define MPC85xx_OPENPIC_SIZE (0x40000) -#define MPC85xx_PCI1_OFFSET (0x08000) -#define MPC85xx_PCI1_SIZE (0x01000) -#define MPC85xx_PCI2_OFFSET (0x09000) -#define MPC85xx_PCI2_SIZE (0x01000) -#define MPC85xx_PERFMON_OFFSET (0xe1000) -#define MPC85xx_PERFMON_SIZE (0x01000) -#define MPC85xx_SEC2_OFFSET (0x30000) -#define MPC85xx_SEC2_SIZE (0x10000) -#define MPC85xx_UART0_OFFSET (0x04500) -#define MPC85xx_UART0_SIZE (0x00100) -#define MPC85xx_UART1_OFFSET (0x04600) -#define MPC85xx_UART1_SIZE (0x00100) - -#define MPC85xx_CCSRBAR_SIZE (1024*1024) - -/* Let modules/drivers get at CCSRBAR */ -extern phys_addr_t get_ccsrbar(void); - -#ifdef MODULE -#define CCSRBAR get_ccsrbar() -#else -#define CCSRBAR BOARD_CCSRBAR -#endif - -enum ppc_sys_devices { - MPC85xx_TSEC1, - MPC85xx_TSEC2, - MPC85xx_FEC, - MPC85xx_IIC1, - MPC85xx_DMA0, - MPC85xx_DMA1, - MPC85xx_DMA2, - MPC85xx_DMA3, - MPC85xx_DUART, - MPC85xx_PERFMON, - MPC85xx_SEC2, - MPC85xx_CPM_SPI, - MPC85xx_CPM_I2C, - MPC85xx_CPM_USB, - MPC85xx_CPM_SCC1, - MPC85xx_CPM_SCC2, - MPC85xx_CPM_SCC3, - MPC85xx_CPM_SCC4, - MPC85xx_CPM_FCC1, - MPC85xx_CPM_FCC2, - MPC85xx_CPM_FCC3, - MPC85xx_CPM_MCC1, - MPC85xx_CPM_MCC2, - MPC85xx_CPM_SMC1, - MPC85xx_CPM_SMC2, - MPC85xx_eTSEC1, - MPC85xx_eTSEC2, - MPC85xx_eTSEC3, - MPC85xx_eTSEC4, - MPC85xx_IIC2, - MPC85xx_MDIO, - NUM_PPC_SYS_DEVS, -}; - -/* Internal interrupts are all Level Sensitive, and Positive Polarity */ -#define MPC85XX_INTERNAL_IRQ_SENSES \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \ - (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */ - -#endif /* CONFIG_85xx */ -#endif /* __ASM_MPC85xx_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 063ad91cbbcc..69347bdbb401 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -271,48 +271,6 @@ extern unsigned long ioremap_bot, ioremap_base; /* ERPN in a PTE never gets cleared, ignore it */ #define _PTE_NONE_MASK 0xffffffff00000000ULL -#elif defined(CONFIG_FSL_BOOKE) -/* - MMU Assist Register 3: - - 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 - RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR - - - PRESENT *must* be in the bottom three bits because swap cache - entries use the top 29 bits. - - - FILE *must* be in the bottom three bits because swap cache - entries use the top 29 bits. -*/ - -/* Definitions for FSL Book-E Cores */ -#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */ -#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */ -#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */ -#define _PAGE_ACCESSED 0x00004 /* S: Page referenced */ -#define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */ -#define _PAGE_RW 0x00010 /* S: Write permission */ -#define _PAGE_HWEXEC 0x00020 /* H: UX permission */ - -#define _PAGE_ENDIAN 0x00040 /* H: E bit */ -#define _PAGE_GUARDED 0x00080 /* H: G bit */ -#define _PAGE_COHERENT 0x00100 /* H: M bit */ -#define _PAGE_NO_CACHE 0x00200 /* H: I bit */ -#define _PAGE_WRITETHRU 0x00400 /* H: W bit */ - -#ifdef CONFIG_PTE_64BIT -#define _PAGE_DIRTY 0x08000 /* S: Page dirty */ - -/* ERPN in a PTE never gets cleared, ignore it */ -#define _PTE_NONE_MASK 0xffffffffffff0000ULL -#else -#define _PAGE_DIRTY 0x00800 /* S: Page dirty */ -#endif - -#define _PMD_PRESENT 0 -#define _PMD_PRESENT_MASK (PAGE_MASK) -#define _PMD_BAD (~PAGE_MASK) - #elif defined(CONFIG_8xx) /* Definitions for 8xx embedded chips. */ #define _PAGE_PRESENT 0x0001 /* Page is valid */ @@ -484,11 +442,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); /* in some case we want to additionaly adjust where the pfn is in the pte to * allow room for more flags */ -#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT) -#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8) -#else #define PFN_SHIFT_OFFSET (PAGE_SHIFT) -#endif #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) #define pte_page(x) pfn_to_page(pte_pfn(x)) diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h index de99e92d627b..d2fee41d600b 100644 --- a/include/asm-ppc/ppc_sys.h +++ b/include/asm-ppc/ppc_sys.h @@ -23,10 +23,6 @@ #if defined(CONFIG_8260) #include <asm/mpc8260.h> -#elif defined(CONFIG_83xx) -#include <asm/mpc83xx.h> -#elif defined(CONFIG_85xx) -#include <asm/mpc85xx.h> #elif defined(CONFIG_8xx) #include <asm/mpc8xx.h> #elif defined(CONFIG_PPC_MPC52xx) diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h index 6b7b63f71daa..3819e17cd7b0 100644 --- a/include/asm-ppc/ppcboot.h +++ b/include/asm-ppc/ppcboot.h @@ -38,8 +38,7 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ -#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx) ||\ - defined(CONFIG_83xx) +#if defined(CONFIG_8xx) || defined(CONFIG_CPM2) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_PPC_MPC52xx) @@ -73,12 +72,11 @@ typedef struct bd_info { #if defined(CONFIG_HYMOD) hymod_conf_t bi_hymod_conf; /* hymod configuration information */ #endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) || \ - defined(CONFIG_85xx) || defined(CONFIG_83xx) +#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) /* second onboard ethernet port */ unsigned char bi_enet1addr[6]; #endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) || defined(CONFIG_85xx) +#if defined(CONFIG_EVB64260) || defined(CONFIG_440GX) /* third onboard ethernet ports */ unsigned char bi_enet2addr[6]; #endif diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h index 2f1a2afcfc28..91e96af88bd8 100644 --- a/include/asm-ppc/reg_booke.h +++ b/include/asm-ppc/reg_booke.h @@ -218,32 +218,6 @@ #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ #endif -#ifdef CONFIG_E500 -#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ -#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ -#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ -#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ -#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */ -#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ -#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ -#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ -#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ -#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ -#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ -#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ -#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ -#endif -#ifdef CONFIG_E200 -#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ -#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ -#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ -#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn - fetch for an exception handler */ -#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ -#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ -#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered - store or cache line push */ -#endif /* Bit definitions for the DBSR. */ /* diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h index 8fc1b546613d..d35ed10315b1 100644 --- a/include/asm-ppc/serial.h +++ b/include/asm-ppc/serial.h @@ -29,10 +29,6 @@ #include <platforms/spruce.h> #elif defined(CONFIG_4xx) #include <asm/ibm4xx.h> -#elif defined(CONFIG_83xx) -#include <asm/mpc83xx.h> -#elif defined(CONFIG_85xx) -#include <asm/mpc85xx.h> #elif defined(CONFIG_RADSTONE_PPC7D) #include <platforms/radstone_ppc7d.h> #else |