diff options
Diffstat (limited to 'drivers/pinctrl')
101 files changed, 6174 insertions, 3140 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1778cf4f81c7..4571cc098b76 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -2,11 +2,10 @@ # PINCTRL infrastructure and drivers # -config PINCTRL - bool +menuconfig PINCTRL + bool "Pin controllers" -menu "Pin controllers" - depends on PINCTRL +if PINCTRL config GENERIC_PINCTRL_GROUPS bool @@ -33,7 +32,8 @@ config DEBUG_PINCTRL config PINCTRL_ADI2 bool "ADI pin controller driver" - depends on BLACKFIN + depends on (BF54x || BF60x) + depends on !GPIO_ADI select PINMUX select IRQ_DOMAIN help @@ -98,8 +98,10 @@ config PINCTRL_AT91PIO4 config PINCTRL_AMD tristate "AMD GPIO pin control" - depends on GPIOLIB + depends on HAS_IOMEM + select GPIOLIB select GPIOLIB_IRQCHIP + select PINMUX select PINCONF select GENERIC_PINCONF help @@ -151,12 +153,14 @@ config PINCTRL_GEMINI depends on ARCH_GEMINI default ARCH_GEMINI select PINMUX + select GENERIC_PINCONF select MFD_SYSCON config PINCTRL_MCP23S08 tristate "Microchip MCP23xxx I/O expander" depends on SPI_MASTER || I2C depends on I2C || I2C=n + select GPIOLIB select GPIOLIB_IRQCHIP select REGMAP_I2C if I2C select REGMAP_SPI if SPI_MASTER @@ -167,16 +171,6 @@ config PINCTRL_MCP23S08 This provides a GPIO interface supporting inputs and outputs. The I2C versions of the chips can be used as interrupt-controller. -config PINCTRL_MESON - bool - depends on OF - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB - select OF_GPIO - select REGMAP_MMIO - config PINCTRL_OXNAS bool depends on OF @@ -209,6 +203,7 @@ config PINCTRL_RZA1 config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" depends on OF + depends on HAS_IOMEM select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF @@ -225,10 +220,11 @@ config PINCTRL_SIRF config PINCTRL_SX150X bool "Semtech SX150x I2C GPIO expander pinctrl driver" - depends on GPIOLIB && I2C=y + depends on I2C=y select PINMUX select PINCONF select GENERIC_PINCONF + select GPIOLIB select GPIOLIB_IRQCHIP select REGMAP help @@ -368,6 +364,7 @@ source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/zte/Kconfig" +source "drivers/pinctrl/meson/Kconfig" config PINCTRL_XWAY bool @@ -379,4 +376,4 @@ config PINCTRL_TB10X depends on OF && ARC_PLAT_TB10X select GPIOLIB -endmenu +endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c16e27900dbb..d0d4844f8022 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # generic pinmux support subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 2a65111f3c70..80ceb9dae944 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Broadcom pinctrl support obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 0944310225db..785c366fd6d6 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -373,17 +373,13 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, unsigned long events; unsigned offset; unsigned gpio; - unsigned int type; events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); events &= mask; events &= pc->enabled_irq_map[bank]; for_each_set_bit(offset, &events, 32) { gpio = (32 * bank) + offset; - /* FIXME: no clue why the code looks up the type here */ - type = pc->irq_type[gpio]; - - generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain, + generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain, gpio)); } } @@ -665,7 +661,7 @@ static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev, enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); const char *fname = bcm2835_functions[fsel]; int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset); - int irq = irq_find_mapping(chip->irqdomain, offset); + int irq = irq_find_mapping(chip->irq.domain, offset); seq_printf(s, "function %s in %s; irq %d (%s)", fname, value ? "hi" : "lo", diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 85a8c97d9dfe..b70058caee50 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -172,7 +172,7 @@ static void iproc_gpio_irq_handler(struct irq_desc *desc) for_each_set_bit(bit, &val, NGPIOS_PER_BANK) { unsigned pin = NGPIOS_PER_BANK * i + bit; - int child_irq = irq_find_mapping(gc->irqdomain, pin); + int child_irq = irq_find_mapping(gc->irq.domain, pin); /* * Clear the interrupt before invoking the @@ -311,7 +311,7 @@ static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset) if (!chip->pinmux_is_supported) return 0; - return pinctrl_request_gpio(gpio); + return pinctrl_gpio_request(gpio); } static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) @@ -322,7 +322,7 @@ static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) if (!chip->pinmux_is_supported) return; - pinctrl_free_gpio(gpio); + pinctrl_gpio_free(gpio); } static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 1cfe45fd391f..e67ae52023ad 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -275,23 +275,6 @@ static struct irq_chip nsp_gpio_irq_chip = { .irq_set_type = nsp_gpio_irq_set_type, }; -/* - * Request the nsp IOMUX pinmux controller to mux individual pins to GPIO - */ -static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset) -{ - unsigned gpio = gc->base + offset; - - return pinctrl_request_gpio(gpio); -} - -static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset) -{ - unsigned gpio = gc->base + offset; - - pinctrl_free_gpio(gpio); -} - static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) { struct nsp_gpio *chip = gpiochip_get_data(gc); @@ -670,8 +653,8 @@ static int nsp_gpio_probe(struct platform_device *pdev) gc->label = dev_name(dev); gc->parent = dev; gc->of_node = dev->of_node; - gc->request = nsp_gpio_request; - gc->free = nsp_gpio_free; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; gc->direction_input = nsp_gpio_direction_input; gc->direction_output = nsp_gpio_direction_output; gc->set = nsp_gpio_set; diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 56fbe4c3e800..4c8d5b23e4d0 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -733,14 +733,14 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, } /** - * pinctrl_request_gpio() - request a single pin to be used as GPIO + * pinctrl_gpio_request() - request a single pin to be used as GPIO * @gpio: the GPIO pin number from the GPIO subsystem number space * * This function should *ONLY* be used from gpiolib-based GPIO drivers, * as part of their gpio_request() semantics, platforms and individual drivers * shall *NOT* request GPIO pins to be muxed in. */ -int pinctrl_request_gpio(unsigned gpio) +int pinctrl_gpio_request(unsigned gpio) { struct pinctrl_dev *pctldev; struct pinctrl_gpio_range *range; @@ -765,17 +765,17 @@ int pinctrl_request_gpio(unsigned gpio) return ret; } -EXPORT_SYMBOL_GPL(pinctrl_request_gpio); +EXPORT_SYMBOL_GPL(pinctrl_gpio_request); /** - * pinctrl_free_gpio() - free control on a single pin, currently used as GPIO + * pinctrl_gpio_free() - free control on a single pin, currently used as GPIO * @gpio: the GPIO pin number from the GPIO subsystem number space * * This function should *ONLY* be used from gpiolib-based GPIO drivers, * as part of their gpio_free() semantics, platforms and individual drivers * shall *NOT* request GPIO pins to be muxed out. */ -void pinctrl_free_gpio(unsigned gpio) +void pinctrl_gpio_free(unsigned gpio) { struct pinctrl_dev *pctldev; struct pinctrl_gpio_range *range; @@ -795,7 +795,7 @@ void pinctrl_free_gpio(unsigned gpio) mutex_unlock(&pctldev->mutex); } -EXPORT_SYMBOL_GPL(pinctrl_free_gpio); +EXPORT_SYMBOL_GPL(pinctrl_gpio_free); static int pinctrl_gpio_direction(unsigned gpio, bool input) { diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 7880c3adc450..8cf2eba17c8c 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -154,7 +154,7 @@ struct pinctrl_setting { * or pin, and each of these will increment the @usecount. * @mux_owner: The name of device that called pinctrl_get(). * @mux_setting: The most recent selected mux setting for this pin, if any. - * @gpio_owner: If pinctrl_request_gpio() was called for this pin, this is + * @gpio_owner: If pinctrl_gpio_request() was called for this pin, this is * the name of the GPIO that "owns" this pin. */ struct pin_desc { diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 525a5ff5dcb4..19bb9a55a567 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Freescale pin control drivers obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index f30720a752f3..4aea1b8504f7 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -5,7 +5,8 @@ if (X86 || COMPILE_TEST) config PINCTRL_BAYTRAIL bool "Intel Baytrail GPIO pin control" - depends on GPIOLIB && ACPI + depends on ACPI + select GPIOLIB select GPIOLIB_IRQCHIP select PINMUX select PINCONF @@ -65,6 +66,14 @@ config PINCTRL_CANNONLAKE This pinctrl driver provides an interface that allows configuring of Intel Cannon Lake PCH pins and using them as GPIOs. +config PINCTRL_CEDARFORK + tristate "Intel Cedar Fork pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Cedar Fork PCH pins and using them as GPIOs. + config PINCTRL_DENVERTON tristate "Intel Denverton pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index c12874da5992..fadfe3ea2b04 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Intel pin control drivers obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o @@ -6,6 +7,7 @@ obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o +obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 0f3a02495aeb..9c1ca29c60b7 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1627,7 +1627,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) pending = readl(reg); raw_spin_unlock(&vg->lock); for_each_set_bit(pin, &pending, 32) { - virq = irq_find_mapping(vg->chip.irqdomain, base + pin); + virq = irq_find_mapping(vg->chip.irq.domain, base + pin); generic_handle_irq(virq); } } @@ -1660,7 +1660,7 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg) value = readl(reg); if (value & BYT_DIRECT_IRQ_EN) { - clear_bit(i, gc->irq_valid_mask); + clear_bit(i, gc->irq.valid_mask); dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i); } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { byt_gpio_clear_triggering(vg, i); @@ -1703,7 +1703,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) gc->can_sleep = false; gc->parent = &vg->pdev->dev; gc->ngpio = vg->soc_data->npins; - gc->irq_need_valid_mask = true; + gc->irq.need_valid_mask = true; #ifdef CONFIG_PM_SLEEP vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c new file mode 100644 index 000000000000..59216b0533d9 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c @@ -0,0 +1,375 @@ +/* + * Intel Cedar Fork PCH pinctrl/GPIO driver + * + * Copyright (C) 2017, Intel Corporation + * Author: Mika Westerberg <mika.westerberg@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/acpi.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define CDF_PAD_OWN 0x020 +#define CDF_PADCFGLOCK 0x0c0 +#define CDF_HOSTSW_OWN 0x120 +#define CDF_GPI_IS 0x200 +#define CDF_GPI_IE 0x230 + +#define CDF_GPP(r, s, e) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + } + +#define CDF_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = CDF_PAD_OWN, \ + .padcfglock_offset = CDF_PADCFGLOCK, \ + .hostown_offset = CDF_HOSTSW_OWN, \ + .is_offset = CDF_GPI_IS, \ + .ie_offset = CDF_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Cedar Fork PCH */ +static const struct pinctrl_pin_desc cdf_pins[] = { + /* WEST2 */ + PINCTRL_PIN(0, "GBE_SDP_TIMESYNC0_S2N"), + PINCTRL_PIN(1, "GBE_SDP_TIMESYNC1_S2N"), + PINCTRL_PIN(2, "GBE_SDP_TIMESYNC2_S2N"), + PINCTRL_PIN(3, "GBE_SDP_TIMESYNC3_S2N"), + PINCTRL_PIN(4, "GBE0_I2C_CLK"), + PINCTRL_PIN(5, "GBE0_I2C_DATA"), + PINCTRL_PIN(6, "GBE1_I2C_CLK"), + PINCTRL_PIN(7, "GBE1_I2C_DATA"), + PINCTRL_PIN(8, "GBE2_I2C_CLK"), + PINCTRL_PIN(9, "GBE2_I2C_DATA"), + PINCTRL_PIN(10, "GBE3_I2C_CLK"), + PINCTRL_PIN(11, "GBE3_I2C_DATA"), + PINCTRL_PIN(12, "GBE0_LED0"), + PINCTRL_PIN(13, "GBE0_LED1"), + PINCTRL_PIN(14, "GBE0_LED2"), + PINCTRL_PIN(15, "GBE1_LED0"), + PINCTRL_PIN(16, "GBE1_LED1"), + PINCTRL_PIN(17, "GBE1_LED2"), + PINCTRL_PIN(18, "GBE2_LED0"), + PINCTRL_PIN(19, "GBE2_LED1"), + PINCTRL_PIN(20, "GBE2_LED2"), + PINCTRL_PIN(21, "GBE3_LED0"), + PINCTRL_PIN(22, "GBE3_LED1"), + PINCTRL_PIN(23, "GBE3_LED2"), + /* WEST3 */ + PINCTRL_PIN(24, "NCSI_RXD0"), + PINCTRL_PIN(25, "NCSI_CLK_IN"), + PINCTRL_PIN(26, "NCSI_RXD1"), + PINCTRL_PIN(27, "NCSI_CRS_DV"), + PINCTRL_PIN(28, "NCSI_ARB_IN"), + PINCTRL_PIN(29, "NCSI_TX_EN"), + PINCTRL_PIN(30, "NCSI_TXD0"), + PINCTRL_PIN(31, "NCSI_TXD1"), + PINCTRL_PIN(32, "NCSI_ARB_OUT"), + PINCTRL_PIN(33, "GBE_SMB_CLK"), + PINCTRL_PIN(34, "GBE_SMB_DATA"), + PINCTRL_PIN(35, "GBE_SMB_ALRT_N"), + PINCTRL_PIN(36, "THERMTRIP_N"), + PINCTRL_PIN(37, "PCHHOT_N"), + PINCTRL_PIN(38, "ERROR0_N"), + PINCTRL_PIN(39, "ERROR1_N"), + PINCTRL_PIN(40, "ERROR2_N"), + PINCTRL_PIN(41, "MSMI_N"), + PINCTRL_PIN(42, "CATERR_N"), + PINCTRL_PIN(43, "MEMTRIP_N"), + PINCTRL_PIN(44, "UART0_RXD"), + PINCTRL_PIN(45, "UART0_TXD"), + PINCTRL_PIN(46, "UART1_RXD"), + PINCTRL_PIN(47, "UART1_TXD"), + /* WEST01 */ + PINCTRL_PIN(48, "GBE_GPIO13"), + PINCTRL_PIN(49, "AUX_PWR"), + PINCTRL_PIN(50, "CPU_GP_2"), + PINCTRL_PIN(51, "CPU_GP_3"), + PINCTRL_PIN(52, "FAN_PWM_0"), + PINCTRL_PIN(53, "FAN_PWM_1"), + PINCTRL_PIN(54, "FAN_PWM_2"), + PINCTRL_PIN(55, "FAN_PWM_3"), + PINCTRL_PIN(56, "FAN_TACH_0"), + PINCTRL_PIN(57, "FAN_TACH_1"), + PINCTRL_PIN(58, "FAN_TACH_2"), + PINCTRL_PIN(59, "FAN_TACH_3"), + PINCTRL_PIN(60, "ME_SMB0_CLK"), + PINCTRL_PIN(61, "ME_SMB0_DATA"), + PINCTRL_PIN(62, "ME_SMB0_ALRT_N"), + PINCTRL_PIN(63, "ME_SMB1_CLK"), + PINCTRL_PIN(64, "ME_SMB1_DATA"), + PINCTRL_PIN(65, "ME_SMB1_ALRT_N"), + PINCTRL_PIN(66, "ME_SMB2_CLK"), + PINCTRL_PIN(67, "ME_SMB2_DATA"), + PINCTRL_PIN(68, "ME_SMB2_ALRT_N"), + PINCTRL_PIN(69, "GBE_MNG_I2C_CLK"), + PINCTRL_PIN(70, "GBE_MNG_I2C_DATA"), + /* WEST5 */ + PINCTRL_PIN(71, "IE_UART_RXD"), + PINCTRL_PIN(72, "IE_UART_TXD"), + PINCTRL_PIN(73, "VPP_SMB_CLK"), + PINCTRL_PIN(74, "VPP_SMB_DATA"), + PINCTRL_PIN(75, "VPP_SMB_ALRT_N"), + PINCTRL_PIN(76, "PCIE_CLKREQ0_N"), + PINCTRL_PIN(77, "PCIE_CLKREQ1_N"), + PINCTRL_PIN(78, "PCIE_CLKREQ2_N"), + PINCTRL_PIN(79, "PCIE_CLKREQ3_N"), + PINCTRL_PIN(80, "PCIE_CLKREQ4_N"), + PINCTRL_PIN(81, "PCIE_CLKREQ5_N"), + PINCTRL_PIN(82, "PCIE_CLKREQ6_N"), + PINCTRL_PIN(83, "PCIE_CLKREQ7_N"), + PINCTRL_PIN(84, "PCIE_CLKREQ8_N"), + PINCTRL_PIN(85, "PCIE_CLKREQ9_N"), + PINCTRL_PIN(86, "FLEX_CLK_SE0"), + PINCTRL_PIN(87, "FLEX_CLK_SE1"), + PINCTRL_PIN(88, "FLEX_CLK1_50"), + PINCTRL_PIN(89, "FLEX_CLK2_50"), + PINCTRL_PIN(90, "FLEX_CLK_125"), + /* WESTC */ + PINCTRL_PIN(91, "TCK_PCH"), + PINCTRL_PIN(92, "JTAGX_PCH"), + PINCTRL_PIN(93, "TRST_N_PCH"), + PINCTRL_PIN(94, "TMS_PCH"), + PINCTRL_PIN(95, "TDI_PCH"), + PINCTRL_PIN(96, "TDO_PCH"), + /* WESTC_DFX */ + PINCTRL_PIN(97, "CX_PRDY_N"), + PINCTRL_PIN(98, "CX_PREQ_N"), + PINCTRL_PIN(99, "CPU_FBREAK_OUT_N"), + PINCTRL_PIN(100, "TRIGGER0_N"), + PINCTRL_PIN(101, "TRIGGER1_N"), + /* WESTA */ + PINCTRL_PIN(102, "DBG_PTI_CLK0"), + PINCTRL_PIN(103, "DBG_PTI_CLK3"), + PINCTRL_PIN(104, "DBG_PTI_DATA0"), + PINCTRL_PIN(105, "DBG_PTI_DATA1"), + PINCTRL_PIN(106, "DBG_PTI_DATA2"), + PINCTRL_PIN(107, "DBG_PTI_DATA3"), + PINCTRL_PIN(108, "DBG_PTI_DATA4"), + PINCTRL_PIN(109, "DBG_PTI_DATA5"), + PINCTRL_PIN(110, "DBG_PTI_DATA6"), + PINCTRL_PIN(111, "DBG_PTI_DATA7"), + /* WESTB */ + PINCTRL_PIN(112, "DBG_PTI_DATA8"), + PINCTRL_PIN(113, "DBG_PTI_DATA9"), + PINCTRL_PIN(114, "DBG_PTI_DATA10"), + PINCTRL_PIN(115, "DBG_PTI_DATA11"), + PINCTRL_PIN(116, "DBG_PTI_DATA12"), + PINCTRL_PIN(117, "DBG_PTI_DATA13"), + PINCTRL_PIN(118, "DBG_PTI_DATA14"), + PINCTRL_PIN(119, "DBG_PTI_DATA15"), + PINCTRL_PIN(120, "DBG_SPARE0"), + PINCTRL_PIN(121, "DBG_SPARE1"), + PINCTRL_PIN(122, "DBG_SPARE2"), + PINCTRL_PIN(123, "DBG_SPARE3"), + /* WESTD */ + PINCTRL_PIN(124, "CPU_PWR_GOOD"), + PINCTRL_PIN(125, "PLTRST_CPU_N"), + PINCTRL_PIN(126, "NAC_RESET_NAC_N"), + PINCTRL_PIN(127, "PCH_SBLINK_RX"), + PINCTRL_PIN(128, "PCH_SBLINK_TX"), + PINCTRL_PIN(129, "PMSYNC_CLK"), + PINCTRL_PIN(130, "CPU_ERR0_N"), + PINCTRL_PIN(131, "CPU_ERR1_N"), + PINCTRL_PIN(132, "CPU_ERR2_N"), + PINCTRL_PIN(133, "CPU_THERMTRIP_N"), + PINCTRL_PIN(134, "CPU_MSMI_N"), + PINCTRL_PIN(135, "CPU_CATERR_N"), + PINCTRL_PIN(136, "CPU_MEMTRIP_N"), + PINCTRL_PIN(137, "NAC_GR_N"), + PINCTRL_PIN(138, "NAC_XTAL_VALID"), + PINCTRL_PIN(139, "NAC_WAKE_N"), + PINCTRL_PIN(140, "NAC_SBLINK_CLK_S2N"), + PINCTRL_PIN(141, "NAC_SBLINK_N2S"), + PINCTRL_PIN(142, "NAC_SBLINK_S2N"), + PINCTRL_PIN(143, "NAC_SBLINK_CLK_N2S"), + /* WESTD_PECI */ + PINCTRL_PIN(144, "ME_PECI"), + /* WESTF */ + PINCTRL_PIN(145, "NAC_RMII_CLK"), + PINCTRL_PIN(146, "NAC_RGMII_CLK"), + PINCTRL_PIN(147, "NAC_SPARE0"), + PINCTRL_PIN(148, "NAC_SPARE1"), + PINCTRL_PIN(149, "NAC_SPARE2"), + PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"), + PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"), + PINCTRL_PIN(152, "NAC_GBE_GPIO1_S2N"), + PINCTRL_PIN(153, "NAC_GBE_GPIO2_S2N"), + PINCTRL_PIN(154, "NAC_GBE_GPIO3_S2N"), + PINCTRL_PIN(155, "NAC_NCSI_RXD0"), + PINCTRL_PIN(156, "NAC_NCSI_CLK_IN"), + PINCTRL_PIN(157, "NAC_NCSI_RXD1"), + PINCTRL_PIN(158, "NAC_NCSI_CRS_DV"), + PINCTRL_PIN(159, "NAC_NCSI_ARB_IN"), + PINCTRL_PIN(160, "NAC_NCSI_TX_EN"), + PINCTRL_PIN(161, "NAC_NCSI_TXD0"), + PINCTRL_PIN(162, "NAC_NCSI_TXD1"), + PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"), + PINCTRL_PIN(164, "NAC_NCSI_OE_N"), + PINCTRL_PIN(165, "NAC_GBE_SMB_CLK"), + PINCTRL_PIN(166, "NAC_GBE_SMB_DATA"), + PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"), + /* EAST2 */ + PINCTRL_PIN(168, "USB_OC0_N"), + PINCTRL_PIN(169, "GBE_GPIO0"), + PINCTRL_PIN(170, "GBE_GPIO1"), + PINCTRL_PIN(171, "GBE_GPIO2"), + PINCTRL_PIN(172, "GBE_GPIO3"), + PINCTRL_PIN(173, "GBE_GPIO4"), + PINCTRL_PIN(174, "GBE_GPIO5"), + PINCTRL_PIN(175, "GBE_GPIO6"), + PINCTRL_PIN(176, "GBE_GPIO7"), + PINCTRL_PIN(177, "GBE_GPIO8"), + PINCTRL_PIN(178, "GBE_GPIO9"), + PINCTRL_PIN(179, "GBE_GPIO10"), + PINCTRL_PIN(180, "GBE_GPIO11"), + PINCTRL_PIN(181, "GBE_GPIO12"), + PINCTRL_PIN(182, "SATA0_LED_N"), + PINCTRL_PIN(183, "SATA1_LED_N"), + PINCTRL_PIN(184, "SATA_PDETECT0"), + PINCTRL_PIN(185, "SATA_PDETECT1"), + PINCTRL_PIN(186, "SATA0_SDOUT"), + PINCTRL_PIN(187, "SATA1_SDOUT"), + PINCTRL_PIN(188, "SATA2_LED_N"), + PINCTRL_PIN(189, "SATA_PDETECT2"), + PINCTRL_PIN(190, "SATA2_SDOUT"), + /* EAST3 */ + PINCTRL_PIN(191, "ESPI_IO0"), + PINCTRL_PIN(192, "ESPI_IO1"), + PINCTRL_PIN(193, "ESPI_IO2"), + PINCTRL_PIN(194, "ESPI_IO3"), + PINCTRL_PIN(195, "ESPI_CLK"), + PINCTRL_PIN(196, "ESPI_RST_N"), + PINCTRL_PIN(197, "ESPI_CS0_N"), + PINCTRL_PIN(198, "ESPI_ALRT0_N"), + PINCTRL_PIN(199, "ESPI_CS1_N"), + PINCTRL_PIN(200, "ESPI_ALRT1_N"), + PINCTRL_PIN(201, "ESPI_CLK_LOOPBK"), + /* EAST0 */ + PINCTRL_PIN(202, "SPI_CS0_N"), + PINCTRL_PIN(203, "SPI_CS1_N"), + PINCTRL_PIN(204, "SPI_MOSI_IO0"), + PINCTRL_PIN(205, "SPI_MISO_IO1"), + PINCTRL_PIN(206, "SPI_IO2"), + PINCTRL_PIN(207, "SPI_IO3"), + PINCTRL_PIN(208, "SPI_CLK"), + PINCTRL_PIN(209, "SPI_CLK_LOOPBK"), + PINCTRL_PIN(210, "SUSPWRDNACK"), + PINCTRL_PIN(211, "PMU_SUSCLK"), + PINCTRL_PIN(212, "ADR_COMPLETE"), + PINCTRL_PIN(213, "ADR_TRIGGER_N"), + PINCTRL_PIN(214, "PMU_SLP_S45_N"), + PINCTRL_PIN(215, "PMU_SLP_S3_N"), + PINCTRL_PIN(216, "PMU_WAKE_N"), + PINCTRL_PIN(217, "PMU_PWRBTN_N"), + PINCTRL_PIN(218, "PMU_RESETBUTTON_N"), + PINCTRL_PIN(219, "PMU_PLTRST_N"), + PINCTRL_PIN(220, "SUS_STAT_N"), + PINCTRL_PIN(221, "PMU_I2C_CLK"), + PINCTRL_PIN(222, "PMU_I2C_DATA"), + PINCTRL_PIN(223, "PECI_SMB_CLK"), + PINCTRL_PIN(224, "PECI_SMB_DATA"), + PINCTRL_PIN(225, "PECI_SMB_ALRT_N"), + /* EMMC */ + PINCTRL_PIN(226, "EMMC_CMD"), + PINCTRL_PIN(227, "EMMC_STROBE"), + PINCTRL_PIN(228, "EMMC_CLK"), + PINCTRL_PIN(229, "EMMC_D0"), + PINCTRL_PIN(230, "EMMC_D1"), + PINCTRL_PIN(231, "EMMC_D2"), + PINCTRL_PIN(232, "EMMC_D3"), + PINCTRL_PIN(233, "EMMC_D4"), + PINCTRL_PIN(234, "EMMC_D5"), + PINCTRL_PIN(235, "EMMC_D6"), + PINCTRL_PIN(236, "EMMC_D7"), +}; + +static const struct intel_padgroup cdf_community0_gpps[] = { + CDF_GPP(0, 0, 23), /* WEST2 */ + CDF_GPP(1, 24, 47), /* WEST3 */ + CDF_GPP(2, 48, 70), /* WEST01 */ + CDF_GPP(3, 71, 90), /* WEST5 */ + CDF_GPP(4, 91, 96), /* WESTC */ + CDF_GPP(5, 97, 101), /* WESTC_DFX */ + CDF_GPP(6, 102, 111), /* WESTA */ + CDF_GPP(7, 112, 123), /* WESTB */ + CDF_GPP(8, 124, 143), /* WESTD */ + CDF_GPP(9, 144, 144), /* WESTD_PECI */ + CDF_GPP(10, 145, 167), /* WESTF */ +}; + +static const struct intel_padgroup cdf_community1_gpps[] = { + CDF_GPP(0, 168, 190), /* EAST2 */ + CDF_GPP(1, 191, 201), /* EAST3 */ + CDF_GPP(2, 202, 225), /* EAST0 */ + CDF_GPP(3, 226, 236), /* EMMC */ +}; + +static const struct intel_community cdf_communities[] = { + CDF_COMMUNITY(0, 0, 167, cdf_community0_gpps), /* West */ + CDF_COMMUNITY(1, 168, 236, cdf_community1_gpps), /* East */ +}; + +static const struct intel_pinctrl_soc_data cdf_soc_data = { + .pins = cdf_pins, + .npins = ARRAY_SIZE(cdf_pins), + .communities = cdf_communities, + .ncommunities = ARRAY_SIZE(cdf_communities), +}; + +static int cdf_pinctrl_probe(struct platform_device *pdev) +{ + return intel_pinctrl_probe(pdev, &cdf_soc_data); +} + +static const struct dev_pm_ops cdf_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, + intel_pinctrl_resume) +}; + +static const struct acpi_device_id cdf_pinctrl_acpi_match[] = { + { "INTC3001" }, + { } +}; +MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match); + +static struct platform_driver cdf_pinctrl_driver = { + .probe = cdf_pinctrl_probe, + .driver = { + .name = "cedarfork-pinctrl", + .acpi_match_table = cdf_pinctrl_acpi_match, + .pm = &cdf_pinctrl_pm_ops, + }, +}; + +static int __init cdf_pinctrl_init(void) +{ + return platform_driver_register(&cdf_pinctrl_driver); +} +subsys_initcall(cdf_pinctrl_init); + +static void __exit cdf_pinctrl_exit(void) +{ + platform_driver_unregister(&cdf_pinctrl_driver); +} +module_exit(cdf_pinctrl_exit); + +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 04e929fd0ffe..bdedb6325c72 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -491,7 +491,7 @@ static const struct chv_community north_community = { .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), .ngpios = ARRAY_SIZE(north_pins), /* - * North community can benerate GPIO interrupts only for the first + * North community can generate GPIO interrupts only for the first * 8 interrupts. The upper half (8-15) can only be used to trigger * GPEs. */ @@ -1523,7 +1523,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) unsigned irq, offset; offset = pctrl->intr_lines[intr_line]; - irq = irq_find_mapping(gc->irqdomain, offset); + irq = irq_find_mapping(gc->irq.domain, offset); generic_handle_irq(irq); } @@ -1577,6 +1577,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) struct gpio_chip *chip = &pctrl->chip; bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); int ret, i, offset; + int irq_base; *chip = chv_gpio_chip; @@ -1584,7 +1585,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) chip->label = dev_name(pctrl->dev); chip->parent = pctrl->dev; chip->base = -1; - chip->irq_need_valid_mask = need_valid_mask; + chip->irq.need_valid_mask = need_valid_mask; ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); if (ret) { @@ -1616,13 +1617,24 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; if (need_valid_mask && intsel >= pctrl->community->nirqs) - clear_bit(i, chip->irq_valid_mask); + clear_bit(i, chip->irq.valid_mask); } /* Clear all interrupts */ chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); - ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, + if (!need_valid_mask) { + irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, + chip->ngpio, NUMA_NO_NODE); + if (irq_base < 0) { + dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); + return irq_base; + } + } else { + irq_base = 0; + } + + ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, irq_base, handle_bad_irq, IRQ_TYPE_NONE); if (ret) { dev_err(pctrl->dev, "failed to add IRQ chip\n"); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 71df0f70b61f..12a1af45acb9 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -30,8 +30,6 @@ #define PADBAR 0x00c #define GPI_IS 0x100 -#define GPI_GPE_STS 0x140 -#define GPI_GPE_EN 0x160 #define PADOWN_BITS 4 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) @@ -818,7 +816,7 @@ static void intel_gpio_irq_ack(struct irq_data *d) community = intel_get_community(pctrl, pin); if (community) { const struct intel_padgroup *padgrp; - unsigned gpp, gpp_offset; + unsigned gpp, gpp_offset, is_offset; padgrp = intel_community_get_padgroup(community, pin); if (!padgrp) @@ -826,9 +824,10 @@ static void intel_gpio_irq_ack(struct irq_data *d) gpp = padgrp->reg_num; gpp_offset = padgroup_offset(padgrp, pin); + is_offset = community->is_offset + gpp * 4; raw_spin_lock(&pctrl->lock); - writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); + writel(BIT(gpp_offset), community->regs + is_offset); raw_spin_unlock(&pctrl->lock); } } @@ -843,7 +842,7 @@ static void intel_gpio_irq_enable(struct irq_data *d) community = intel_get_community(pctrl, pin); if (community) { const struct intel_padgroup *padgrp; - unsigned gpp, gpp_offset; + unsigned gpp, gpp_offset, is_offset; unsigned long flags; u32 value; @@ -853,10 +852,11 @@ static void intel_gpio_irq_enable(struct irq_data *d) gpp = padgrp->reg_num; gpp_offset = padgroup_offset(padgrp, pin); + is_offset = community->is_offset + gpp * 4; raw_spin_lock_irqsave(&pctrl->lock, flags); /* Clear interrupt status first to avoid unexpected interrupt */ - writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); + writel(BIT(gpp_offset), community->regs + is_offset); value = readl(community->regs + community->ie_offset + gpp * 4); value |= BIT(gpp_offset); @@ -991,7 +991,8 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, const struct intel_padgroup *padgrp = &community->gpps[gpp]; unsigned long pending, enabled, gpp_offset; - pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4); + pending = readl(community->regs + community->is_offset + + padgrp->reg_num * 4); enabled = readl(community->regs + community->ie_offset + padgrp->reg_num * 4); @@ -1005,7 +1006,7 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, if (padno >= community->npins) break; - irq = irq_find_mapping(gc->irqdomain, + irq = irq_find_mapping(gc->irq.domain, community->pin_base + padno); generic_handle_irq(irq); @@ -1241,6 +1242,9 @@ int intel_pinctrl_probe(struct platform_device *pdev, community->regs = regs; community->pad_regs = regs + padbar; + if (!community->is_offset) + community->is_offset = GPI_IS; + ret = intel_pinctrl_add_padgroups(pctrl, community); if (ret) return ret; @@ -1356,7 +1360,7 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) for (gpp = 0; gpp < community->ngpps; gpp++) { /* Mask and clear all interrupts */ writel(0, base + community->ie_offset + gpp * 4); - writel(0xffff, base + GPI_IS + gpp * 4); + writel(0xffff, base + community->is_offset + gpp * 4); } } } diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 7fdb07753c2d..13b0bd6eb2a2 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -73,6 +73,8 @@ struct intel_padgroup { * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it * is assumed that the host owns the pin (rather than * ACPI). + * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the + * default (%0x100). * @ie_offset: Register offset of GPI_IE from @regs. * @pin_base: Starting pin of pins in this community * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, @@ -98,6 +100,7 @@ struct intel_community { unsigned padown_offset; unsigned padcfglock_offset; unsigned hostown_offset; + unsigned is_offset; unsigned ie_offset; unsigned pin_base; unsigned gpp_size; diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index e59c613d4ddd..10d90140a38a 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Core obj-y += pinctrl-mtk-common.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h index 4eb98ddb40a4..17df4cfbde4e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __PINCTRL_MTK_MT6397_H #define __PINCTRL_MTK_MT6397_H diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h index 212559c147f8..850483d7d9be 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __PINCTRL_MTK_MT8127_H #define __PINCTRL_MTK_MT8127_H diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig new file mode 100644 index 000000000000..1a51778759ea --- /dev/null +++ b/drivers/pinctrl/meson/Kconfig @@ -0,0 +1,41 @@ +menuconfig PINCTRL_MESON + bool "Amlogic SoC pinctrl drivers" + depends on ARCH_MESON + depends on OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select OF_GPIO + select REGMAP_MMIO + +if PINCTRL_MESON + +config PINCTRL_MESON8 + bool "Meson 8 SoC pinctrl driver" + depends on ARM + select PINCTRL_MESON8_PMX + default y + +config PINCTRL_MESON8B + bool "Meson 8b SoC pinctrl driver" + depends on ARM + select PINCTRL_MESON8_PMX + default y + +config PINCTRL_MESON_GXBB + bool "Meson gxbb SoC pinctrl driver" + depends on ARM64 + select PINCTRL_MESON8_PMX + default y + +config PINCTRL_MESON_GXL + bool "Meson gxl SoC pinctrl driver" + depends on ARM64 + select PINCTRL_MESON8_PMX + default y + +config PINCTRL_MESON8_PMX + bool + +endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 27c5b5126008..cbd47bb74549 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -1,3 +1,6 @@ -obj-y += pinctrl-meson8.o pinctrl-meson8b.o -obj-y += pinctrl-meson-gxbb.o pinctrl-meson-gxl.o -obj-y += pinctrl-meson.o +obj-$(CONFIG_PINCTRL_MESON) += pinctrl-meson.o +obj-$(CONFIG_PINCTRL_MESON8_PMX) += pinctrl-meson8-pmx.o +obj-$(CONFIG_PINCTRL_MESON8) += pinctrl-meson8.o +obj-$(CONFIG_PINCTRL_MESON8B) += pinctrl-meson8b.o +obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o +obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 7bbc0d3cddcf..9079020259c5 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -14,418 +14,417 @@ #include <dt-bindings/gpio/meson-gxbb-gpio.h> #include "pinctrl-meson.h" - -#define EE_OFF 14 +#include "pinctrl-meson8-pmx.h" static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = { - MESON_PIN(GPIOZ_0, EE_OFF), - MESON_PIN(GPIOZ_1, EE_OFF), - MESON_PIN(GPIOZ_2, EE_OFF), - MESON_PIN(GPIOZ_3, EE_OFF), - MESON_PIN(GPIOZ_4, EE_OFF), - MESON_PIN(GPIOZ_5, EE_OFF), - MESON_PIN(GPIOZ_6, EE_OFF), - MESON_PIN(GPIOZ_7, EE_OFF), - MESON_PIN(GPIOZ_8, EE_OFF), - MESON_PIN(GPIOZ_9, EE_OFF), - MESON_PIN(GPIOZ_10, EE_OFF), - MESON_PIN(GPIOZ_11, EE_OFF), - MESON_PIN(GPIOZ_12, EE_OFF), - MESON_PIN(GPIOZ_13, EE_OFF), - MESON_PIN(GPIOZ_14, EE_OFF), - MESON_PIN(GPIOZ_15, EE_OFF), - - MESON_PIN(GPIOH_0, EE_OFF), - MESON_PIN(GPIOH_1, EE_OFF), - MESON_PIN(GPIOH_2, EE_OFF), - MESON_PIN(GPIOH_3, EE_OFF), - - MESON_PIN(BOOT_0, EE_OFF), - MESON_PIN(BOOT_1, EE_OFF), - MESON_PIN(BOOT_2, EE_OFF), - MESON_PIN(BOOT_3, EE_OFF), - MESON_PIN(BOOT_4, EE_OFF), - MESON_PIN(BOOT_5, EE_OFF), - MESON_PIN(BOOT_6, EE_OFF), - MESON_PIN(BOOT_7, EE_OFF), - MESON_PIN(BOOT_8, EE_OFF), - MESON_PIN(BOOT_9, EE_OFF), - MESON_PIN(BOOT_10, EE_OFF), - MESON_PIN(BOOT_11, EE_OFF), - MESON_PIN(BOOT_12, EE_OFF), - MESON_PIN(BOOT_13, EE_OFF), - MESON_PIN(BOOT_14, EE_OFF), - MESON_PIN(BOOT_15, EE_OFF), - MESON_PIN(BOOT_16, EE_OFF), - MESON_PIN(BOOT_17, EE_OFF), - - MESON_PIN(CARD_0, EE_OFF), - MESON_PIN(CARD_1, EE_OFF), - MESON_PIN(CARD_2, EE_OFF), - MESON_PIN(CARD_3, EE_OFF), - MESON_PIN(CARD_4, EE_OFF), - MESON_PIN(CARD_5, EE_OFF), - MESON_PIN(CARD_6, EE_OFF), - - MESON_PIN(GPIODV_0, EE_OFF), - MESON_PIN(GPIODV_1, EE_OFF), - MESON_PIN(GPIODV_2, EE_OFF), - MESON_PIN(GPIODV_3, EE_OFF), - MESON_PIN(GPIODV_4, EE_OFF), - MESON_PIN(GPIODV_5, EE_OFF), - MESON_PIN(GPIODV_6, EE_OFF), - MESON_PIN(GPIODV_7, EE_OFF), - MESON_PIN(GPIODV_8, EE_OFF), - MESON_PIN(GPIODV_9, EE_OFF), - MESON_PIN(GPIODV_10, EE_OFF), - MESON_PIN(GPIODV_11, EE_OFF), - MESON_PIN(GPIODV_12, EE_OFF), - MESON_PIN(GPIODV_13, EE_OFF), - MESON_PIN(GPIODV_14, EE_OFF), - MESON_PIN(GPIODV_15, EE_OFF), - MESON_PIN(GPIODV_16, EE_OFF), - MESON_PIN(GPIODV_17, EE_OFF), - MESON_PIN(GPIODV_18, EE_OFF), - MESON_PIN(GPIODV_19, EE_OFF), - MESON_PIN(GPIODV_20, EE_OFF), - MESON_PIN(GPIODV_21, EE_OFF), - MESON_PIN(GPIODV_22, EE_OFF), - MESON_PIN(GPIODV_23, EE_OFF), - MESON_PIN(GPIODV_24, EE_OFF), - MESON_PIN(GPIODV_25, EE_OFF), - MESON_PIN(GPIODV_26, EE_OFF), - MESON_PIN(GPIODV_27, EE_OFF), - MESON_PIN(GPIODV_28, EE_OFF), - MESON_PIN(GPIODV_29, EE_OFF), - - MESON_PIN(GPIOY_0, EE_OFF), - MESON_PIN(GPIOY_1, EE_OFF), - MESON_PIN(GPIOY_2, EE_OFF), - MESON_PIN(GPIOY_3, EE_OFF), - MESON_PIN(GPIOY_4, EE_OFF), - MESON_PIN(GPIOY_5, EE_OFF), - MESON_PIN(GPIOY_6, EE_OFF), - MESON_PIN(GPIOY_7, EE_OFF), - MESON_PIN(GPIOY_8, EE_OFF), - MESON_PIN(GPIOY_9, EE_OFF), - MESON_PIN(GPIOY_10, EE_OFF), - MESON_PIN(GPIOY_11, EE_OFF), - MESON_PIN(GPIOY_12, EE_OFF), - MESON_PIN(GPIOY_13, EE_OFF), - MESON_PIN(GPIOY_14, EE_OFF), - MESON_PIN(GPIOY_15, EE_OFF), - MESON_PIN(GPIOY_16, EE_OFF), - - MESON_PIN(GPIOX_0, EE_OFF), - MESON_PIN(GPIOX_1, EE_OFF), - MESON_PIN(GPIOX_2, EE_OFF), - MESON_PIN(GPIOX_3, EE_OFF), - MESON_PIN(GPIOX_4, EE_OFF), - MESON_PIN(GPIOX_5, EE_OFF), - MESON_PIN(GPIOX_6, EE_OFF), - MESON_PIN(GPIOX_7, EE_OFF), - MESON_PIN(GPIOX_8, EE_OFF), - MESON_PIN(GPIOX_9, EE_OFF), - MESON_PIN(GPIOX_10, EE_OFF), - MESON_PIN(GPIOX_11, EE_OFF), - MESON_PIN(GPIOX_12, EE_OFF), - MESON_PIN(GPIOX_13, EE_OFF), - MESON_PIN(GPIOX_14, EE_OFF), - MESON_PIN(GPIOX_15, EE_OFF), - MESON_PIN(GPIOX_16, EE_OFF), - MESON_PIN(GPIOX_17, EE_OFF), - MESON_PIN(GPIOX_18, EE_OFF), - MESON_PIN(GPIOX_19, EE_OFF), - MESON_PIN(GPIOX_20, EE_OFF), - MESON_PIN(GPIOX_21, EE_OFF), - - MESON_PIN(GPIOCLK_0, EE_OFF), - MESON_PIN(GPIOCLK_1, EE_OFF), - MESON_PIN(GPIOCLK_2, EE_OFF), - MESON_PIN(GPIOCLK_3, EE_OFF), - - MESON_PIN(GPIO_TEST_N, EE_OFF), + MESON_PIN(GPIOZ_0), + MESON_PIN(GPIOZ_1), + MESON_PIN(GPIOZ_2), + MESON_PIN(GPIOZ_3), + MESON_PIN(GPIOZ_4), + MESON_PIN(GPIOZ_5), + MESON_PIN(GPIOZ_6), + MESON_PIN(GPIOZ_7), + MESON_PIN(GPIOZ_8), + MESON_PIN(GPIOZ_9), + MESON_PIN(GPIOZ_10), + MESON_PIN(GPIOZ_11), + MESON_PIN(GPIOZ_12), + MESON_PIN(GPIOZ_13), + MESON_PIN(GPIOZ_14), + MESON_PIN(GPIOZ_15), + + MESON_PIN(GPIOH_0), + MESON_PIN(GPIOH_1), + MESON_PIN(GPIOH_2), + MESON_PIN(GPIOH_3), + + MESON_PIN(BOOT_0), + MESON_PIN(BOOT_1), + MESON_PIN(BOOT_2), + MESON_PIN(BOOT_3), + MESON_PIN(BOOT_4), + MESON_PIN(BOOT_5), + MESON_PIN(BOOT_6), + MESON_PIN(BOOT_7), + MESON_PIN(BOOT_8), + MESON_PIN(BOOT_9), + MESON_PIN(BOOT_10), + MESON_PIN(BOOT_11), + MESON_PIN(BOOT_12), + MESON_PIN(BOOT_13), + MESON_PIN(BOOT_14), + MESON_PIN(BOOT_15), + MESON_PIN(BOOT_16), + MESON_PIN(BOOT_17), + + MESON_PIN(CARD_0), + MESON_PIN(CARD_1), + MESON_PIN(CARD_2), + MESON_PIN(CARD_3), + MESON_PIN(CARD_4), + MESON_PIN(CARD_5), + MESON_PIN(CARD_6), + + MESON_PIN(GPIODV_0), + MESON_PIN(GPIODV_1), + MESON_PIN(GPIODV_2), + MESON_PIN(GPIODV_3), + MESON_PIN(GPIODV_4), + MESON_PIN(GPIODV_5), + MESON_PIN(GPIODV_6), + MESON_PIN(GPIODV_7), + MESON_PIN(GPIODV_8), + MESON_PIN(GPIODV_9), + MESON_PIN(GPIODV_10), + MESON_PIN(GPIODV_11), + MESON_PIN(GPIODV_12), + MESON_PIN(GPIODV_13), + MESON_PIN(GPIODV_14), + MESON_PIN(GPIODV_15), + MESON_PIN(GPIODV_16), + MESON_PIN(GPIODV_17), + MESON_PIN(GPIODV_18), + MESON_PIN(GPIODV_19), + MESON_PIN(GPIODV_20), + MESON_PIN(GPIODV_21), + MESON_PIN(GPIODV_22), + MESON_PIN(GPIODV_23), + MESON_PIN(GPIODV_24), + MESON_PIN(GPIODV_25), + MESON_PIN(GPIODV_26), + MESON_PIN(GPIODV_27), + MESON_PIN(GPIODV_28), + MESON_PIN(GPIODV_29), + + MESON_PIN(GPIOY_0), + MESON_PIN(GPIOY_1), + MESON_PIN(GPIOY_2), + MESON_PIN(GPIOY_3), + MESON_PIN(GPIOY_4), + MESON_PIN(GPIOY_5), + MESON_PIN(GPIOY_6), + MESON_PIN(GPIOY_7), + MESON_PIN(GPIOY_8), + MESON_PIN(GPIOY_9), + MESON_PIN(GPIOY_10), + MESON_PIN(GPIOY_11), + MESON_PIN(GPIOY_12), + MESON_PIN(GPIOY_13), + MESON_PIN(GPIOY_14), + MESON_PIN(GPIOY_15), + MESON_PIN(GPIOY_16), + + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOX_14), + MESON_PIN(GPIOX_15), + MESON_PIN(GPIOX_16), + MESON_PIN(GPIOX_17), + MESON_PIN(GPIOX_18), + MESON_PIN(GPIOX_19), + MESON_PIN(GPIOX_20), + MESON_PIN(GPIOX_21), + MESON_PIN(GPIOX_22), + + MESON_PIN(GPIOCLK_0), + MESON_PIN(GPIOCLK_1), + MESON_PIN(GPIOCLK_2), + MESON_PIN(GPIOCLK_3), }; static const unsigned int emmc_nand_d07_pins[] = { - PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF), - PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF), - PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF), -}; -static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) }; -static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) }; -static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) }; - -static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) }; -static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; -static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; -static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; - -static const unsigned int spi_sclk_pins[] = { PIN(GPIOZ_6, EE_OFF) }; -static const unsigned int spi_ss0_pins[] = { PIN(GPIOZ_7, EE_OFF) }; -static const unsigned int spi_miso_pins[] = { PIN(GPIOZ_12, EE_OFF) }; -static const unsigned int spi_mosi_pins[] = { PIN(GPIOZ_13, EE_OFF) }; - -static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; -static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; -static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; -static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) }; -static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) }; -static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) }; - -static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) }; -static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) }; -static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) }; -static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) }; -static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; -static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; -static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; - -static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; -static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; -static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; -static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; -static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; -static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; -static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) }; -static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) }; - -static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; -static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; -static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; -static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) }; - -static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) }; -static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) }; -static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; -static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; - -static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_13, EE_OFF) }; -static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_14, EE_OFF) }; -static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_11, EE_OFF) }; -static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_12, EE_OFF) }; - -static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) }; -static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) }; - -static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; -static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; - -static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) }; -static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) }; - -static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) }; -static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) }; -static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) }; -static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) }; -static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) }; -static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) }; -static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) }; -static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) }; -static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) }; -static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) }; -static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) }; -static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) }; -static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) }; -static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) }; - -static const unsigned int pwm_a_x_pins[] = { PIN(GPIOX_6, EE_OFF) }; -static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, EE_OFF) }; -static const unsigned int pwm_b_pins[] = { PIN(GPIODV_29, EE_OFF) }; -static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) }; -static const unsigned int pwm_e_pins[] = { PIN(GPIOX_19, EE_OFF) }; -static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) }; -static const unsigned int pwm_f_y_pins[] = { PIN(GPIOY_15, EE_OFF) }; - -static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; -static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; -static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; - -static const unsigned int i2s_out_ch23_y_pins[] = { PIN(GPIOY_8, EE_OFF) }; -static const unsigned int i2s_out_ch45_y_pins[] = { PIN(GPIOY_9, EE_OFF) }; -static const unsigned int i2s_out_ch67_y_pins[] = { PIN(GPIOY_10, EE_OFF) }; - -static const unsigned int spdif_out_y_pins[] = { PIN(GPIOY_12, EE_OFF) }; + BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7, +}; +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; +static const unsigned int emmc_ds_pins[] = { BOOT_15 }; + +static const unsigned int nor_d_pins[] = { BOOT_11 }; +static const unsigned int nor_q_pins[] = { BOOT_12 }; +static const unsigned int nor_c_pins[] = { BOOT_13 }; +static const unsigned int nor_cs_pins[] = { BOOT_15 }; + +static const unsigned int spi_sclk_pins[] = { GPIOZ_6 }; +static const unsigned int spi_ss0_pins[] = { GPIOZ_7 }; +static const unsigned int spi_miso_pins[] = { GPIOZ_12 }; +static const unsigned int spi_mosi_pins[] = { GPIOZ_13 }; + +static const unsigned int sdcard_d0_pins[] = { CARD_1 }; +static const unsigned int sdcard_d1_pins[] = { CARD_0 }; +static const unsigned int sdcard_d2_pins[] = { CARD_5 }; +static const unsigned int sdcard_d3_pins[] = { CARD_4 }; +static const unsigned int sdcard_cmd_pins[] = { CARD_3 }; +static const unsigned int sdcard_clk_pins[] = { CARD_2 }; + +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; +static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; + +static const unsigned int nand_ce0_pins[] = { BOOT_8 }; +static const unsigned int nand_ce1_pins[] = { BOOT_9 }; +static const unsigned int nand_rb0_pins[] = { BOOT_10 }; +static const unsigned int nand_ale_pins[] = { BOOT_11 }; +static const unsigned int nand_cle_pins[] = { BOOT_12 }; +static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; +static const unsigned int nand_ren_wr_pins[] = { BOOT_14 }; +static const unsigned int nand_dqs_pins[] = { BOOT_15 }; + +static const unsigned int uart_tx_a_pins[] = { GPIOX_12 }; +static const unsigned int uart_rx_a_pins[] = { GPIOX_13 }; +static const unsigned int uart_cts_a_pins[] = { GPIOX_14 }; +static const unsigned int uart_rts_a_pins[] = { GPIOX_15 }; + +static const unsigned int uart_tx_b_pins[] = { GPIODV_24 }; +static const unsigned int uart_rx_b_pins[] = { GPIODV_25 }; +static const unsigned int uart_cts_b_pins[] = { GPIODV_26 }; +static const unsigned int uart_rts_b_pins[] = { GPIODV_27 }; + +static const unsigned int uart_tx_c_pins[] = { GPIOY_13 }; +static const unsigned int uart_rx_c_pins[] = { GPIOY_14 }; +static const unsigned int uart_cts_c_pins[] = { GPIOX_11 }; +static const unsigned int uart_rts_c_pins[] = { GPIOX_12 }; + +static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; +static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; + +static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 }; +static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 }; + +static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 }; +static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 }; + +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; +static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 }; +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; +static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 }; +static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 }; +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; +static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 }; +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; +static const unsigned int eth_txd2_pins[] = { GPIOZ_12 }; +static const unsigned int eth_txd3_pins[] = { GPIOZ_13 }; + +static const unsigned int pwm_a_x_pins[] = { GPIOX_6 }; +static const unsigned int pwm_a_y_pins[] = { GPIOY_16 }; +static const unsigned int pwm_b_pins[] = { GPIODV_29 }; +static const unsigned int pwm_d_pins[] = { GPIODV_28 }; +static const unsigned int pwm_e_pins[] = { GPIOX_19 }; +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; +static const unsigned int pwm_f_y_pins[] = { GPIOY_15 }; + +static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; +static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; +static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; + +static const unsigned int i2s_out_ch23_y_pins[] = { GPIOY_8 }; +static const unsigned int i2s_out_ch45_y_pins[] = { GPIOY_9 }; +static const unsigned int i2s_out_ch67_y_pins[] = { GPIOY_10 }; + +static const unsigned int spdif_out_y_pins[] = { GPIOY_12 }; static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = { - MESON_PIN(GPIOAO_0, 0), - MESON_PIN(GPIOAO_1, 0), - MESON_PIN(GPIOAO_2, 0), - MESON_PIN(GPIOAO_3, 0), - MESON_PIN(GPIOAO_4, 0), - MESON_PIN(GPIOAO_5, 0), - MESON_PIN(GPIOAO_6, 0), - MESON_PIN(GPIOAO_7, 0), - MESON_PIN(GPIOAO_8, 0), - MESON_PIN(GPIOAO_9, 0), - MESON_PIN(GPIOAO_10, 0), - MESON_PIN(GPIOAO_11, 0), - MESON_PIN(GPIOAO_12, 0), - MESON_PIN(GPIOAO_13, 0), -}; - -static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) }; -static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) }; -static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) }; -static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) }; -static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_4, 0) }; -static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_5, 0) }; -static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) }; -static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) }; - -static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; -static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; -static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; -static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; - -static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; - -static const unsigned int pwm_ao_a_3_pins[] = { PIN(GPIOAO_3, 0) }; -static const unsigned int pwm_ao_a_6_pins[] = { PIN(GPIOAO_6, 0) }; -static const unsigned int pwm_ao_a_12_pins[] = { PIN(GPIOAO_12, 0) }; -static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_13, 0) }; - -static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOAO_8, 0) }; -static const unsigned int i2s_out_ao_clk_pins[] = { PIN(GPIOAO_9, 0) }; -static const unsigned int i2s_out_lr_clk_pins[] = { PIN(GPIOAO_10, 0) }; -static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, 0) }; -static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_12, 0) }; -static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_13, 0) }; - -static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) }; -static const unsigned int spdif_out_ao_13_pins[] = { PIN(GPIOAO_13, 0) }; - -static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_12, 0) }; -static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_12, 0) }; + MESON_PIN(GPIOAO_0), + MESON_PIN(GPIOAO_1), + MESON_PIN(GPIOAO_2), + MESON_PIN(GPIOAO_3), + MESON_PIN(GPIOAO_4), + MESON_PIN(GPIOAO_5), + MESON_PIN(GPIOAO_6), + MESON_PIN(GPIOAO_7), + MESON_PIN(GPIOAO_8), + MESON_PIN(GPIOAO_9), + MESON_PIN(GPIOAO_10), + MESON_PIN(GPIOAO_11), + MESON_PIN(GPIOAO_12), + MESON_PIN(GPIOAO_13), + + MESON_PIN(GPIO_TEST_N), +}; + +static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; +static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; +static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; +static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; +static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 }; +static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 }; +static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 }; +static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 }; + +static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 }; +static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 }; +static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 }; +static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 }; + +static const unsigned int remote_input_ao_pins[] = { GPIOAO_7 }; + +static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 }; +static const unsigned int pwm_ao_a_6_pins[] = { GPIOAO_6 }; +static const unsigned int pwm_ao_a_12_pins[] = { GPIOAO_12 }; +static const unsigned int pwm_ao_b_pins[] = { GPIOAO_13 }; + +static const unsigned int i2s_am_clk_pins[] = { GPIOAO_8 }; +static const unsigned int i2s_out_ao_clk_pins[] = { GPIOAO_9 }; +static const unsigned int i2s_out_lr_clk_pins[] = { GPIOAO_10 }; +static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 }; +static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_12 }; +static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_13 }; +static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N }; + +static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 }; +static const unsigned int spdif_out_ao_13_pins[] = { GPIOAO_13 }; + +static const unsigned int ao_cec_pins[] = { GPIOAO_12 }; +static const unsigned int ee_cec_pins[] = { GPIOAO_12 }; static struct meson_pmx_group meson_gxbb_periphs_groups[] = { - GPIO_GROUP(GPIOZ_0, EE_OFF), - GPIO_GROUP(GPIOZ_1, EE_OFF), - GPIO_GROUP(GPIOZ_2, EE_OFF), - GPIO_GROUP(GPIOZ_3, EE_OFF), - GPIO_GROUP(GPIOZ_4, EE_OFF), - GPIO_GROUP(GPIOZ_5, EE_OFF), - GPIO_GROUP(GPIOZ_6, EE_OFF), - GPIO_GROUP(GPIOZ_7, EE_OFF), - GPIO_GROUP(GPIOZ_8, EE_OFF), - GPIO_GROUP(GPIOZ_9, EE_OFF), - GPIO_GROUP(GPIOZ_10, EE_OFF), - GPIO_GROUP(GPIOZ_11, EE_OFF), - GPIO_GROUP(GPIOZ_12, EE_OFF), - GPIO_GROUP(GPIOZ_13, EE_OFF), - GPIO_GROUP(GPIOZ_14, EE_OFF), - GPIO_GROUP(GPIOZ_15, EE_OFF), - - GPIO_GROUP(GPIOH_0, EE_OFF), - GPIO_GROUP(GPIOH_1, EE_OFF), - GPIO_GROUP(GPIOH_2, EE_OFF), - GPIO_GROUP(GPIOH_3, EE_OFF), - - GPIO_GROUP(BOOT_0, EE_OFF), - GPIO_GROUP(BOOT_1, EE_OFF), - GPIO_GROUP(BOOT_2, EE_OFF), - GPIO_GROUP(BOOT_3, EE_OFF), - GPIO_GROUP(BOOT_4, EE_OFF), - GPIO_GROUP(BOOT_5, EE_OFF), - GPIO_GROUP(BOOT_6, EE_OFF), - GPIO_GROUP(BOOT_7, EE_OFF), - GPIO_GROUP(BOOT_8, EE_OFF), - GPIO_GROUP(BOOT_9, EE_OFF), - GPIO_GROUP(BOOT_10, EE_OFF), - GPIO_GROUP(BOOT_11, EE_OFF), - GPIO_GROUP(BOOT_12, EE_OFF), - GPIO_GROUP(BOOT_13, EE_OFF), - GPIO_GROUP(BOOT_14, EE_OFF), - GPIO_GROUP(BOOT_15, EE_OFF), - GPIO_GROUP(BOOT_16, EE_OFF), - GPIO_GROUP(BOOT_17, EE_OFF), - - GPIO_GROUP(CARD_0, EE_OFF), - GPIO_GROUP(CARD_1, EE_OFF), - GPIO_GROUP(CARD_2, EE_OFF), - GPIO_GROUP(CARD_3, EE_OFF), - GPIO_GROUP(CARD_4, EE_OFF), - GPIO_GROUP(CARD_5, EE_OFF), - GPIO_GROUP(CARD_6, EE_OFF), - - GPIO_GROUP(GPIODV_0, EE_OFF), - GPIO_GROUP(GPIODV_1, EE_OFF), - GPIO_GROUP(GPIODV_2, EE_OFF), - GPIO_GROUP(GPIODV_3, EE_OFF), - GPIO_GROUP(GPIODV_4, EE_OFF), - GPIO_GROUP(GPIODV_5, EE_OFF), - GPIO_GROUP(GPIODV_6, EE_OFF), - GPIO_GROUP(GPIODV_7, EE_OFF), - GPIO_GROUP(GPIODV_8, EE_OFF), - GPIO_GROUP(GPIODV_9, EE_OFF), - GPIO_GROUP(GPIODV_10, EE_OFF), - GPIO_GROUP(GPIODV_11, EE_OFF), - GPIO_GROUP(GPIODV_12, EE_OFF), - GPIO_GROUP(GPIODV_13, EE_OFF), - GPIO_GROUP(GPIODV_14, EE_OFF), - GPIO_GROUP(GPIODV_15, EE_OFF), - GPIO_GROUP(GPIODV_16, EE_OFF), - GPIO_GROUP(GPIODV_17, EE_OFF), - GPIO_GROUP(GPIODV_19, EE_OFF), - GPIO_GROUP(GPIODV_20, EE_OFF), - GPIO_GROUP(GPIODV_21, EE_OFF), - GPIO_GROUP(GPIODV_22, EE_OFF), - GPIO_GROUP(GPIODV_23, EE_OFF), - GPIO_GROUP(GPIODV_24, EE_OFF), - GPIO_GROUP(GPIODV_25, EE_OFF), - GPIO_GROUP(GPIODV_26, EE_OFF), - GPIO_GROUP(GPIODV_27, EE_OFF), - GPIO_GROUP(GPIODV_28, EE_OFF), - GPIO_GROUP(GPIODV_29, EE_OFF), - - GPIO_GROUP(GPIOY_0, EE_OFF), - GPIO_GROUP(GPIOY_1, EE_OFF), - GPIO_GROUP(GPIOY_2, EE_OFF), - GPIO_GROUP(GPIOY_3, EE_OFF), - GPIO_GROUP(GPIOY_4, EE_OFF), - GPIO_GROUP(GPIOY_5, EE_OFF), - GPIO_GROUP(GPIOY_6, EE_OFF), - GPIO_GROUP(GPIOY_7, EE_OFF), - GPIO_GROUP(GPIOY_8, EE_OFF), - GPIO_GROUP(GPIOY_9, EE_OFF), - GPIO_GROUP(GPIOY_10, EE_OFF), - GPIO_GROUP(GPIOY_11, EE_OFF), - GPIO_GROUP(GPIOY_12, EE_OFF), - GPIO_GROUP(GPIOY_13, EE_OFF), - GPIO_GROUP(GPIOY_14, EE_OFF), - GPIO_GROUP(GPIOY_15, EE_OFF), - GPIO_GROUP(GPIOY_16, EE_OFF), - - GPIO_GROUP(GPIOX_0, EE_OFF), - GPIO_GROUP(GPIOX_1, EE_OFF), - GPIO_GROUP(GPIOX_2, EE_OFF), - GPIO_GROUP(GPIOX_3, EE_OFF), - GPIO_GROUP(GPIOX_4, EE_OFF), - GPIO_GROUP(GPIOX_5, EE_OFF), - GPIO_GROUP(GPIOX_6, EE_OFF), - GPIO_GROUP(GPIOX_7, EE_OFF), - GPIO_GROUP(GPIOX_8, EE_OFF), - GPIO_GROUP(GPIOX_9, EE_OFF), - GPIO_GROUP(GPIOX_10, EE_OFF), - GPIO_GROUP(GPIOX_11, EE_OFF), - GPIO_GROUP(GPIOX_12, EE_OFF), - GPIO_GROUP(GPIOX_13, EE_OFF), - GPIO_GROUP(GPIOX_14, EE_OFF), - GPIO_GROUP(GPIOX_15, EE_OFF), - GPIO_GROUP(GPIOX_16, EE_OFF), - GPIO_GROUP(GPIOX_17, EE_OFF), - GPIO_GROUP(GPIOX_18, EE_OFF), - GPIO_GROUP(GPIOX_19, EE_OFF), - GPIO_GROUP(GPIOX_20, EE_OFF), - GPIO_GROUP(GPIOX_21, EE_OFF), - GPIO_GROUP(GPIOX_22, EE_OFF), - - GPIO_GROUP(GPIOCLK_0, EE_OFF), - GPIO_GROUP(GPIOCLK_1, EE_OFF), - GPIO_GROUP(GPIOCLK_2, EE_OFF), - GPIO_GROUP(GPIOCLK_3, EE_OFF), - - GPIO_GROUP(GPIO_TEST_N, EE_OFF), + GPIO_GROUP(GPIOZ_0), + GPIO_GROUP(GPIOZ_1), + GPIO_GROUP(GPIOZ_2), + GPIO_GROUP(GPIOZ_3), + GPIO_GROUP(GPIOZ_4), + GPIO_GROUP(GPIOZ_5), + GPIO_GROUP(GPIOZ_6), + GPIO_GROUP(GPIOZ_7), + GPIO_GROUP(GPIOZ_8), + GPIO_GROUP(GPIOZ_9), + GPIO_GROUP(GPIOZ_10), + GPIO_GROUP(GPIOZ_11), + GPIO_GROUP(GPIOZ_12), + GPIO_GROUP(GPIOZ_13), + GPIO_GROUP(GPIOZ_14), + GPIO_GROUP(GPIOZ_15), + + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + + GPIO_GROUP(BOOT_0), + GPIO_GROUP(BOOT_1), + GPIO_GROUP(BOOT_2), + GPIO_GROUP(BOOT_3), + GPIO_GROUP(BOOT_4), + GPIO_GROUP(BOOT_5), + GPIO_GROUP(BOOT_6), + GPIO_GROUP(BOOT_7), + GPIO_GROUP(BOOT_8), + GPIO_GROUP(BOOT_9), + GPIO_GROUP(BOOT_10), + GPIO_GROUP(BOOT_11), + GPIO_GROUP(BOOT_12), + GPIO_GROUP(BOOT_13), + GPIO_GROUP(BOOT_14), + GPIO_GROUP(BOOT_15), + GPIO_GROUP(BOOT_16), + GPIO_GROUP(BOOT_17), + + GPIO_GROUP(CARD_0), + GPIO_GROUP(CARD_1), + GPIO_GROUP(CARD_2), + GPIO_GROUP(CARD_3), + GPIO_GROUP(CARD_4), + GPIO_GROUP(CARD_5), + GPIO_GROUP(CARD_6), + + GPIO_GROUP(GPIODV_0), + GPIO_GROUP(GPIODV_1), + GPIO_GROUP(GPIODV_2), + GPIO_GROUP(GPIODV_3), + GPIO_GROUP(GPIODV_4), + GPIO_GROUP(GPIODV_5), + GPIO_GROUP(GPIODV_6), + GPIO_GROUP(GPIODV_7), + GPIO_GROUP(GPIODV_8), + GPIO_GROUP(GPIODV_9), + GPIO_GROUP(GPIODV_10), + GPIO_GROUP(GPIODV_11), + GPIO_GROUP(GPIODV_12), + GPIO_GROUP(GPIODV_13), + GPIO_GROUP(GPIODV_14), + GPIO_GROUP(GPIODV_15), + GPIO_GROUP(GPIODV_16), + GPIO_GROUP(GPIODV_17), + GPIO_GROUP(GPIODV_19), + GPIO_GROUP(GPIODV_20), + GPIO_GROUP(GPIODV_21), + GPIO_GROUP(GPIODV_22), + GPIO_GROUP(GPIODV_23), + GPIO_GROUP(GPIODV_24), + GPIO_GROUP(GPIODV_25), + GPIO_GROUP(GPIODV_26), + GPIO_GROUP(GPIODV_27), + GPIO_GROUP(GPIODV_28), + GPIO_GROUP(GPIODV_29), + + GPIO_GROUP(GPIOY_0), + GPIO_GROUP(GPIOY_1), + GPIO_GROUP(GPIOY_2), + GPIO_GROUP(GPIOY_3), + GPIO_GROUP(GPIOY_4), + GPIO_GROUP(GPIOY_5), + GPIO_GROUP(GPIOY_6), + GPIO_GROUP(GPIOY_7), + GPIO_GROUP(GPIOY_8), + GPIO_GROUP(GPIOY_9), + GPIO_GROUP(GPIOY_10), + GPIO_GROUP(GPIOY_11), + GPIO_GROUP(GPIOY_12), + GPIO_GROUP(GPIOY_13), + GPIO_GROUP(GPIOY_14), + GPIO_GROUP(GPIOY_15), + GPIO_GROUP(GPIOY_16), + + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + GPIO_GROUP(GPIOX_20), + GPIO_GROUP(GPIOX_21), + GPIO_GROUP(GPIOX_22), + + GPIO_GROUP(GPIOCLK_0), + GPIO_GROUP(GPIOCLK_1), + GPIO_GROUP(GPIOCLK_2), + GPIO_GROUP(GPIOCLK_3), + + GPIO_GROUP(GPIO_TEST_N), /* Bank X */ GROUP(sdio_d0, 8, 5), @@ -522,20 +521,20 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { }; static struct meson_pmx_group meson_gxbb_aobus_groups[] = { - GPIO_GROUP(GPIOAO_0, 0), - GPIO_GROUP(GPIOAO_1, 0), - GPIO_GROUP(GPIOAO_2, 0), - GPIO_GROUP(GPIOAO_3, 0), - GPIO_GROUP(GPIOAO_4, 0), - GPIO_GROUP(GPIOAO_5, 0), - GPIO_GROUP(GPIOAO_6, 0), - GPIO_GROUP(GPIOAO_7, 0), - GPIO_GROUP(GPIOAO_8, 0), - GPIO_GROUP(GPIOAO_9, 0), - GPIO_GROUP(GPIOAO_10, 0), - GPIO_GROUP(GPIOAO_11, 0), - GPIO_GROUP(GPIOAO_12, 0), - GPIO_GROUP(GPIOAO_13, 0), + GPIO_GROUP(GPIOAO_0), + GPIO_GROUP(GPIOAO_1), + GPIO_GROUP(GPIOAO_2), + GPIO_GROUP(GPIOAO_3), + GPIO_GROUP(GPIOAO_4), + GPIO_GROUP(GPIOAO_5), + GPIO_GROUP(GPIOAO_6), + GPIO_GROUP(GPIOAO_7), + GPIO_GROUP(GPIOAO_8), + GPIO_GROUP(GPIOAO_9), + GPIO_GROUP(GPIOAO_10), + GPIO_GROUP(GPIOAO_11), + GPIO_GROUP(GPIOAO_12), + GPIO_GROUP(GPIOAO_13), /* bank AO */ GROUP(uart_tx_ao_b, 0, 24), @@ -565,6 +564,9 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = { GROUP(spdif_out_ao_13, 0, 4), GROUP(ao_cec, 0, 15), GROUP(ee_cec, 0, 14), + + /* test n pin */ + GROUP(i2s_out_ch67_ao, 1, 2), }; static const char * const gpio_periphs_groups[] = { @@ -600,8 +602,6 @@ static const char * const gpio_periphs_groups[] = { "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", "GPIOX_20", "GPIOX_21", "GPIOX_22", - - "GPIO_TEST_N", }; static const char * const emmc_groups[] = { @@ -710,6 +710,8 @@ static const char * const gpio_aobus_groups[] = { "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", + + "GPIO_TEST_N", }; static const char * const uart_ao_groups[] = { @@ -751,6 +753,7 @@ static const char * const pwm_ao_b_groups[] = { static const char * const i2s_out_ao_groups[] = { "i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk", "i2s_out_ch01_ao", "i2s_out_ch23_ao", "i2s_out_ch45_ao", + "i2s_out_ch67_ao", }; static const char * const spdif_out_ao_groups[] = { @@ -806,25 +809,24 @@ static struct meson_pmx_func meson_gxbb_aobus_functions[] = { }; static struct meson_bank meson_gxbb_periphs_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), - BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 59, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), - BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_3, EE_OFF), 30, 33, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), - BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 14, 29, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), - BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), - BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_17, EE_OFF), 34, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), - BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_3, EE_OFF), 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), + /* name first last irq pullen pull dir out in */ + BANK("X", GPIOX_0, GPIOX_22, 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("Y", GPIOY_0, GPIOY_16, 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", GPIODV_0, GPIODV_29, 59, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("H", GPIOH_0, GPIOH_3, 30, 33, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), + BANK("Z", GPIOZ_0, GPIOZ_15, 14, 29, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), + BANK("BOOT", BOOT_0, BOOT_17, 34, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("CLK", GPIOCLK_0, GPIOCLK_3, 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), }; static struct meson_bank meson_gxbb_aobus_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first last irq pullen pull dir out in */ + BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; -struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { +static struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .name = "periphs-banks", - .pin_base = 14, .pins = meson_gxbb_periphs_pins, .groups = meson_gxbb_periphs_groups, .funcs = meson_gxbb_periphs_functions, @@ -833,11 +835,11 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), + .pmx_ops = &meson8_pmx_ops, }; -struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { +static struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { .name = "aobus-banks", - .pin_base = 0, .pins = meson_gxbb_aobus_pins, .groups = meson_gxbb_aobus_groups, .funcs = meson_gxbb_aobus_functions, @@ -846,4 +848,26 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), + .pmx_ops = &meson8_pmx_ops, +}; + +static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = { + { + .compatible = "amlogic,meson-gxbb-periphs-pinctrl", + .data = &meson_gxbb_periphs_pinctrl_data, + }, + { + .compatible = "amlogic,meson-gxbb-aobus-pinctrl", + .data = &meson_gxbb_aobus_pinctrl_data, + }, + { }, +}; + +static struct platform_driver meson_gxbb_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "meson-gxbb-pinctrl", + .of_match_table = meson_gxbb_pinctrl_dt_match, + }, }; +builtin_platform_driver(meson_gxbb_pinctrl_driver); diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 36c14b85fc7c..b3786cde963d 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -14,408 +14,400 @@ #include <dt-bindings/gpio/meson-gxl-gpio.h> #include "pinctrl-meson.h" - -#define EE_OFF 10 +#include "pinctrl-meson8-pmx.h" static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = { - MESON_PIN(GPIOZ_0, EE_OFF), - MESON_PIN(GPIOZ_1, EE_OFF), - MESON_PIN(GPIOZ_2, EE_OFF), - MESON_PIN(GPIOZ_3, EE_OFF), - MESON_PIN(GPIOZ_4, EE_OFF), - MESON_PIN(GPIOZ_5, EE_OFF), - MESON_PIN(GPIOZ_6, EE_OFF), - MESON_PIN(GPIOZ_7, EE_OFF), - MESON_PIN(GPIOZ_8, EE_OFF), - MESON_PIN(GPIOZ_9, EE_OFF), - MESON_PIN(GPIOZ_10, EE_OFF), - MESON_PIN(GPIOZ_11, EE_OFF), - MESON_PIN(GPIOZ_12, EE_OFF), - MESON_PIN(GPIOZ_13, EE_OFF), - MESON_PIN(GPIOZ_14, EE_OFF), - MESON_PIN(GPIOZ_15, EE_OFF), - - MESON_PIN(GPIOH_0, EE_OFF), - MESON_PIN(GPIOH_1, EE_OFF), - MESON_PIN(GPIOH_2, EE_OFF), - MESON_PIN(GPIOH_3, EE_OFF), - MESON_PIN(GPIOH_4, EE_OFF), - MESON_PIN(GPIOH_5, EE_OFF), - MESON_PIN(GPIOH_6, EE_OFF), - MESON_PIN(GPIOH_7, EE_OFF), - MESON_PIN(GPIOH_8, EE_OFF), - MESON_PIN(GPIOH_9, EE_OFF), - - MESON_PIN(BOOT_0, EE_OFF), - MESON_PIN(BOOT_1, EE_OFF), - MESON_PIN(BOOT_2, EE_OFF), - MESON_PIN(BOOT_3, EE_OFF), - MESON_PIN(BOOT_4, EE_OFF), - MESON_PIN(BOOT_5, EE_OFF), - MESON_PIN(BOOT_6, EE_OFF), - MESON_PIN(BOOT_7, EE_OFF), - MESON_PIN(BOOT_8, EE_OFF), - MESON_PIN(BOOT_9, EE_OFF), - MESON_PIN(BOOT_10, EE_OFF), - MESON_PIN(BOOT_11, EE_OFF), - MESON_PIN(BOOT_12, EE_OFF), - MESON_PIN(BOOT_13, EE_OFF), - MESON_PIN(BOOT_14, EE_OFF), - MESON_PIN(BOOT_15, EE_OFF), - - MESON_PIN(CARD_0, EE_OFF), - MESON_PIN(CARD_1, EE_OFF), - MESON_PIN(CARD_2, EE_OFF), - MESON_PIN(CARD_3, EE_OFF), - MESON_PIN(CARD_4, EE_OFF), - MESON_PIN(CARD_5, EE_OFF), - MESON_PIN(CARD_6, EE_OFF), - - MESON_PIN(GPIODV_0, EE_OFF), - MESON_PIN(GPIODV_1, EE_OFF), - MESON_PIN(GPIODV_2, EE_OFF), - MESON_PIN(GPIODV_3, EE_OFF), - MESON_PIN(GPIODV_4, EE_OFF), - MESON_PIN(GPIODV_5, EE_OFF), - MESON_PIN(GPIODV_6, EE_OFF), - MESON_PIN(GPIODV_7, EE_OFF), - MESON_PIN(GPIODV_8, EE_OFF), - MESON_PIN(GPIODV_9, EE_OFF), - MESON_PIN(GPIODV_10, EE_OFF), - MESON_PIN(GPIODV_11, EE_OFF), - MESON_PIN(GPIODV_12, EE_OFF), - MESON_PIN(GPIODV_13, EE_OFF), - MESON_PIN(GPIODV_14, EE_OFF), - MESON_PIN(GPIODV_15, EE_OFF), - MESON_PIN(GPIODV_16, EE_OFF), - MESON_PIN(GPIODV_17, EE_OFF), - MESON_PIN(GPIODV_18, EE_OFF), - MESON_PIN(GPIODV_19, EE_OFF), - MESON_PIN(GPIODV_20, EE_OFF), - MESON_PIN(GPIODV_21, EE_OFF), - MESON_PIN(GPIODV_22, EE_OFF), - MESON_PIN(GPIODV_23, EE_OFF), - MESON_PIN(GPIODV_24, EE_OFF), - MESON_PIN(GPIODV_25, EE_OFF), - MESON_PIN(GPIODV_26, EE_OFF), - MESON_PIN(GPIODV_27, EE_OFF), - MESON_PIN(GPIODV_28, EE_OFF), - MESON_PIN(GPIODV_29, EE_OFF), - - MESON_PIN(GPIOX_0, EE_OFF), - MESON_PIN(GPIOX_1, EE_OFF), - MESON_PIN(GPIOX_2, EE_OFF), - MESON_PIN(GPIOX_3, EE_OFF), - MESON_PIN(GPIOX_4, EE_OFF), - MESON_PIN(GPIOX_5, EE_OFF), - MESON_PIN(GPIOX_6, EE_OFF), - MESON_PIN(GPIOX_7, EE_OFF), - MESON_PIN(GPIOX_8, EE_OFF), - MESON_PIN(GPIOX_9, EE_OFF), - MESON_PIN(GPIOX_10, EE_OFF), - MESON_PIN(GPIOX_11, EE_OFF), - MESON_PIN(GPIOX_12, EE_OFF), - MESON_PIN(GPIOX_13, EE_OFF), - MESON_PIN(GPIOX_14, EE_OFF), - MESON_PIN(GPIOX_15, EE_OFF), - MESON_PIN(GPIOX_16, EE_OFF), - MESON_PIN(GPIOX_17, EE_OFF), - MESON_PIN(GPIOX_18, EE_OFF), - - MESON_PIN(GPIOCLK_0, EE_OFF), - MESON_PIN(GPIOCLK_1, EE_OFF), - - MESON_PIN(GPIO_TEST_N, EE_OFF), + MESON_PIN(GPIOZ_0), + MESON_PIN(GPIOZ_1), + MESON_PIN(GPIOZ_2), + MESON_PIN(GPIOZ_3), + MESON_PIN(GPIOZ_4), + MESON_PIN(GPIOZ_5), + MESON_PIN(GPIOZ_6), + MESON_PIN(GPIOZ_7), + MESON_PIN(GPIOZ_8), + MESON_PIN(GPIOZ_9), + MESON_PIN(GPIOZ_10), + MESON_PIN(GPIOZ_11), + MESON_PIN(GPIOZ_12), + MESON_PIN(GPIOZ_13), + MESON_PIN(GPIOZ_14), + MESON_PIN(GPIOZ_15), + + MESON_PIN(GPIOH_0), + MESON_PIN(GPIOH_1), + MESON_PIN(GPIOH_2), + MESON_PIN(GPIOH_3), + MESON_PIN(GPIOH_4), + MESON_PIN(GPIOH_5), + MESON_PIN(GPIOH_6), + MESON_PIN(GPIOH_7), + MESON_PIN(GPIOH_8), + MESON_PIN(GPIOH_9), + + MESON_PIN(BOOT_0), + MESON_PIN(BOOT_1), + MESON_PIN(BOOT_2), + MESON_PIN(BOOT_3), + MESON_PIN(BOOT_4), + MESON_PIN(BOOT_5), + MESON_PIN(BOOT_6), + MESON_PIN(BOOT_7), + MESON_PIN(BOOT_8), + MESON_PIN(BOOT_9), + MESON_PIN(BOOT_10), + MESON_PIN(BOOT_11), + MESON_PIN(BOOT_12), + MESON_PIN(BOOT_13), + MESON_PIN(BOOT_14), + MESON_PIN(BOOT_15), + + MESON_PIN(CARD_0), + MESON_PIN(CARD_1), + MESON_PIN(CARD_2), + MESON_PIN(CARD_3), + MESON_PIN(CARD_4), + MESON_PIN(CARD_5), + MESON_PIN(CARD_6), + + MESON_PIN(GPIODV_0), + MESON_PIN(GPIODV_1), + MESON_PIN(GPIODV_2), + MESON_PIN(GPIODV_3), + MESON_PIN(GPIODV_4), + MESON_PIN(GPIODV_5), + MESON_PIN(GPIODV_6), + MESON_PIN(GPIODV_7), + MESON_PIN(GPIODV_8), + MESON_PIN(GPIODV_9), + MESON_PIN(GPIODV_10), + MESON_PIN(GPIODV_11), + MESON_PIN(GPIODV_12), + MESON_PIN(GPIODV_13), + MESON_PIN(GPIODV_14), + MESON_PIN(GPIODV_15), + MESON_PIN(GPIODV_16), + MESON_PIN(GPIODV_17), + MESON_PIN(GPIODV_18), + MESON_PIN(GPIODV_19), + MESON_PIN(GPIODV_20), + MESON_PIN(GPIODV_21), + MESON_PIN(GPIODV_22), + MESON_PIN(GPIODV_23), + MESON_PIN(GPIODV_24), + MESON_PIN(GPIODV_25), + MESON_PIN(GPIODV_26), + MESON_PIN(GPIODV_27), + MESON_PIN(GPIODV_28), + MESON_PIN(GPIODV_29), + + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOX_14), + MESON_PIN(GPIOX_15), + MESON_PIN(GPIOX_16), + MESON_PIN(GPIOX_17), + MESON_PIN(GPIOX_18), + + MESON_PIN(GPIOCLK_0), + MESON_PIN(GPIOCLK_1), }; static const unsigned int emmc_nand_d07_pins[] = { - PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF), - PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF), - PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF), -}; -static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) }; -static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) }; -static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) }; - -static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) }; -static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; -static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; -static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; - -static const unsigned int spi_mosi_pins[] = { PIN(GPIOX_8, EE_OFF) }; -static const unsigned int spi_miso_pins[] = { PIN(GPIOX_9, EE_OFF) }; -static const unsigned int spi_ss0_pins[] = { PIN(GPIOX_10, EE_OFF) }; -static const unsigned int spi_sclk_pins[] = { PIN(GPIOX_11, EE_OFF) }; - -static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; -static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; -static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; -static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) }; -static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) }; -static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) }; - -static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) }; -static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) }; -static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) }; -static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) }; -static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; -static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; -static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; - -static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; -static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; -static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; -static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; -static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; -static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; -static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) }; -static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) }; - -static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; -static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; -static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; -static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) }; - -static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) }; -static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) }; -static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; -static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; - -static const unsigned int uart_tx_c_pins[] = { PIN(GPIOX_8, EE_OFF) }; -static const unsigned int uart_rx_c_pins[] = { PIN(GPIOX_9, EE_OFF) }; -static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_10, EE_OFF) }; -static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_11, EE_OFF) }; - -static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) }; -static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) }; - -static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; -static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; - -static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) }; -static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) }; - -static const unsigned int i2c_sck_c_dv19_pins[] = { PIN(GPIODV_19, EE_OFF) }; -static const unsigned int i2c_sda_c_dv18_pins[] = { PIN(GPIODV_18, EE_OFF) }; - -static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) }; -static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) }; -static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) }; -static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) }; -static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) }; -static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) }; -static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) }; -static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) }; -static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) }; -static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) }; -static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) }; -static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) }; -static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) }; -static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) }; - -static const unsigned int pwm_a_pins[] = { PIN(GPIOX_6, EE_OFF) }; - -static const unsigned int pwm_b_pins[] = { PIN(GPIODV_29, EE_OFF) }; - -static const unsigned int pwm_c_pins[] = { PIN(GPIOZ_15, EE_OFF) }; - -static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) }; - -static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) }; - -static const unsigned int pwm_f_clk_pins[] = { PIN(GPIOCLK_1, EE_OFF) }; -static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) }; - -static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; -static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; -static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; - -static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOH_6, EE_OFF) }; -static const unsigned int i2s_out_ao_clk_pins[] = { PIN(GPIOH_7, EE_OFF) }; -static const unsigned int i2s_out_lr_clk_pins[] = { PIN(GPIOH_8, EE_OFF) }; -static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOH_9, EE_OFF) }; -static const unsigned int i2s_out_ch23_z_pins[] = { PIN(GPIOZ_5, EE_OFF) }; -static const unsigned int i2s_out_ch45_z_pins[] = { PIN(GPIOZ_6, EE_OFF) }; -static const unsigned int i2s_out_ch67_z_pins[] = { PIN(GPIOZ_7, EE_OFF) }; - -static const unsigned int spdif_out_h_pins[] = { PIN(GPIOH_4, EE_OFF) }; - -static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) }; -static const unsigned int eth_act_led_pins[] = { PIN(GPIOZ_15, EE_OFF) }; - -static const unsigned int tsin_a_d0_pins[] = { PIN(GPIODV_0, EE_OFF) }; -static const unsigned int tsin_a_d0_x_pins[] = { PIN(GPIOX_10, EE_OFF) }; -static const unsigned int tsin_a_clk_pins[] = { PIN(GPIODV_8, EE_OFF) }; -static const unsigned int tsin_a_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) }; -static const unsigned int tsin_a_sop_pins[] = { PIN(GPIODV_9, EE_OFF) }; -static const unsigned int tsin_a_sop_x_pins[] = { PIN(GPIOX_8, EE_OFF) }; -static const unsigned int tsin_a_d_valid_pins[] = { PIN(GPIODV_10, EE_OFF) }; -static const unsigned int tsin_a_d_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) }; -static const unsigned int tsin_a_fail_pins[] = { PIN(GPIODV_11, EE_OFF) }; + BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7, +}; +static const unsigned int emmc_clk_pins[] = { BOOT_8 }; +static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; +static const unsigned int emmc_ds_pins[] = { BOOT_15 }; + +static const unsigned int nor_d_pins[] = { BOOT_11 }; +static const unsigned int nor_q_pins[] = { BOOT_12 }; +static const unsigned int nor_c_pins[] = { BOOT_13 }; +static const unsigned int nor_cs_pins[] = { BOOT_15 }; + +static const unsigned int spi_mosi_pins[] = { GPIOX_8 }; +static const unsigned int spi_miso_pins[] = { GPIOX_9 }; +static const unsigned int spi_ss0_pins[] = { GPIOX_10 }; +static const unsigned int spi_sclk_pins[] = { GPIOX_11 }; + +static const unsigned int sdcard_d0_pins[] = { CARD_1 }; +static const unsigned int sdcard_d1_pins[] = { CARD_0 }; +static const unsigned int sdcard_d2_pins[] = { CARD_5 }; +static const unsigned int sdcard_d3_pins[] = { CARD_4 }; +static const unsigned int sdcard_cmd_pins[] = { CARD_3 }; +static const unsigned int sdcard_clk_pins[] = { CARD_2 }; + +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; +static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; + +static const unsigned int nand_ce0_pins[] = { BOOT_8 }; +static const unsigned int nand_ce1_pins[] = { BOOT_9 }; +static const unsigned int nand_rb0_pins[] = { BOOT_10 }; +static const unsigned int nand_ale_pins[] = { BOOT_11 }; +static const unsigned int nand_cle_pins[] = { BOOT_12 }; +static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; +static const unsigned int nand_ren_wr_pins[] = { BOOT_14 }; +static const unsigned int nand_dqs_pins[] = { BOOT_15 }; + +static const unsigned int uart_tx_a_pins[] = { GPIOX_12 }; +static const unsigned int uart_rx_a_pins[] = { GPIOX_13 }; +static const unsigned int uart_cts_a_pins[] = { GPIOX_14 }; +static const unsigned int uart_rts_a_pins[] = { GPIOX_15 }; + +static const unsigned int uart_tx_b_pins[] = { GPIODV_24 }; +static const unsigned int uart_rx_b_pins[] = { GPIODV_25 }; +static const unsigned int uart_cts_b_pins[] = { GPIODV_26 }; +static const unsigned int uart_rts_b_pins[] = { GPIODV_27 }; + +static const unsigned int uart_tx_c_pins[] = { GPIOX_8 }; +static const unsigned int uart_rx_c_pins[] = { GPIOX_9 }; +static const unsigned int uart_cts_c_pins[] = { GPIOX_10 }; +static const unsigned int uart_rts_c_pins[] = { GPIOX_11 }; + +static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; +static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; + +static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 }; +static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 }; + +static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 }; +static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 }; + +static const unsigned int i2c_sck_c_dv19_pins[] = { GPIODV_19 }; +static const unsigned int i2c_sda_c_dv18_pins[] = { GPIODV_18 }; + +static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; +static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; +static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 }; +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; +static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; +static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; +static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 }; +static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 }; +static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; +static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 }; +static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; +static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; +static const unsigned int eth_txd2_pins[] = { GPIOZ_12 }; +static const unsigned int eth_txd3_pins[] = { GPIOZ_13 }; + +static const unsigned int pwm_a_pins[] = { GPIOX_6 }; + +static const unsigned int pwm_b_pins[] = { GPIODV_29 }; + +static const unsigned int pwm_c_pins[] = { GPIOZ_15 }; + +static const unsigned int pwm_d_pins[] = { GPIODV_28 }; + +static const unsigned int pwm_e_pins[] = { GPIOX_16 }; + +static const unsigned int pwm_f_clk_pins[] = { GPIOCLK_1 }; +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; + +static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; +static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; +static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; + +static const unsigned int i2s_am_clk_pins[] = { GPIOH_6 }; +static const unsigned int i2s_out_ao_clk_pins[] = { GPIOH_7 }; +static const unsigned int i2s_out_lr_clk_pins[] = { GPIOH_8 }; +static const unsigned int i2s_out_ch01_pins[] = { GPIOH_9 }; +static const unsigned int i2s_out_ch23_z_pins[] = { GPIOZ_5 }; +static const unsigned int i2s_out_ch45_z_pins[] = { GPIOZ_6 }; +static const unsigned int i2s_out_ch67_z_pins[] = { GPIOZ_7 }; + +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; + +static const unsigned int eth_link_led_pins[] = { GPIOZ_14 }; +static const unsigned int eth_act_led_pins[] = { GPIOZ_15 }; + +static const unsigned int tsin_a_d0_pins[] = { GPIODV_0 }; +static const unsigned int tsin_a_d0_x_pins[] = { GPIOX_10 }; +static const unsigned int tsin_a_clk_pins[] = { GPIODV_8 }; +static const unsigned int tsin_a_clk_x_pins[] = { GPIOX_11 }; +static const unsigned int tsin_a_sop_pins[] = { GPIODV_9 }; +static const unsigned int tsin_a_sop_x_pins[] = { GPIOX_8 }; +static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 }; +static const unsigned int tsin_a_d_valid_x_pins[] = { GPIOX_9 }; +static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 }; static const unsigned int tsin_a_dp_pins[] = { - PIN(GPIODV_1, EE_OFF), - PIN(GPIODV_2, EE_OFF), - PIN(GPIODV_3, EE_OFF), - PIN(GPIODV_4, EE_OFF), - PIN(GPIODV_5, EE_OFF), - PIN(GPIODV_6, EE_OFF), - PIN(GPIODV_7, EE_OFF), + GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7, }; static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = { - MESON_PIN(GPIOAO_0, 0), - MESON_PIN(GPIOAO_1, 0), - MESON_PIN(GPIOAO_2, 0), - MESON_PIN(GPIOAO_3, 0), - MESON_PIN(GPIOAO_4, 0), - MESON_PIN(GPIOAO_5, 0), - MESON_PIN(GPIOAO_6, 0), - MESON_PIN(GPIOAO_7, 0), - MESON_PIN(GPIOAO_8, 0), - MESON_PIN(GPIOAO_9, 0), -}; - -static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) }; -static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) }; -static const unsigned int uart_tx_ao_b_0_pins[] = { PIN(GPIOAO_0, 0) }; -static const unsigned int uart_rx_ao_b_1_pins[] = { PIN(GPIOAO_1, 0) }; -static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) }; -static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) }; -static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_4, 0) }; -static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_5, 0) }; -static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) }; -static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) }; - -static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; -static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; -static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; -static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; - -static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; - -static const unsigned int pwm_ao_a_3_pins[] = { PIN(GPIOAO_3, 0) }; -static const unsigned int pwm_ao_a_8_pins[] = { PIN(GPIOAO_8, 0) }; - -static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_9, 0) }; -static const unsigned int pwm_ao_b_6_pins[] = { PIN(GPIOAO_6, 0) }; - -static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, 0) }; -static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, 0) }; - -static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) }; -static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, 0) }; - -static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_8, 0) }; -static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_8, 0) }; + MESON_PIN(GPIOAO_0), + MESON_PIN(GPIOAO_1), + MESON_PIN(GPIOAO_2), + MESON_PIN(GPIOAO_3), + MESON_PIN(GPIOAO_4), + MESON_PIN(GPIOAO_5), + MESON_PIN(GPIOAO_6), + MESON_PIN(GPIOAO_7), + MESON_PIN(GPIOAO_8), + MESON_PIN(GPIOAO_9), + + MESON_PIN(GPIO_TEST_N), +}; + +static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; +static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; +static const unsigned int uart_tx_ao_b_0_pins[] = { GPIOAO_0 }; +static const unsigned int uart_rx_ao_b_1_pins[] = { GPIOAO_1 }; +static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; +static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; +static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 }; +static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 }; +static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 }; +static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 }; + +static const unsigned int i2c_sck_ao_pins[] = {GPIOAO_4 }; +static const unsigned int i2c_sda_ao_pins[] = {GPIOAO_5 }; +static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 }; +static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 }; + +static const unsigned int remote_input_ao_pins[] = {GPIOAO_7 }; + +static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 }; +static const unsigned int pwm_ao_a_8_pins[] = { GPIOAO_8 }; + +static const unsigned int pwm_ao_b_pins[] = { GPIOAO_9 }; +static const unsigned int pwm_ao_b_6_pins[] = { GPIOAO_6 }; + +static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_8 }; +static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_9 }; +static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N }; + +static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 }; +static const unsigned int spdif_out_ao_9_pins[] = { GPIOAO_9 }; + +static const unsigned int ao_cec_pins[] = { GPIOAO_8 }; +static const unsigned int ee_cec_pins[] = { GPIOAO_8 }; static struct meson_pmx_group meson_gxl_periphs_groups[] = { - GPIO_GROUP(GPIOZ_0, EE_OFF), - GPIO_GROUP(GPIOZ_1, EE_OFF), - GPIO_GROUP(GPIOZ_2, EE_OFF), - GPIO_GROUP(GPIOZ_3, EE_OFF), - GPIO_GROUP(GPIOZ_4, EE_OFF), - GPIO_GROUP(GPIOZ_5, EE_OFF), - GPIO_GROUP(GPIOZ_6, EE_OFF), - GPIO_GROUP(GPIOZ_7, EE_OFF), - GPIO_GROUP(GPIOZ_8, EE_OFF), - GPIO_GROUP(GPIOZ_9, EE_OFF), - GPIO_GROUP(GPIOZ_10, EE_OFF), - GPIO_GROUP(GPIOZ_11, EE_OFF), - GPIO_GROUP(GPIOZ_12, EE_OFF), - GPIO_GROUP(GPIOZ_13, EE_OFF), - GPIO_GROUP(GPIOZ_14, EE_OFF), - GPIO_GROUP(GPIOZ_15, EE_OFF), - - GPIO_GROUP(GPIOH_0, EE_OFF), - GPIO_GROUP(GPIOH_1, EE_OFF), - GPIO_GROUP(GPIOH_2, EE_OFF), - GPIO_GROUP(GPIOH_3, EE_OFF), - GPIO_GROUP(GPIOH_4, EE_OFF), - GPIO_GROUP(GPIOH_5, EE_OFF), - GPIO_GROUP(GPIOH_6, EE_OFF), - GPIO_GROUP(GPIOH_7, EE_OFF), - GPIO_GROUP(GPIOH_8, EE_OFF), - GPIO_GROUP(GPIOH_9, EE_OFF), - - GPIO_GROUP(BOOT_0, EE_OFF), - GPIO_GROUP(BOOT_1, EE_OFF), - GPIO_GROUP(BOOT_2, EE_OFF), - GPIO_GROUP(BOOT_3, EE_OFF), - GPIO_GROUP(BOOT_4, EE_OFF), - GPIO_GROUP(BOOT_5, EE_OFF), - GPIO_GROUP(BOOT_6, EE_OFF), - GPIO_GROUP(BOOT_7, EE_OFF), - GPIO_GROUP(BOOT_8, EE_OFF), - GPIO_GROUP(BOOT_9, EE_OFF), - GPIO_GROUP(BOOT_10, EE_OFF), - GPIO_GROUP(BOOT_11, EE_OFF), - GPIO_GROUP(BOOT_12, EE_OFF), - GPIO_GROUP(BOOT_13, EE_OFF), - GPIO_GROUP(BOOT_14, EE_OFF), - GPIO_GROUP(BOOT_15, EE_OFF), - - GPIO_GROUP(CARD_0, EE_OFF), - GPIO_GROUP(CARD_1, EE_OFF), - GPIO_GROUP(CARD_2, EE_OFF), - GPIO_GROUP(CARD_3, EE_OFF), - GPIO_GROUP(CARD_4, EE_OFF), - GPIO_GROUP(CARD_5, EE_OFF), - GPIO_GROUP(CARD_6, EE_OFF), - - GPIO_GROUP(GPIODV_0, EE_OFF), - GPIO_GROUP(GPIODV_1, EE_OFF), - GPIO_GROUP(GPIODV_2, EE_OFF), - GPIO_GROUP(GPIODV_3, EE_OFF), - GPIO_GROUP(GPIODV_4, EE_OFF), - GPIO_GROUP(GPIODV_5, EE_OFF), - GPIO_GROUP(GPIODV_6, EE_OFF), - GPIO_GROUP(GPIODV_7, EE_OFF), - GPIO_GROUP(GPIODV_8, EE_OFF), - GPIO_GROUP(GPIODV_9, EE_OFF), - GPIO_GROUP(GPIODV_10, EE_OFF), - GPIO_GROUP(GPIODV_11, EE_OFF), - GPIO_GROUP(GPIODV_12, EE_OFF), - GPIO_GROUP(GPIODV_13, EE_OFF), - GPIO_GROUP(GPIODV_14, EE_OFF), - GPIO_GROUP(GPIODV_15, EE_OFF), - GPIO_GROUP(GPIODV_16, EE_OFF), - GPIO_GROUP(GPIODV_17, EE_OFF), - GPIO_GROUP(GPIODV_19, EE_OFF), - GPIO_GROUP(GPIODV_20, EE_OFF), - GPIO_GROUP(GPIODV_21, EE_OFF), - GPIO_GROUP(GPIODV_22, EE_OFF), - GPIO_GROUP(GPIODV_23, EE_OFF), - GPIO_GROUP(GPIODV_24, EE_OFF), - GPIO_GROUP(GPIODV_25, EE_OFF), - GPIO_GROUP(GPIODV_26, EE_OFF), - GPIO_GROUP(GPIODV_27, EE_OFF), - GPIO_GROUP(GPIODV_28, EE_OFF), - GPIO_GROUP(GPIODV_29, EE_OFF), - - GPIO_GROUP(GPIOX_0, EE_OFF), - GPIO_GROUP(GPIOX_1, EE_OFF), - GPIO_GROUP(GPIOX_2, EE_OFF), - GPIO_GROUP(GPIOX_3, EE_OFF), - GPIO_GROUP(GPIOX_4, EE_OFF), - GPIO_GROUP(GPIOX_5, EE_OFF), - GPIO_GROUP(GPIOX_6, EE_OFF), - GPIO_GROUP(GPIOX_7, EE_OFF), - GPIO_GROUP(GPIOX_8, EE_OFF), - GPIO_GROUP(GPIOX_9, EE_OFF), - GPIO_GROUP(GPIOX_10, EE_OFF), - GPIO_GROUP(GPIOX_11, EE_OFF), - GPIO_GROUP(GPIOX_12, EE_OFF), - GPIO_GROUP(GPIOX_13, EE_OFF), - GPIO_GROUP(GPIOX_14, EE_OFF), - GPIO_GROUP(GPIOX_15, EE_OFF), - GPIO_GROUP(GPIOX_16, EE_OFF), - GPIO_GROUP(GPIOX_17, EE_OFF), - GPIO_GROUP(GPIOX_18, EE_OFF), - - GPIO_GROUP(GPIOCLK_0, EE_OFF), - GPIO_GROUP(GPIOCLK_1, EE_OFF), - - GPIO_GROUP(GPIO_TEST_N, EE_OFF), + GPIO_GROUP(GPIOZ_0), + GPIO_GROUP(GPIOZ_1), + GPIO_GROUP(GPIOZ_2), + GPIO_GROUP(GPIOZ_3), + GPIO_GROUP(GPIOZ_4), + GPIO_GROUP(GPIOZ_5), + GPIO_GROUP(GPIOZ_6), + GPIO_GROUP(GPIOZ_7), + GPIO_GROUP(GPIOZ_8), + GPIO_GROUP(GPIOZ_9), + GPIO_GROUP(GPIOZ_10), + GPIO_GROUP(GPIOZ_11), + GPIO_GROUP(GPIOZ_12), + GPIO_GROUP(GPIOZ_13), + GPIO_GROUP(GPIOZ_14), + GPIO_GROUP(GPIOZ_15), + + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + GPIO_GROUP(GPIOH_4), + GPIO_GROUP(GPIOH_5), + GPIO_GROUP(GPIOH_6), + GPIO_GROUP(GPIOH_7), + GPIO_GROUP(GPIOH_8), + GPIO_GROUP(GPIOH_9), + + GPIO_GROUP(BOOT_0), + GPIO_GROUP(BOOT_1), + GPIO_GROUP(BOOT_2), + GPIO_GROUP(BOOT_3), + GPIO_GROUP(BOOT_4), + GPIO_GROUP(BOOT_5), + GPIO_GROUP(BOOT_6), + GPIO_GROUP(BOOT_7), + GPIO_GROUP(BOOT_8), + GPIO_GROUP(BOOT_9), + GPIO_GROUP(BOOT_10), + GPIO_GROUP(BOOT_11), + GPIO_GROUP(BOOT_12), + GPIO_GROUP(BOOT_13), + GPIO_GROUP(BOOT_14), + GPIO_GROUP(BOOT_15), + + GPIO_GROUP(CARD_0), + GPIO_GROUP(CARD_1), + GPIO_GROUP(CARD_2), + GPIO_GROUP(CARD_3), + GPIO_GROUP(CARD_4), + GPIO_GROUP(CARD_5), + GPIO_GROUP(CARD_6), + + GPIO_GROUP(GPIODV_0), + GPIO_GROUP(GPIODV_1), + GPIO_GROUP(GPIODV_2), + GPIO_GROUP(GPIODV_3), + GPIO_GROUP(GPIODV_4), + GPIO_GROUP(GPIODV_5), + GPIO_GROUP(GPIODV_6), + GPIO_GROUP(GPIODV_7), + GPIO_GROUP(GPIODV_8), + GPIO_GROUP(GPIODV_9), + GPIO_GROUP(GPIODV_10), + GPIO_GROUP(GPIODV_11), + GPIO_GROUP(GPIODV_12), + GPIO_GROUP(GPIODV_13), + GPIO_GROUP(GPIODV_14), + GPIO_GROUP(GPIODV_15), + GPIO_GROUP(GPIODV_16), + GPIO_GROUP(GPIODV_17), + GPIO_GROUP(GPIODV_19), + GPIO_GROUP(GPIODV_20), + GPIO_GROUP(GPIODV_21), + GPIO_GROUP(GPIODV_22), + GPIO_GROUP(GPIODV_23), + GPIO_GROUP(GPIODV_24), + GPIO_GROUP(GPIODV_25), + GPIO_GROUP(GPIODV_26), + GPIO_GROUP(GPIODV_27), + GPIO_GROUP(GPIODV_28), + GPIO_GROUP(GPIODV_29), + + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + + GPIO_GROUP(GPIOCLK_0), + GPIO_GROUP(GPIOCLK_1), + + GPIO_GROUP(GPIO_TEST_N), /* Bank X */ GROUP(sdio_d0, 5, 31), @@ -530,16 +522,16 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = { }; static struct meson_pmx_group meson_gxl_aobus_groups[] = { - GPIO_GROUP(GPIOAO_0, 0), - GPIO_GROUP(GPIOAO_1, 0), - GPIO_GROUP(GPIOAO_2, 0), - GPIO_GROUP(GPIOAO_3, 0), - GPIO_GROUP(GPIOAO_4, 0), - GPIO_GROUP(GPIOAO_5, 0), - GPIO_GROUP(GPIOAO_6, 0), - GPIO_GROUP(GPIOAO_7, 0), - GPIO_GROUP(GPIOAO_8, 0), - GPIO_GROUP(GPIOAO_9, 0), + GPIO_GROUP(GPIOAO_0), + GPIO_GROUP(GPIOAO_1), + GPIO_GROUP(GPIOAO_2), + GPIO_GROUP(GPIOAO_3), + GPIO_GROUP(GPIOAO_4), + GPIO_GROUP(GPIOAO_5), + GPIO_GROUP(GPIOAO_6), + GPIO_GROUP(GPIOAO_7), + GPIO_GROUP(GPIOAO_8), + GPIO_GROUP(GPIOAO_9), /* bank AO */ GROUP(uart_tx_ao_b_0, 0, 26), @@ -567,6 +559,9 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = { GROUP(spdif_out_ao_9, 0, 4), GROUP(ao_cec, 0, 15), GROUP(ee_cec, 0, 14), + + /* test n pin */ + GROUP(i2s_out_ch67_ao, 1, 2), }; static const char * const gpio_periphs_groups[] = { @@ -597,8 +592,6 @@ static const char * const gpio_periphs_groups[] = { "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", - - "GPIO_TEST_N", }; static const char * const emmc_groups[] = { @@ -713,6 +706,8 @@ static const char * const tsin_a_groups[] = { static const char * const gpio_aobus_groups[] = { "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", + + "GPIO_TEST_N", }; static const char * const uart_ao_groups[] = { @@ -745,7 +740,7 @@ static const char * const pwm_ao_b_groups[] = { }; static const char * const i2s_out_ao_groups[] = { - "i2s_out_ch23_ao", "i2s_out_ch45_ao", + "i2s_out_ch23_ao", "i2s_out_ch45_ao", "i2s_out_ch67_ao", }; static const char * const spdif_out_ao_groups[] = { @@ -800,24 +795,23 @@ static struct meson_pmx_func meson_gxl_aobus_functions[] = { }; static struct meson_bank meson_gxl_periphs_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_18, EE_OFF), 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), - BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), - BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF), 26, 35, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), - BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 10, 25, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), - BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), - BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 36, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), - BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_1, EE_OFF), 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), + /* name first last irq pullen pull dir out in */ + BANK("X", GPIOX_0, GPIOX_18, 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("DV", GPIODV_0, GPIODV_29, 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("H", GPIOH_0, GPIOH_9, 26, 35, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), + BANK("Z", GPIOZ_0, GPIOZ_15, 10, 25, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), + BANK("BOOT", BOOT_0, BOOT_15, 36, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("CLK", GPIOCLK_0, GPIOCLK_1, 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), }; static struct meson_bank meson_gxl_aobus_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_9, 0), 0, 9, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first last irq pullen pull dir out in */ + BANK("AO", GPIOAO_0, GPIOAO_9, 0, 9, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; -struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { +static struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { .name = "periphs-banks", - .pin_base = 10, .pins = meson_gxl_periphs_pins, .groups = meson_gxl_periphs_groups, .funcs = meson_gxl_periphs_functions, @@ -826,11 +820,11 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), + .pmx_ops = &meson8_pmx_ops, }; -struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { +static struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { .name = "aobus-banks", - .pin_base = 0, .pins = meson_gxl_aobus_pins, .groups = meson_gxl_aobus_groups, .funcs = meson_gxl_aobus_functions, @@ -839,4 +833,26 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), + .pmx_ops = &meson8_pmx_ops, +}; + +static const struct of_device_id meson_gxl_pinctrl_dt_match[] = { + { + .compatible = "amlogic,meson-gxl-periphs-pinctrl", + .data = &meson_gxl_periphs_pinctrl_data, + }, + { + .compatible = "amlogic,meson-gxl-aobus-pinctrl", + .data = &meson_gxl_aobus_pinctrl_data, + }, + { }, +}; + +static struct platform_driver meson_gxl_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "meson-gxl-pinctrl", + .of_match_table = meson_gxl_pinctrl_dt_match, + }, }; +builtin_platform_driver(meson_gxl_pinctrl_driver); diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 66ed70c12733..29a458da78db 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -31,10 +31,6 @@ * In some cases the register ranges for pull enable and pull * direction are the same and thus there are only 3 register ranges. * - * Every pinmux group can be enabled by a specific bit in the first - * register range; when all groups for a given pin are disabled the - * pin acts as a GPIO. - * * For the pull and GPIO configuration every bank uses a contiguous * set of bits in the register sets described above; the same register * can be shared by more banks with different offsets. @@ -50,6 +46,7 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/of_device.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> @@ -147,94 +144,24 @@ static const struct pinctrl_ops meson_pctrl_ops = { .pin_dbg_show = meson_pin_dbg_show, }; -/** - * meson_pmx_disable_other_groups() - disable other groups using a given pin - * - * @pc: meson pin controller device - * @pin: number of the pin - * @sel_group: index of the selected group, or -1 if none - * - * The function disables all pinmux groups using a pin except the - * selected one. If @sel_group is -1 all groups are disabled, leaving - * the pin in GPIO mode. - */ -static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc, - unsigned int pin, int sel_group) -{ - struct meson_pmx_group *group; - int i, j; - - for (i = 0; i < pc->data->num_groups; i++) { - group = &pc->data->groups[i]; - if (group->is_gpio || i == sel_group) - continue; - - for (j = 0; j < group->num_pins; j++) { - if (group->pins[j] == pin) { - /* We have found a group using the pin */ - regmap_update_bits(pc->reg_mux, - group->reg * 4, - BIT(group->bit), 0); - } - } - } -} - -static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, - unsigned group_num) -{ - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); - struct meson_pmx_func *func = &pc->data->funcs[func_num]; - struct meson_pmx_group *group = &pc->data->groups[group_num]; - int i, ret = 0; - - dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, - group->name); - - /* - * Disable groups using the same pin. - * The selected group is not disabled to avoid glitches. - */ - for (i = 0; i < group->num_pins; i++) - meson_pmx_disable_other_groups(pc, group->pins[i], group_num); - - /* Function 0 (GPIO) doesn't need any additional setting */ - if (func_num) - ret = regmap_update_bits(pc->reg_mux, group->reg * 4, - BIT(group->bit), BIT(group->bit)); - - return ret; -} - -static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev, - struct pinctrl_gpio_range *range, - unsigned offset) -{ - struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); - - meson_pmx_disable_other_groups(pc, offset, -1); - - return 0; -} - -static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) +int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev) { struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); return pc->data->num_funcs; } -static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, - unsigned selector) +const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, + unsigned selector) { struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); return pc->data->funcs[selector].name; } -static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) +int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) { struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); @@ -244,14 +171,6 @@ static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, return 0; } -static const struct pinmux_ops meson_pmx_ops = { - .set_mux = meson_pmx_set_mux, - .get_functions_count = meson_pmx_get_funcs_count, - .get_function_name = meson_pmx_get_func_name, - .get_function_groups = meson_pmx_get_groups, - .gpio_request_enable = meson_pmx_request_gpio, -}; - static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, unsigned long *configs, unsigned num_configs) { @@ -399,7 +318,7 @@ static int meson_pinconf_group_set(struct pinctrl_dev *pcdev, static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, unsigned int group, unsigned long *config) { - return -ENOSYS; + return -ENOTSUPP; } static const struct pinconf_ops meson_pinconf_ops = { @@ -410,31 +329,18 @@ static const struct pinconf_ops meson_pinconf_ops = { .is_generic = true, }; -static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio) -{ - return pinctrl_request_gpio(chip->base + gpio); -} - -static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio) -{ - struct meson_pinctrl *pc = gpiochip_get_data(chip); - - pinctrl_free_gpio(pc->data->pin_base + gpio); -} - static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit, pin; + unsigned int reg, bit; struct meson_bank *bank; int ret; - pin = pc->data->pin_base + gpio; - ret = meson_get_bank(pc, pin, &bank); + ret = meson_get_bank(pc, gpio, &bank); if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); } @@ -443,21 +349,20 @@ static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit, pin; + unsigned int reg, bit; struct meson_bank *bank; int ret; - pin = pc->data->pin_base + gpio; - ret = meson_get_bank(pc, pin, &bank); + ret = meson_get_bank(pc, gpio, &bank); if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), value ? BIT(bit) : 0); } @@ -465,16 +370,15 @@ static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) { struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit, pin; + unsigned int reg, bit; struct meson_bank *bank; int ret; - pin = pc->data->pin_base + gpio; - ret = meson_get_bank(pc, pin, &bank); + ret = meson_get_bank(pc, gpio, &bank); if (ret) return; - meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); regmap_update_bits(pc->reg_gpio, reg, BIT(bit), value ? BIT(bit) : 0); } @@ -482,70 +386,33 @@ static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) { struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit, val, pin; + unsigned int reg, bit, val; struct meson_bank *bank; int ret; - pin = pc->data->pin_base + gpio; - ret = meson_get_bank(pc, pin, &bank); + ret = meson_get_bank(pc, gpio, &bank); if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); regmap_read(pc->reg_gpio, reg, &val); return !!(val & BIT(bit)); } -static const struct of_device_id meson_pinctrl_dt_match[] = { - { - .compatible = "amlogic,meson8-cbus-pinctrl", - .data = &meson8_cbus_pinctrl_data, - }, - { - .compatible = "amlogic,meson8b-cbus-pinctrl", - .data = &meson8b_cbus_pinctrl_data, - }, - { - .compatible = "amlogic,meson8-aobus-pinctrl", - .data = &meson8_aobus_pinctrl_data, - }, - { - .compatible = "amlogic,meson8b-aobus-pinctrl", - .data = &meson8b_aobus_pinctrl_data, - }, - { - .compatible = "amlogic,meson-gxbb-periphs-pinctrl", - .data = &meson_gxbb_periphs_pinctrl_data, - }, - { - .compatible = "amlogic,meson-gxbb-aobus-pinctrl", - .data = &meson_gxbb_aobus_pinctrl_data, - }, - { - .compatible = "amlogic,meson-gxl-periphs-pinctrl", - .data = &meson_gxl_periphs_pinctrl_data, - }, - { - .compatible = "amlogic,meson-gxl-aobus-pinctrl", - .data = &meson_gxl_aobus_pinctrl_data, - }, - { }, -}; - static int meson_gpiolib_register(struct meson_pinctrl *pc) { int ret; pc->chip.label = pc->data->name; pc->chip.parent = pc->dev; - pc->chip.request = meson_gpio_request; - pc->chip.free = meson_gpio_free; + pc->chip.request = gpiochip_generic_request; + pc->chip.free = gpiochip_generic_free; pc->chip.direction_input = meson_gpio_direction_input; pc->chip.direction_output = meson_gpio_direction_output; pc->chip.get = meson_gpio_get; pc->chip.set = meson_gpio_set; - pc->chip.base = pc->data->pin_base; + pc->chip.base = -1; pc->chip.ngpio = pc->data->num_pins; pc->chip.can_sleep = false; pc->chip.of_node = pc->of_node; @@ -640,9 +507,8 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, return 0; } -static int meson_pinctrl_probe(struct platform_device *pdev) +int meson_pinctrl_probe(struct platform_device *pdev) { - const struct of_device_id *match; struct device *dev = &pdev->dev; struct meson_pinctrl *pc; int ret; @@ -652,17 +518,16 @@ static int meson_pinctrl_probe(struct platform_device *pdev) return -ENOMEM; pc->dev = dev; - match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node); - pc->data = (struct meson_pinctrl_data *) match->data; + pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev); - ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node); + ret = meson_pinctrl_parse_dt(pc, dev->of_node); if (ret) return ret; pc->desc.name = "pinctrl-meson"; pc->desc.owner = THIS_MODULE; pc->desc.pctlops = &meson_pctrl_ops; - pc->desc.pmxops = &meson_pmx_ops; + pc->desc.pmxops = pc->data->pmx_ops; pc->desc.confops = &meson_pinconf_ops; pc->desc.pins = pc->data->pins; pc->desc.npins = pc->data->num_pins; @@ -675,12 +540,3 @@ static int meson_pinctrl_probe(struct platform_device *pdev) return meson_gpiolib_register(pc); } - -static struct platform_driver meson_pinctrl_driver = { - .probe = meson_pinctrl_probe, - .driver = { - .name = "meson-pinctrl", - .of_match_table = meson_pinctrl_dt_match, - }, -}; -builtin_platform_driver(meson_pinctrl_driver); diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 890f296f5840..183b6e471635 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -13,6 +13,7 @@ #include <linux/gpio.h> #include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/types.h> @@ -31,9 +32,7 @@ struct meson_pmx_group { const char *name; const unsigned int *pins; unsigned int num_pins; - bool is_gpio; - unsigned int reg; - unsigned int bit; + const void *data; }; /** @@ -103,12 +102,12 @@ struct meson_pinctrl_data { const struct pinctrl_pin_desc *pins; struct meson_pmx_group *groups; struct meson_pmx_func *funcs; - unsigned int pin_base; unsigned int num_pins; unsigned int num_groups; unsigned int num_funcs; struct meson_bank *banks; unsigned int num_banks; + const struct pinmux_ops *pmx_ops; }; struct meson_pinctrl { @@ -124,25 +123,6 @@ struct meson_pinctrl { struct device_node *of_node; }; -#define PIN(x, b) (b + x) - -#define GROUP(grp, r, b) \ - { \ - .name = #grp, \ - .pins = grp ## _pins, \ - .num_pins = ARRAY_SIZE(grp ## _pins), \ - .reg = r, \ - .bit = b, \ - } - -#define GPIO_GROUP(gpio, b) \ - { \ - .name = #gpio, \ - .pins = (const unsigned int[]){ PIN(gpio, b) }, \ - .num_pins = 1, \ - .is_gpio = true, \ - } - #define FUNCTION(fn) \ { \ .name = #fn, \ @@ -166,13 +146,16 @@ struct meson_pinctrl { }, \ } -#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x) +#define MESON_PIN(x) PINCTRL_PIN(x, #x) + +/* Common pmx functions */ +int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev); +const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, + unsigned selector); +int meson_pmx_get_groups(struct pinctrl_dev *pcdev, + unsigned selector, + const char * const **groups, + unsigned * const num_groups); -extern struct meson_pinctrl_data meson8_cbus_pinctrl_data; -extern struct meson_pinctrl_data meson8_aobus_pinctrl_data; -extern struct meson_pinctrl_data meson8b_cbus_pinctrl_data; -extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data; -extern struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data; -extern struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data; -extern struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data; -extern struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data; +/* Common probe function */ +int meson_pinctrl_probe(struct platform_device *pdev); diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c new file mode 100644 index 000000000000..b93b058c8a07 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c @@ -0,0 +1,108 @@ +/* + * First generation of pinmux driver for Amlogic Meson SoCs + * + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> + * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* For this first generation of pinctrl driver every pinmux group can be + * enabled by a specific bit in the first register range. When all groups for + * a given pin are disabled the pin acts as a GPIO. + */ +#include <linux/device.h> +#include <linux/regmap.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + +#include "pinctrl-meson.h" +#include "pinctrl-meson8-pmx.h" + +/** + * meson8_pmx_disable_other_groups() - disable other groups using a given pin + * + * @pc: meson pin controller device + * @pin: number of the pin + * @sel_group: index of the selected group, or -1 if none + * + * The function disables all pinmux groups using a pin except the + * selected one. If @sel_group is -1 all groups are disabled, leaving + * the pin in GPIO mode. + */ +static void meson8_pmx_disable_other_groups(struct meson_pinctrl *pc, + unsigned int pin, int sel_group) +{ + struct meson_pmx_group *group; + struct meson8_pmx_data *pmx_data; + int i, j; + + for (i = 0; i < pc->data->num_groups; i++) { + group = &pc->data->groups[i]; + pmx_data = (struct meson8_pmx_data *)group->data; + if (pmx_data->is_gpio || i == sel_group) + continue; + + for (j = 0; j < group->num_pins; j++) { + if (group->pins[j] == pin) { + /* We have found a group using the pin */ + regmap_update_bits(pc->reg_mux, + pmx_data->reg * 4, + BIT(pmx_data->bit), 0); + } + } + } +} + +static int meson8_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num, + unsigned group_num) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + struct meson_pmx_func *func = &pc->data->funcs[func_num]; + struct meson_pmx_group *group = &pc->data->groups[group_num]; + struct meson8_pmx_data *pmx_data = + (struct meson8_pmx_data *)group->data; + int i, ret = 0; + + dev_dbg(pc->dev, "enable function %s, group %s\n", func->name, + group->name); + + /* + * Disable groups using the same pin. + * The selected group is not disabled to avoid glitches. + */ + for (i = 0; i < group->num_pins; i++) + meson8_pmx_disable_other_groups(pc, group->pins[i], group_num); + + /* Function 0 (GPIO) doesn't need any additional setting */ + if (func_num) + ret = regmap_update_bits(pc->reg_mux, pmx_data->reg * 4, + BIT(pmx_data->bit), + BIT(pmx_data->bit)); + + return ret; +} + +static int meson8_pmx_request_gpio(struct pinctrl_dev *pcdev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); + + meson8_pmx_disable_other_groups(pc, offset, -1); + + return 0; +} + +const struct pinmux_ops meson8_pmx_ops = { + .set_mux = meson8_pmx_set_mux, + .get_functions_count = meson_pmx_get_funcs_count, + .get_function_name = meson_pmx_get_func_name, + .get_function_groups = meson_pmx_get_groups, + .gpio_request_enable = meson8_pmx_request_gpio, +}; diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h new file mode 100644 index 000000000000..47293c28f913 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h @@ -0,0 +1,48 @@ +/* + * First generation of pinmux driver for Amlogic Meson SoCs + * + * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> + * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +struct meson8_pmx_data { + bool is_gpio; + unsigned int reg; + unsigned int bit; +}; + +#define PMX_DATA(r, b, g) \ + { \ + .reg = r, \ + .bit = b, \ + .is_gpio = g, \ + } + +#define GROUP(grp, r, b) \ + { \ + .name = #grp, \ + .pins = grp ## _pins, \ + .num_pins = ARRAY_SIZE(grp ## _pins), \ + .data = (const struct meson8_pmx_data[]){ \ + PMX_DATA(r, b, false), \ + }, \ + } + +#define GPIO_GROUP(gpio) \ + { \ + .name = #gpio, \ + .pins = (const unsigned int[]){ gpio }, \ + .num_pins = 1, \ + .data = (const struct meson8_pmx_data[]){ \ + PMX_DATA(0, 0, true), \ + }, \ + } + +extern const struct pinmux_ops meson8_pmx_ops; diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c index 970f6f14502c..49c7ce03547b 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8.c +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -13,506 +13,495 @@ #include <dt-bindings/gpio/meson8-gpio.h> #include "pinctrl-meson.h" - -#define AO_OFF 120 +#include "pinctrl-meson8-pmx.h" static const struct pinctrl_pin_desc meson8_cbus_pins[] = { - MESON_PIN(GPIOX_0, 0), - MESON_PIN(GPIOX_1, 0), - MESON_PIN(GPIOX_2, 0), - MESON_PIN(GPIOX_3, 0), - MESON_PIN(GPIOX_4, 0), - MESON_PIN(GPIOX_5, 0), - MESON_PIN(GPIOX_6, 0), - MESON_PIN(GPIOX_7, 0), - MESON_PIN(GPIOX_8, 0), - MESON_PIN(GPIOX_9, 0), - MESON_PIN(GPIOX_10, 0), - MESON_PIN(GPIOX_11, 0), - MESON_PIN(GPIOX_12, 0), - MESON_PIN(GPIOX_13, 0), - MESON_PIN(GPIOX_14, 0), - MESON_PIN(GPIOX_15, 0), - MESON_PIN(GPIOX_16, 0), - MESON_PIN(GPIOX_17, 0), - MESON_PIN(GPIOX_18, 0), - MESON_PIN(GPIOX_19, 0), - MESON_PIN(GPIOX_20, 0), - MESON_PIN(GPIOX_21, 0), - MESON_PIN(GPIOY_0, 0), - MESON_PIN(GPIOY_1, 0), - MESON_PIN(GPIOY_2, 0), - MESON_PIN(GPIOY_3, 0), - MESON_PIN(GPIOY_4, 0), - MESON_PIN(GPIOY_5, 0), - MESON_PIN(GPIOY_6, 0), - MESON_PIN(GPIOY_7, 0), - MESON_PIN(GPIOY_8, 0), - MESON_PIN(GPIOY_9, 0), - MESON_PIN(GPIOY_10, 0), - MESON_PIN(GPIOY_11, 0), - MESON_PIN(GPIOY_12, 0), - MESON_PIN(GPIOY_13, 0), - MESON_PIN(GPIOY_14, 0), - MESON_PIN(GPIOY_15, 0), - MESON_PIN(GPIOY_16, 0), - MESON_PIN(GPIODV_0, 0), - MESON_PIN(GPIODV_1, 0), - MESON_PIN(GPIODV_2, 0), - MESON_PIN(GPIODV_3, 0), - MESON_PIN(GPIODV_4, 0), - MESON_PIN(GPIODV_5, 0), - MESON_PIN(GPIODV_6, 0), - MESON_PIN(GPIODV_7, 0), - MESON_PIN(GPIODV_8, 0), - MESON_PIN(GPIODV_9, 0), - MESON_PIN(GPIODV_10, 0), - MESON_PIN(GPIODV_11, 0), - MESON_PIN(GPIODV_12, 0), - MESON_PIN(GPIODV_13, 0), - MESON_PIN(GPIODV_14, 0), - MESON_PIN(GPIODV_15, 0), - MESON_PIN(GPIODV_16, 0), - MESON_PIN(GPIODV_17, 0), - MESON_PIN(GPIODV_18, 0), - MESON_PIN(GPIODV_19, 0), - MESON_PIN(GPIODV_20, 0), - MESON_PIN(GPIODV_21, 0), - MESON_PIN(GPIODV_22, 0), - MESON_PIN(GPIODV_23, 0), - MESON_PIN(GPIODV_24, 0), - MESON_PIN(GPIODV_25, 0), - MESON_PIN(GPIODV_26, 0), - MESON_PIN(GPIODV_27, 0), - MESON_PIN(GPIODV_28, 0), - MESON_PIN(GPIODV_29, 0), - MESON_PIN(GPIOH_0, 0), - MESON_PIN(GPIOH_1, 0), - MESON_PIN(GPIOH_2, 0), - MESON_PIN(GPIOH_3, 0), - MESON_PIN(GPIOH_4, 0), - MESON_PIN(GPIOH_5, 0), - MESON_PIN(GPIOH_6, 0), - MESON_PIN(GPIOH_7, 0), - MESON_PIN(GPIOH_8, 0), - MESON_PIN(GPIOH_9, 0), - MESON_PIN(GPIOZ_0, 0), - MESON_PIN(GPIOZ_1, 0), - MESON_PIN(GPIOZ_2, 0), - MESON_PIN(GPIOZ_3, 0), - MESON_PIN(GPIOZ_4, 0), - MESON_PIN(GPIOZ_5, 0), - MESON_PIN(GPIOZ_6, 0), - MESON_PIN(GPIOZ_7, 0), - MESON_PIN(GPIOZ_8, 0), - MESON_PIN(GPIOZ_9, 0), - MESON_PIN(GPIOZ_10, 0), - MESON_PIN(GPIOZ_11, 0), - MESON_PIN(GPIOZ_12, 0), - MESON_PIN(GPIOZ_13, 0), - MESON_PIN(GPIOZ_14, 0), - MESON_PIN(CARD_0, 0), - MESON_PIN(CARD_1, 0), - MESON_PIN(CARD_2, 0), - MESON_PIN(CARD_3, 0), - MESON_PIN(CARD_4, 0), - MESON_PIN(CARD_5, 0), - MESON_PIN(CARD_6, 0), - MESON_PIN(BOOT_0, 0), - MESON_PIN(BOOT_1, 0), - MESON_PIN(BOOT_2, 0), - MESON_PIN(BOOT_3, 0), - MESON_PIN(BOOT_4, 0), - MESON_PIN(BOOT_5, 0), - MESON_PIN(BOOT_6, 0), - MESON_PIN(BOOT_7, 0), - MESON_PIN(BOOT_8, 0), - MESON_PIN(BOOT_9, 0), - MESON_PIN(BOOT_10, 0), - MESON_PIN(BOOT_11, 0), - MESON_PIN(BOOT_12, 0), - MESON_PIN(BOOT_13, 0), - MESON_PIN(BOOT_14, 0), - MESON_PIN(BOOT_15, 0), - MESON_PIN(BOOT_16, 0), - MESON_PIN(BOOT_17, 0), - MESON_PIN(BOOT_18, 0), + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOX_14), + MESON_PIN(GPIOX_15), + MESON_PIN(GPIOX_16), + MESON_PIN(GPIOX_17), + MESON_PIN(GPIOX_18), + MESON_PIN(GPIOX_19), + MESON_PIN(GPIOX_20), + MESON_PIN(GPIOX_21), + MESON_PIN(GPIOY_0), + MESON_PIN(GPIOY_1), + MESON_PIN(GPIOY_2), + MESON_PIN(GPIOY_3), + MESON_PIN(GPIOY_4), + MESON_PIN(GPIOY_5), + MESON_PIN(GPIOY_6), + MESON_PIN(GPIOY_7), + MESON_PIN(GPIOY_8), + MESON_PIN(GPIOY_9), + MESON_PIN(GPIOY_10), + MESON_PIN(GPIOY_11), + MESON_PIN(GPIOY_12), + MESON_PIN(GPIOY_13), + MESON_PIN(GPIOY_14), + MESON_PIN(GPIOY_15), + MESON_PIN(GPIOY_16), + MESON_PIN(GPIODV_0), + MESON_PIN(GPIODV_1), + MESON_PIN(GPIODV_2), + MESON_PIN(GPIODV_3), + MESON_PIN(GPIODV_4), + MESON_PIN(GPIODV_5), + MESON_PIN(GPIODV_6), + MESON_PIN(GPIODV_7), + MESON_PIN(GPIODV_8), + MESON_PIN(GPIODV_9), + MESON_PIN(GPIODV_10), + MESON_PIN(GPIODV_11), + MESON_PIN(GPIODV_12), + MESON_PIN(GPIODV_13), + MESON_PIN(GPIODV_14), + MESON_PIN(GPIODV_15), + MESON_PIN(GPIODV_16), + MESON_PIN(GPIODV_17), + MESON_PIN(GPIODV_18), + MESON_PIN(GPIODV_19), + MESON_PIN(GPIODV_20), + MESON_PIN(GPIODV_21), + MESON_PIN(GPIODV_22), + MESON_PIN(GPIODV_23), + MESON_PIN(GPIODV_24), + MESON_PIN(GPIODV_25), + MESON_PIN(GPIODV_26), + MESON_PIN(GPIODV_27), + MESON_PIN(GPIODV_28), + MESON_PIN(GPIODV_29), + MESON_PIN(GPIOH_0), + MESON_PIN(GPIOH_1), + MESON_PIN(GPIOH_2), + MESON_PIN(GPIOH_3), + MESON_PIN(GPIOH_4), + MESON_PIN(GPIOH_5), + MESON_PIN(GPIOH_6), + MESON_PIN(GPIOH_7), + MESON_PIN(GPIOH_8), + MESON_PIN(GPIOH_9), + MESON_PIN(GPIOZ_0), + MESON_PIN(GPIOZ_1), + MESON_PIN(GPIOZ_2), + MESON_PIN(GPIOZ_3), + MESON_PIN(GPIOZ_4), + MESON_PIN(GPIOZ_5), + MESON_PIN(GPIOZ_6), + MESON_PIN(GPIOZ_7), + MESON_PIN(GPIOZ_8), + MESON_PIN(GPIOZ_9), + MESON_PIN(GPIOZ_10), + MESON_PIN(GPIOZ_11), + MESON_PIN(GPIOZ_12), + MESON_PIN(GPIOZ_13), + MESON_PIN(GPIOZ_14), + MESON_PIN(CARD_0), + MESON_PIN(CARD_1), + MESON_PIN(CARD_2), + MESON_PIN(CARD_3), + MESON_PIN(CARD_4), + MESON_PIN(CARD_5), + MESON_PIN(CARD_6), + MESON_PIN(BOOT_0), + MESON_PIN(BOOT_1), + MESON_PIN(BOOT_2), + MESON_PIN(BOOT_3), + MESON_PIN(BOOT_4), + MESON_PIN(BOOT_5), + MESON_PIN(BOOT_6), + MESON_PIN(BOOT_7), + MESON_PIN(BOOT_8), + MESON_PIN(BOOT_9), + MESON_PIN(BOOT_10), + MESON_PIN(BOOT_11), + MESON_PIN(BOOT_12), + MESON_PIN(BOOT_13), + MESON_PIN(BOOT_14), + MESON_PIN(BOOT_15), + MESON_PIN(BOOT_16), + MESON_PIN(BOOT_17), + MESON_PIN(BOOT_18), }; static const struct pinctrl_pin_desc meson8_aobus_pins[] = { - MESON_PIN(GPIOAO_0, AO_OFF), - MESON_PIN(GPIOAO_1, AO_OFF), - MESON_PIN(GPIOAO_2, AO_OFF), - MESON_PIN(GPIOAO_3, AO_OFF), - MESON_PIN(GPIOAO_4, AO_OFF), - MESON_PIN(GPIOAO_5, AO_OFF), - MESON_PIN(GPIOAO_6, AO_OFF), - MESON_PIN(GPIOAO_7, AO_OFF), - MESON_PIN(GPIOAO_8, AO_OFF), - MESON_PIN(GPIOAO_9, AO_OFF), - MESON_PIN(GPIOAO_10, AO_OFF), - MESON_PIN(GPIOAO_11, AO_OFF), - MESON_PIN(GPIOAO_12, AO_OFF), - MESON_PIN(GPIOAO_13, AO_OFF), - MESON_PIN(GPIO_BSD_EN, AO_OFF), - MESON_PIN(GPIO_TEST_N, AO_OFF), + MESON_PIN(GPIOAO_0), + MESON_PIN(GPIOAO_1), + MESON_PIN(GPIOAO_2), + MESON_PIN(GPIOAO_3), + MESON_PIN(GPIOAO_4), + MESON_PIN(GPIOAO_5), + MESON_PIN(GPIOAO_6), + MESON_PIN(GPIOAO_7), + MESON_PIN(GPIOAO_8), + MESON_PIN(GPIOAO_9), + MESON_PIN(GPIOAO_10), + MESON_PIN(GPIOAO_11), + MESON_PIN(GPIOAO_12), + MESON_PIN(GPIOAO_13), + MESON_PIN(GPIO_BSD_EN), + MESON_PIN(GPIO_TEST_N), }; /* bank X */ -static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) }; -static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) }; -static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) }; -static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) }; -static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; - -static const unsigned int sdxc_d0_a_pins[] = { PIN(GPIOX_0, 0) }; -static const unsigned int sdxc_d13_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0), - PIN(GPIOX_3, 0) }; -static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0), - PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; -static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; - -static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) }; -static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) }; -static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) }; -static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) }; - -static const unsigned int uart_tx_a0_pins[] = { PIN(GPIOX_4, 0) }; -static const unsigned int uart_rx_a0_pins[] = { PIN(GPIOX_5, 0) }; -static const unsigned int uart_cts_a0_pins[] = { PIN(GPIOX_6, 0) }; -static const unsigned int uart_rts_a0_pins[] = { PIN(GPIOX_7, 0) }; - -static const unsigned int uart_tx_a1_pins[] = { PIN(GPIOX_12, 0) }; -static const unsigned int uart_rx_a1_pins[] = { PIN(GPIOX_13, 0) }; -static const unsigned int uart_cts_a1_pins[] = { PIN(GPIOX_14, 0) }; -static const unsigned int uart_rts_a1_pins[] = { PIN(GPIOX_15, 0) }; - -static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) }; -static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) }; -static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) }; - -static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) }; -static const unsigned int iso7816_clk_pins[] = { PIN(GPIOX_18, 0) }; -static const unsigned int iso7816_data_pins[] = { PIN(GPIOX_19, 0) }; - -static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; - -static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; - -static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_11, 0) }; +static const unsigned int sd_d0_a_pins[] = { GPIOX_0 }; +static const unsigned int sd_d1_a_pins[] = { GPIOX_1 }; +static const unsigned int sd_d2_a_pins[] = { GPIOX_2 }; +static const unsigned int sd_d3_a_pins[] = { GPIOX_3 }; +static const unsigned int sd_clk_a_pins[] = { GPIOX_8 }; +static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 }; + +static const unsigned int sdxc_d0_a_pins[] = { GPIOX_0 }; +static const unsigned int sdxc_d13_a_pins[] = { GPIOX_1, GPIOX_2, GPIOX_3 }; +static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, GPIOX_6, + GPIOX_7 }; +static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 }; +static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 }; + +static const unsigned int pcm_out_a_pins[] = { GPIOX_4 }; +static const unsigned int pcm_in_a_pins[] = { GPIOX_5 }; +static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 }; +static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 }; + +static const unsigned int uart_tx_a0_pins[] = { GPIOX_4 }; +static const unsigned int uart_rx_a0_pins[] = { GPIOX_5 }; +static const unsigned int uart_cts_a0_pins[] = { GPIOX_6 }; +static const unsigned int uart_rts_a0_pins[] = { GPIOX_7 }; + +static const unsigned int uart_tx_a1_pins[] = { GPIOX_12 }; +static const unsigned int uart_rx_a1_pins[] = { GPIOX_13 }; +static const unsigned int uart_cts_a1_pins[] = { GPIOX_14 }; +static const unsigned int uart_rts_a1_pins[] = { GPIOX_15 }; + +static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 }; +static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 }; +static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 }; +static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 }; + +static const unsigned int iso7816_det_pins[] = { GPIOX_16 }; +static const unsigned int iso7816_reset_pins[] = { GPIOX_17 }; +static const unsigned int iso7816_clk_pins[] = { GPIOX_18 }; +static const unsigned int iso7816_data_pins[] = { GPIOX_19 }; + +static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 }; +static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 }; + +static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 }; +static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 }; + +static const unsigned int pwm_e_pins[] = { GPIOX_10 }; +static const unsigned int pwm_b_x_pins[] = { GPIOX_11 }; /* bank Y */ -static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) }; -static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) }; -static const unsigned int uart_cts_c_pins[] = { PIN(GPIOY_2, 0) }; -static const unsigned int uart_rts_c_pins[] = { PIN(GPIOY_3, 0) }; +static const unsigned int uart_tx_c_pins[] = { GPIOY_0 }; +static const unsigned int uart_rx_c_pins[] = { GPIOY_1 }; +static const unsigned int uart_cts_c_pins[] = { GPIOY_2 }; +static const unsigned int uart_rts_c_pins[] = { GPIOY_3 }; -static const unsigned int pcm_out_b_pins[] = { PIN(GPIOY_4, 0) }; -static const unsigned int pcm_in_b_pins[] = { PIN(GPIOY_5, 0) }; -static const unsigned int pcm_fs_b_pins[] = { PIN(GPIOY_6, 0) }; -static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) }; +static const unsigned int pcm_out_b_pins[] = { GPIOY_4 }; +static const unsigned int pcm_in_b_pins[] = { GPIOY_5 }; +static const unsigned int pcm_fs_b_pins[] = { GPIOY_6 }; +static const unsigned int pcm_clk_b_pins[] = { GPIOY_7 }; -static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) }; -static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int i2c_sda_c0_pins[] = { GPIOY_0 }; +static const unsigned int i2c_sck_c0_pins[] = { GPIOY_1 }; -static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, 0) }; +static const unsigned int pwm_a_y_pins[] = { GPIOY_16 }; -static const unsigned int i2s_out_ch45_pins[] = { PIN(GPIOY_0, 0) }; -static const unsigned int i2s_out_ch23_pins[] = { PIN(GPIOY_1, 0) }; -static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOY_4, 0) }; -static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOY_5, 0) }; -static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOY_6, 0) }; -static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOY_7, 0) }; -static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOY_8, 0) }; -static const unsigned int i2s_out_ch78_pins[] = { PIN(GPIOY_9, 0) }; +static const unsigned int i2s_out_ch45_pins[] = { GPIOY_0 }; +static const unsigned int i2s_out_ch23_pins[] = { GPIOY_1 }; +static const unsigned int i2s_out_ch01_pins[] = { GPIOY_4 }; +static const unsigned int i2s_in_ch01_pins[] = { GPIOY_5 }; +static const unsigned int i2s_lr_clk_in_pins[] = { GPIOY_6 }; +static const unsigned int i2s_ao_clk_in_pins[] = { GPIOY_7 }; +static const unsigned int i2s_am_clk_pins[] = { GPIOY_8 }; +static const unsigned int i2s_out_ch78_pins[] = { GPIOY_9 }; -static const unsigned int spdif_in_pins[] = { PIN(GPIOY_2, 0) }; -static const unsigned int spdif_out_pins[] = { PIN(GPIOY_3, 0) }; +static const unsigned int spdif_in_pins[] = { GPIOY_2 }; +static const unsigned int spdif_out_pins[] = { GPIOY_3 }; /* bank DV */ -static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0), - PIN(GPIODV_2, 0), PIN(GPIODV_3, 0), - PIN(GPIODV_4, 0), PIN(GPIODV_5, 0), - PIN(GPIODV_6, 0), PIN(GPIODV_7, 0), - PIN(GPIODV_8, 0), PIN(GPIODV_9, 0), - PIN(GPIODV_10, 0), PIN(GPIODV_11, 0), - PIN(GPIODV_12, 0), PIN(GPIODV_13, 0), - PIN(GPIODV_14, 0), PIN(GPIODV_15, 0), - PIN(GPIODV_16, 0), PIN(GPIODV_17, 0), - PIN(GPIODV_18, 0), PIN(GPIODV_19, 0), - PIN(GPIODV_20, 0), PIN(GPIODV_21, 0), - PIN(GPIODV_22, 0), PIN(GPIODV_23, 0) }; -static const unsigned int dvin_vs_pins[] = { PIN(GPIODV_24, 0) }; -static const unsigned int dvin_hs_pins[] = { PIN(GPIODV_25, 0) }; -static const unsigned int dvin_clk_pins[] = { PIN(GPIODV_26, 0) }; -static const unsigned int dvin_de_pins[] = { PIN(GPIODV_27, 0) }; - -static const unsigned int enc_0_pins[] = { PIN(GPIODV_0, 0) }; -static const unsigned int enc_1_pins[] = { PIN(GPIODV_1, 0) }; -static const unsigned int enc_2_pins[] = { PIN(GPIODV_2, 0) }; -static const unsigned int enc_3_pins[] = { PIN(GPIODV_3, 0) }; -static const unsigned int enc_4_pins[] = { PIN(GPIODV_4, 0) }; -static const unsigned int enc_5_pins[] = { PIN(GPIODV_5, 0) }; -static const unsigned int enc_6_pins[] = { PIN(GPIODV_6, 0) }; -static const unsigned int enc_7_pins[] = { PIN(GPIODV_7, 0) }; -static const unsigned int enc_8_pins[] = { PIN(GPIODV_8, 0) }; -static const unsigned int enc_9_pins[] = { PIN(GPIODV_9, 0) }; -static const unsigned int enc_10_pins[] = { PIN(GPIODV_10, 0) }; -static const unsigned int enc_11_pins[] = { PIN(GPIODV_11, 0) }; -static const unsigned int enc_12_pins[] = { PIN(GPIODV_12, 0) }; -static const unsigned int enc_13_pins[] = { PIN(GPIODV_13, 0) }; -static const unsigned int enc_14_pins[] = { PIN(GPIODV_14, 0) }; -static const unsigned int enc_15_pins[] = { PIN(GPIODV_15, 0) }; -static const unsigned int enc_16_pins[] = { PIN(GPIODV_16, 0) }; -static const unsigned int enc_17_pins[] = { PIN(GPIODV_17, 0) }; - -static const unsigned int uart_tx_b1_pins[] = { PIN(GPIODV_24, 0) }; -static const unsigned int uart_rx_b1_pins[] = { PIN(GPIODV_25, 0) }; -static const unsigned int uart_cts_b1_pins[] = { PIN(GPIODV_26, 0) }; -static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) }; - -static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) }; -static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) }; - -static const unsigned int pwm_c_dv9_pins[] = { PIN(GPIODV_9, 0) }; -static const unsigned int pwm_c_dv29_pins[] = { PIN(GPIODV_29, 0) }; -static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) }; +static const unsigned int dvin_rgb_pins[] = { + GPIODV_0, GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, + GPIODV_6, GPIODV_7, GPIODV_8, GPIODV_9, GPIODV_10, GPIODV_11, + GPIODV_12, GPIODV_13, GPIODV_14, GPIODV_15, GPIODV_16, GPIODV_17, + GPIODV_18, GPIODV_19, GPIODV_20, GPIODV_21, GPIODV_22, GPIODV_23 +}; +static const unsigned int dvin_vs_pins[] = { GPIODV_24 }; +static const unsigned int dvin_hs_pins[] = { GPIODV_25 }; +static const unsigned int dvin_clk_pins[] = { GPIODV_26 }; +static const unsigned int dvin_de_pins[] = { GPIODV_27 }; + +static const unsigned int enc_0_pins[] = { GPIODV_0 }; +static const unsigned int enc_1_pins[] = { GPIODV_1 }; +static const unsigned int enc_2_pins[] = { GPIODV_2 }; +static const unsigned int enc_3_pins[] = { GPIODV_3 }; +static const unsigned int enc_4_pins[] = { GPIODV_4 }; +static const unsigned int enc_5_pins[] = { GPIODV_5 }; +static const unsigned int enc_6_pins[] = { GPIODV_6 }; +static const unsigned int enc_7_pins[] = { GPIODV_7 }; +static const unsigned int enc_8_pins[] = { GPIODV_8 }; +static const unsigned int enc_9_pins[] = { GPIODV_9 }; +static const unsigned int enc_10_pins[] = { GPIODV_10 }; +static const unsigned int enc_11_pins[] = { GPIODV_11 }; +static const unsigned int enc_12_pins[] = { GPIODV_12 }; +static const unsigned int enc_13_pins[] = { GPIODV_13 }; +static const unsigned int enc_14_pins[] = { GPIODV_14 }; +static const unsigned int enc_15_pins[] = { GPIODV_15 }; +static const unsigned int enc_16_pins[] = { GPIODV_16 }; +static const unsigned int enc_17_pins[] = { GPIODV_17 }; + +static const unsigned int uart_tx_b1_pins[] = { GPIODV_24 }; +static const unsigned int uart_rx_b1_pins[] = { GPIODV_25 }; +static const unsigned int uart_cts_b1_pins[] = { GPIODV_26 }; +static const unsigned int uart_rts_b1_pins[] = { GPIODV_27 }; + +static const unsigned int vga_vs_pins[] = { GPIODV_24 }; +static const unsigned int vga_hs_pins[] = { GPIODV_25 }; + +static const unsigned int pwm_c_dv9_pins[] = { GPIODV_9 }; +static const unsigned int pwm_c_dv29_pins[] = { GPIODV_29 }; +static const unsigned int pwm_d_pins[] = { GPIODV_28 }; /* bank H */ -static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; -static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; -static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) }; -static const unsigned int hdmi_cec_pins[] = { PIN(GPIOH_3, 0) }; +static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; +static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; +static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; +static const unsigned int hdmi_cec_pins[] = { GPIOH_3 }; -static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOH_3, 0) }; -static const unsigned int spi_miso_0_pins[] = { PIN(GPIOH_4, 0) }; -static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOH_5, 0) }; -static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOH_6, 0) }; +static const unsigned int spi_ss0_0_pins[] = { GPIOH_3 }; +static const unsigned int spi_miso_0_pins[] = { GPIOH_4 }; +static const unsigned int spi_mosi_0_pins[] = { GPIOH_5 }; +static const unsigned int spi_sclk_0_pins[] = { GPIOH_6 }; -static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) }; -static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) }; +static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 }; +static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 }; /* bank Z */ -static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOZ_9, 0) }; -static const unsigned int spi_ss1_1_pins[] = { PIN(GPIOZ_10, 0) }; -static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOZ_11, 0) }; -static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOZ_12, 0) }; -static const unsigned int spi_miso_1_pins[] = { PIN(GPIOZ_13, 0) }; -static const unsigned int spi_ss2_1_pins[] = { PIN(GPIOZ_14, 0) }; - -static const unsigned int eth_tx_clk_50m_pins[] = { PIN(GPIOZ_4, 0) }; -static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_5, 0) }; -static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_6, 0) }; -static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_7, 0) }; -static const unsigned int eth_rx_clk_in_pins[] = { PIN(GPIOZ_8, 0) }; -static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_9, 0) }; -static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_10, 0) }; -static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_11, 0) }; -static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_12, 0) }; -static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_13, 0) }; - -static const unsigned int i2c_sda_a0_pins[] = { PIN(GPIOZ_0, 0) }; -static const unsigned int i2c_sck_a0_pins[] = { PIN(GPIOZ_1, 0) }; - -static const unsigned int i2c_sda_b_pins[] = { PIN(GPIOZ_2, 0) }; -static const unsigned int i2c_sck_b_pins[] = { PIN(GPIOZ_3, 0) }; - -static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOZ_4, 0) }; -static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOZ_5, 0) }; - -static const unsigned int i2c_sda_a1_pins[] = { PIN(GPIOZ_0, 0) }; -static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) }; - -static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) }; -static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) }; - -static const unsigned int pwm_a_z0_pins[] = { PIN(GPIOZ_0, 0) }; -static const unsigned int pwm_a_z7_pins[] = { PIN(GPIOZ_7, 0) }; -static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_1, 0) }; -static const unsigned int pwm_c_z_pins[] = { PIN(GPIOZ_8, 0) }; +static const unsigned int spi_ss0_1_pins[] = { GPIOZ_9 }; +static const unsigned int spi_ss1_1_pins[] = { GPIOZ_10 }; +static const unsigned int spi_sclk_1_pins[] = { GPIOZ_11 }; +static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 }; +static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 }; +static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 }; + +static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 }; +static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 }; +static const unsigned int eth_txd1_pins[] = { GPIOZ_6 }; +static const unsigned int eth_txd0_pins[] = { GPIOZ_7 }; +static const unsigned int eth_rx_clk_in_pins[] = { GPIOZ_8 }; +static const unsigned int eth_rx_dv_pins[] = { GPIOZ_9 }; +static const unsigned int eth_rxd1_pins[] = { GPIOZ_10 }; +static const unsigned int eth_rxd0_pins[] = { GPIOZ_11 }; +static const unsigned int eth_mdio_pins[] = { GPIOZ_12 }; +static const unsigned int eth_mdc_pins[] = { GPIOZ_13 }; + +static const unsigned int i2c_sda_a0_pins[] = { GPIOZ_0 }; +static const unsigned int i2c_sck_a0_pins[] = { GPIOZ_1 }; + +static const unsigned int i2c_sda_b_pins[] = { GPIOZ_2 }; +static const unsigned int i2c_sck_b_pins[] = { GPIOZ_3 }; + +static const unsigned int i2c_sda_c1_pins[] = { GPIOZ_4 }; +static const unsigned int i2c_sck_c1_pins[] = { GPIOZ_5 }; + +static const unsigned int i2c_sda_a1_pins[] = { GPIOZ_0 }; +static const unsigned int i2c_sck_a1_pins[] = { GPIOZ_1 }; + +static const unsigned int i2c_sda_a2_pins[] = { GPIOZ_0 }; +static const unsigned int i2c_sck_a2_pins[] = { GPIOZ_1 }; + +static const unsigned int pwm_a_z0_pins[] = { GPIOZ_0 }; +static const unsigned int pwm_a_z7_pins[] = { GPIOZ_7 }; +static const unsigned int pwm_b_z_pins[] = { GPIOZ_1 }; +static const unsigned int pwm_c_z_pins[] = { GPIOZ_8 }; /* bank BOOT */ -static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; -static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; -static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) }; -static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) }; -static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_16, 0) }; -static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_17, 0) }; - -static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; -static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0), - PIN(BOOT_3, 0) }; -static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0), - PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; -static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_16, 0) }; -static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_17, 0) }; - -static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0), - PIN(BOOT_2, 0), PIN(BOOT_3, 0), - PIN(BOOT_4, 0), PIN(BOOT_5, 0), - PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; -static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) }; -static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) }; -static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) }; -static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; -static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; -static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; -static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; -static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, 0) }; -static const unsigned int nand_ce2_pins[] = { PIN(BOOT_16, 0) }; -static const unsigned int nand_ce3_pins[] = { PIN(BOOT_17, 0) }; - -static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) }; -static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) }; -static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) }; -static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) }; +static const unsigned int sd_d0_c_pins[] = { BOOT_0 }; +static const unsigned int sd_d1_c_pins[] = { BOOT_1 }; +static const unsigned int sd_d2_c_pins[] = { BOOT_2 }; +static const unsigned int sd_d3_c_pins[] = { BOOT_3 }; +static const unsigned int sd_cmd_c_pins[] = { BOOT_16 }; +static const unsigned int sd_clk_c_pins[] = { BOOT_17 }; + +static const unsigned int sdxc_d0_c_pins[] = { BOOT_0}; +static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, BOOT_3 }; +static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, BOOT_6, + BOOT_7 }; +static const unsigned int sdxc_cmd_c_pins[] = { BOOT_16 }; +static const unsigned int sdxc_clk_c_pins[] = { BOOT_17 }; + +static const unsigned int nand_io_pins[] = { + BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 +}; +static const unsigned int nand_io_ce0_pins[] = { BOOT_8 }; +static const unsigned int nand_io_ce1_pins[] = { BOOT_9 }; +static const unsigned int nand_io_rb0_pins[] = { BOOT_10 }; +static const unsigned int nand_ale_pins[] = { BOOT_11 }; +static const unsigned int nand_cle_pins[] = { BOOT_12 }; +static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; +static const unsigned int nand_ren_clk_pins[] = { BOOT_14 }; +static const unsigned int nand_dqs_pins[] = { BOOT_15 }; +static const unsigned int nand_ce2_pins[] = { BOOT_16 }; +static const unsigned int nand_ce3_pins[] = { BOOT_17 }; + +static const unsigned int nor_d_pins[] = { BOOT_11 }; +static const unsigned int nor_q_pins[] = { BOOT_12 }; +static const unsigned int nor_c_pins[] = { BOOT_13 }; +static const unsigned int nor_cs_pins[] = { BOOT_18 }; /* bank CARD */ -static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) }; -static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) }; -static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) }; -static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) }; -static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) }; -static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) }; - -static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0), - PIN(CARD_5, 0) }; -static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) }; -static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) }; -static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) }; +static const unsigned int sd_d1_b_pins[] = { CARD_0 }; +static const unsigned int sd_d0_b_pins[] = { CARD_1 }; +static const unsigned int sd_clk_b_pins[] = { CARD_2 }; +static const unsigned int sd_cmd_b_pins[] = { CARD_3 }; +static const unsigned int sd_d3_b_pins[] = { CARD_4 }; +static const unsigned int sd_d2_b_pins[] = { CARD_5 }; + +static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, CARD_5 }; +static const unsigned int sdxc_d0_b_pins[] = { CARD_1 }; +static const unsigned int sdxc_clk_b_pins[] = { CARD_2 }; +static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 }; /* bank AO */ -static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) }; -static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) }; -static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; -static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; +static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; +static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; +static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; +static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; -static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; -static const unsigned int remote_output_ao_pins[] = { PIN(GPIOAO_13, AO_OFF) }; +static const unsigned int remote_input_pins[] = { GPIOAO_7 }; +static const unsigned int remote_output_ao_pins[] = { GPIOAO_13 }; -static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int i2c_slave_sck_ao_pins[] = { GPIOAO_4 }; +static const unsigned int i2c_slave_sda_ao_pins[] = { GPIOAO_5 }; -static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) }; -static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) }; +static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 }; +static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 }; -static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 }; +static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 }; -static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 }; +static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 }; -static const unsigned int pwm_f_ao_pins[] = { PIN(GPIO_TEST_N, AO_OFF) }; +static const unsigned int pwm_f_ao_pins[] = { GPIO_TEST_N }; -static const unsigned int i2s_am_clk_out_ao_pins[] = { PIN(GPIOAO_8, AO_OFF) }; -static const unsigned int i2s_ao_clk_out_ao_pins[] = { PIN(GPIOAO_9, AO_OFF) }; -static const unsigned int i2s_lr_clk_out_ao_pins[] = { PIN(GPIOAO_10, AO_OFF) }; -static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, AO_OFF) }; +static const unsigned int i2s_am_clk_out_ao_pins[] = { GPIOAO_8 }; +static const unsigned int i2s_ao_clk_out_ao_pins[] = { GPIOAO_9 }; +static const unsigned int i2s_lr_clk_out_ao_pins[] = { GPIOAO_10 }; +static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 }; -static const unsigned int hdmi_cec_ao_pins[] = { PIN(GPIOAO_12, AO_OFF) }; +static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 }; static struct meson_pmx_group meson8_cbus_groups[] = { - GPIO_GROUP(GPIOX_0, 0), - GPIO_GROUP(GPIOX_1, 0), - GPIO_GROUP(GPIOX_2, 0), - GPIO_GROUP(GPIOX_3, 0), - GPIO_GROUP(GPIOX_4, 0), - GPIO_GROUP(GPIOX_5, 0), - GPIO_GROUP(GPIOX_6, 0), - GPIO_GROUP(GPIOX_7, 0), - GPIO_GROUP(GPIOX_8, 0), - GPIO_GROUP(GPIOX_9, 0), - GPIO_GROUP(GPIOX_10, 0), - GPIO_GROUP(GPIOX_11, 0), - GPIO_GROUP(GPIOX_12, 0), - GPIO_GROUP(GPIOX_13, 0), - GPIO_GROUP(GPIOX_14, 0), - GPIO_GROUP(GPIOX_15, 0), - GPIO_GROUP(GPIOX_16, 0), - GPIO_GROUP(GPIOX_17, 0), - GPIO_GROUP(GPIOX_18, 0), - GPIO_GROUP(GPIOX_19, 0), - GPIO_GROUP(GPIOX_20, 0), - GPIO_GROUP(GPIOX_21, 0), - GPIO_GROUP(GPIOY_0, 0), - GPIO_GROUP(GPIOY_1, 0), - GPIO_GROUP(GPIOY_2, 0), - GPIO_GROUP(GPIOY_3, 0), - GPIO_GROUP(GPIOY_4, 0), - GPIO_GROUP(GPIOY_5, 0), - GPIO_GROUP(GPIOY_6, 0), - GPIO_GROUP(GPIOY_7, 0), - GPIO_GROUP(GPIOY_8, 0), - GPIO_GROUP(GPIOY_9, 0), - GPIO_GROUP(GPIOY_10, 0), - GPIO_GROUP(GPIOY_11, 0), - GPIO_GROUP(GPIOY_12, 0), - GPIO_GROUP(GPIOY_13, 0), - GPIO_GROUP(GPIOY_14, 0), - GPIO_GROUP(GPIOY_15, 0), - GPIO_GROUP(GPIOY_16, 0), - GPIO_GROUP(GPIODV_0, 0), - GPIO_GROUP(GPIODV_1, 0), - GPIO_GROUP(GPIODV_2, 0), - GPIO_GROUP(GPIODV_3, 0), - GPIO_GROUP(GPIODV_4, 0), - GPIO_GROUP(GPIODV_5, 0), - GPIO_GROUP(GPIODV_6, 0), - GPIO_GROUP(GPIODV_7, 0), - GPIO_GROUP(GPIODV_8, 0), - GPIO_GROUP(GPIODV_9, 0), - GPIO_GROUP(GPIODV_10, 0), - GPIO_GROUP(GPIODV_11, 0), - GPIO_GROUP(GPIODV_12, 0), - GPIO_GROUP(GPIODV_13, 0), - GPIO_GROUP(GPIODV_14, 0), - GPIO_GROUP(GPIODV_15, 0), - GPIO_GROUP(GPIODV_16, 0), - GPIO_GROUP(GPIODV_17, 0), - GPIO_GROUP(GPIODV_18, 0), - GPIO_GROUP(GPIODV_19, 0), - GPIO_GROUP(GPIODV_20, 0), - GPIO_GROUP(GPIODV_21, 0), - GPIO_GROUP(GPIODV_22, 0), - GPIO_GROUP(GPIODV_23, 0), - GPIO_GROUP(GPIODV_24, 0), - GPIO_GROUP(GPIODV_25, 0), - GPIO_GROUP(GPIODV_26, 0), - GPIO_GROUP(GPIODV_27, 0), - GPIO_GROUP(GPIODV_28, 0), - GPIO_GROUP(GPIODV_29, 0), - GPIO_GROUP(GPIOH_0, 0), - GPIO_GROUP(GPIOH_1, 0), - GPIO_GROUP(GPIOH_2, 0), - GPIO_GROUP(GPIOH_3, 0), - GPIO_GROUP(GPIOH_4, 0), - GPIO_GROUP(GPIOH_5, 0), - GPIO_GROUP(GPIOH_6, 0), - GPIO_GROUP(GPIOH_7, 0), - GPIO_GROUP(GPIOH_8, 0), - GPIO_GROUP(GPIOH_9, 0), - GPIO_GROUP(GPIOZ_0, 0), - GPIO_GROUP(GPIOZ_1, 0), - GPIO_GROUP(GPIOZ_2, 0), - GPIO_GROUP(GPIOZ_3, 0), - GPIO_GROUP(GPIOZ_4, 0), - GPIO_GROUP(GPIOZ_5, 0), - GPIO_GROUP(GPIOZ_6, 0), - GPIO_GROUP(GPIOZ_7, 0), - GPIO_GROUP(GPIOZ_8, 0), - GPIO_GROUP(GPIOZ_9, 0), - GPIO_GROUP(GPIOZ_10, 0), - GPIO_GROUP(GPIOZ_11, 0), - GPIO_GROUP(GPIOZ_12, 0), - GPIO_GROUP(GPIOZ_13, 0), - GPIO_GROUP(GPIOZ_14, 0), + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + GPIO_GROUP(GPIOX_20), + GPIO_GROUP(GPIOX_21), + GPIO_GROUP(GPIOY_0), + GPIO_GROUP(GPIOY_1), + GPIO_GROUP(GPIOY_2), + GPIO_GROUP(GPIOY_3), + GPIO_GROUP(GPIOY_4), + GPIO_GROUP(GPIOY_5), + GPIO_GROUP(GPIOY_6), + GPIO_GROUP(GPIOY_7), + GPIO_GROUP(GPIOY_8), + GPIO_GROUP(GPIOY_9), + GPIO_GROUP(GPIOY_10), + GPIO_GROUP(GPIOY_11), + GPIO_GROUP(GPIOY_12), + GPIO_GROUP(GPIOY_13), + GPIO_GROUP(GPIOY_14), + GPIO_GROUP(GPIOY_15), + GPIO_GROUP(GPIOY_16), + GPIO_GROUP(GPIODV_0), + GPIO_GROUP(GPIODV_1), + GPIO_GROUP(GPIODV_2), + GPIO_GROUP(GPIODV_3), + GPIO_GROUP(GPIODV_4), + GPIO_GROUP(GPIODV_5), + GPIO_GROUP(GPIODV_6), + GPIO_GROUP(GPIODV_7), + GPIO_GROUP(GPIODV_8), + GPIO_GROUP(GPIODV_9), + GPIO_GROUP(GPIODV_10), + GPIO_GROUP(GPIODV_11), + GPIO_GROUP(GPIODV_12), + GPIO_GROUP(GPIODV_13), + GPIO_GROUP(GPIODV_14), + GPIO_GROUP(GPIODV_15), + GPIO_GROUP(GPIODV_16), + GPIO_GROUP(GPIODV_17), + GPIO_GROUP(GPIODV_18), + GPIO_GROUP(GPIODV_19), + GPIO_GROUP(GPIODV_20), + GPIO_GROUP(GPIODV_21), + GPIO_GROUP(GPIODV_22), + GPIO_GROUP(GPIODV_23), + GPIO_GROUP(GPIODV_24), + GPIO_GROUP(GPIODV_25), + GPIO_GROUP(GPIODV_26), + GPIO_GROUP(GPIODV_27), + GPIO_GROUP(GPIODV_28), + GPIO_GROUP(GPIODV_29), + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + GPIO_GROUP(GPIOH_4), + GPIO_GROUP(GPIOH_5), + GPIO_GROUP(GPIOH_6), + GPIO_GROUP(GPIOH_7), + GPIO_GROUP(GPIOH_8), + GPIO_GROUP(GPIOH_9), + GPIO_GROUP(GPIOZ_0), + GPIO_GROUP(GPIOZ_1), + GPIO_GROUP(GPIOZ_2), + GPIO_GROUP(GPIOZ_3), + GPIO_GROUP(GPIOZ_4), + GPIO_GROUP(GPIOZ_5), + GPIO_GROUP(GPIOZ_6), + GPIO_GROUP(GPIOZ_7), + GPIO_GROUP(GPIOZ_8), + GPIO_GROUP(GPIOZ_9), + GPIO_GROUP(GPIOZ_10), + GPIO_GROUP(GPIOZ_11), + GPIO_GROUP(GPIOZ_12), + GPIO_GROUP(GPIOZ_13), + GPIO_GROUP(GPIOZ_14), /* bank X */ GROUP(sd_d0_a, 8, 5), @@ -727,22 +716,22 @@ static struct meson_pmx_group meson8_cbus_groups[] = { }; static struct meson_pmx_group meson8_aobus_groups[] = { - GPIO_GROUP(GPIOAO_0, AO_OFF), - GPIO_GROUP(GPIOAO_1, AO_OFF), - GPIO_GROUP(GPIOAO_2, AO_OFF), - GPIO_GROUP(GPIOAO_3, AO_OFF), - GPIO_GROUP(GPIOAO_4, AO_OFF), - GPIO_GROUP(GPIOAO_5, AO_OFF), - GPIO_GROUP(GPIOAO_6, AO_OFF), - GPIO_GROUP(GPIOAO_7, AO_OFF), - GPIO_GROUP(GPIOAO_8, AO_OFF), - GPIO_GROUP(GPIOAO_9, AO_OFF), - GPIO_GROUP(GPIOAO_10, AO_OFF), - GPIO_GROUP(GPIOAO_11, AO_OFF), - GPIO_GROUP(GPIOAO_12, AO_OFF), - GPIO_GROUP(GPIOAO_13, AO_OFF), - GPIO_GROUP(GPIO_BSD_EN, AO_OFF), - GPIO_GROUP(GPIO_TEST_N, AO_OFF), + GPIO_GROUP(GPIOAO_0), + GPIO_GROUP(GPIOAO_1), + GPIO_GROUP(GPIOAO_2), + GPIO_GROUP(GPIOAO_3), + GPIO_GROUP(GPIOAO_4), + GPIO_GROUP(GPIOAO_5), + GPIO_GROUP(GPIOAO_6), + GPIO_GROUP(GPIOAO_7), + GPIO_GROUP(GPIOAO_8), + GPIO_GROUP(GPIOAO_9), + GPIO_GROUP(GPIOAO_10), + GPIO_GROUP(GPIOAO_11), + GPIO_GROUP(GPIOAO_12), + GPIO_GROUP(GPIOAO_13), + GPIO_GROUP(GPIO_BSD_EN), + GPIO_GROUP(GPIO_TEST_N), /* bank AO */ GROUP(uart_tx_ao_a, 0, 12), @@ -1041,24 +1030,23 @@ static struct meson_pmx_func meson8_aobus_functions[] = { }; static struct meson_bank meson8_cbus_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), - BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), - BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), - BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), - BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), - BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), + /* name first last irq pullen pull dir out in */ + BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", GPIODV_0, GPIODV_29, 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), + BANK("H", GPIOH_0, GPIOH_9, 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("Z", GPIOZ_0, GPIOZ_14, 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), + BANK("CARD", CARD_0, CARD_6, 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), }; static struct meson_bank meson8_aobus_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first last irq pullen pull dir out in */ + BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; -struct meson_pinctrl_data meson8_cbus_pinctrl_data = { +static struct meson_pinctrl_data meson8_cbus_pinctrl_data = { .name = "cbus-banks", - .pin_base = 0, .pins = meson8_cbus_pins, .groups = meson8_cbus_groups, .funcs = meson8_cbus_functions, @@ -1067,11 +1055,11 @@ struct meson_pinctrl_data meson8_cbus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson8_cbus_groups), .num_funcs = ARRAY_SIZE(meson8_cbus_functions), .num_banks = ARRAY_SIZE(meson8_cbus_banks), + .pmx_ops = &meson8_pmx_ops, }; -struct meson_pinctrl_data meson8_aobus_pinctrl_data = { +static struct meson_pinctrl_data meson8_aobus_pinctrl_data = { .name = "ao-bank", - .pin_base = 120, .pins = meson8_aobus_pins, .groups = meson8_aobus_groups, .funcs = meson8_aobus_functions, @@ -1080,4 +1068,26 @@ struct meson_pinctrl_data meson8_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson8_aobus_groups), .num_funcs = ARRAY_SIZE(meson8_aobus_functions), .num_banks = ARRAY_SIZE(meson8_aobus_banks), + .pmx_ops = &meson8_pmx_ops, +}; + +static const struct of_device_id meson8_pinctrl_dt_match[] = { + { + .compatible = "amlogic,meson8-cbus-pinctrl", + .data = &meson8_cbus_pinctrl_data, + }, + { + .compatible = "amlogic,meson8-aobus-pinctrl", + .data = &meson8_aobus_pinctrl_data, + }, + { }, +}; + +static struct platform_driver meson8_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "meson8-pinctrl", + .of_match_table = meson8_pinctrl_dt_match, + }, }; +builtin_platform_driver(meson8_pinctrl_driver); diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index 71f216b5b0b9..5bd808dc81e1 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -14,408 +14,405 @@ #include <dt-bindings/gpio/meson8b-gpio.h> #include "pinctrl-meson.h" - -#define AO_OFF 130 +#include "pinctrl-meson8-pmx.h" static const struct pinctrl_pin_desc meson8b_cbus_pins[] = { - MESON_PIN(GPIOX_0, 0), - MESON_PIN(GPIOX_1, 0), - MESON_PIN(GPIOX_2, 0), - MESON_PIN(GPIOX_3, 0), - MESON_PIN(GPIOX_4, 0), - MESON_PIN(GPIOX_5, 0), - MESON_PIN(GPIOX_6, 0), - MESON_PIN(GPIOX_7, 0), - MESON_PIN(GPIOX_8, 0), - MESON_PIN(GPIOX_9, 0), - MESON_PIN(GPIOX_10, 0), - MESON_PIN(GPIOX_11, 0), - MESON_PIN(GPIOX_16, 0), - MESON_PIN(GPIOX_17, 0), - MESON_PIN(GPIOX_18, 0), - MESON_PIN(GPIOX_19, 0), - MESON_PIN(GPIOX_20, 0), - MESON_PIN(GPIOX_21, 0), - - MESON_PIN(GPIOY_0, 0), - MESON_PIN(GPIOY_1, 0), - MESON_PIN(GPIOY_3, 0), - MESON_PIN(GPIOY_6, 0), - MESON_PIN(GPIOY_7, 0), - MESON_PIN(GPIOY_8, 0), - MESON_PIN(GPIOY_9, 0), - MESON_PIN(GPIOY_10, 0), - MESON_PIN(GPIOY_11, 0), - MESON_PIN(GPIOY_12, 0), - MESON_PIN(GPIOY_13, 0), - MESON_PIN(GPIOY_14, 0), - - MESON_PIN(GPIODV_9, 0), - MESON_PIN(GPIODV_24, 0), - MESON_PIN(GPIODV_25, 0), - MESON_PIN(GPIODV_26, 0), - MESON_PIN(GPIODV_27, 0), - MESON_PIN(GPIODV_28, 0), - MESON_PIN(GPIODV_29, 0), - - MESON_PIN(GPIOH_0, 0), - MESON_PIN(GPIOH_1, 0), - MESON_PIN(GPIOH_2, 0), - MESON_PIN(GPIOH_3, 0), - MESON_PIN(GPIOH_4, 0), - MESON_PIN(GPIOH_5, 0), - MESON_PIN(GPIOH_6, 0), - MESON_PIN(GPIOH_7, 0), - MESON_PIN(GPIOH_8, 0), - MESON_PIN(GPIOH_9, 0), - - MESON_PIN(CARD_0, 0), - MESON_PIN(CARD_1, 0), - MESON_PIN(CARD_2, 0), - MESON_PIN(CARD_3, 0), - MESON_PIN(CARD_4, 0), - MESON_PIN(CARD_5, 0), - MESON_PIN(CARD_6, 0), - - MESON_PIN(BOOT_0, 0), - MESON_PIN(BOOT_1, 0), - MESON_PIN(BOOT_2, 0), - MESON_PIN(BOOT_3, 0), - MESON_PIN(BOOT_4, 0), - MESON_PIN(BOOT_5, 0), - MESON_PIN(BOOT_6, 0), - MESON_PIN(BOOT_7, 0), - MESON_PIN(BOOT_8, 0), - MESON_PIN(BOOT_9, 0), - MESON_PIN(BOOT_10, 0), - MESON_PIN(BOOT_11, 0), - MESON_PIN(BOOT_12, 0), - MESON_PIN(BOOT_13, 0), - MESON_PIN(BOOT_14, 0), - MESON_PIN(BOOT_15, 0), - MESON_PIN(BOOT_16, 0), - MESON_PIN(BOOT_17, 0), - MESON_PIN(BOOT_18, 0), - - MESON_PIN(DIF_0_P, 0), - MESON_PIN(DIF_0_N, 0), - MESON_PIN(DIF_1_P, 0), - MESON_PIN(DIF_1_N, 0), - MESON_PIN(DIF_2_P, 0), - MESON_PIN(DIF_2_N, 0), - MESON_PIN(DIF_3_P, 0), - MESON_PIN(DIF_3_N, 0), - MESON_PIN(DIF_4_P, 0), - MESON_PIN(DIF_4_N, 0), + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_16), + MESON_PIN(GPIOX_17), + MESON_PIN(GPIOX_18), + MESON_PIN(GPIOX_19), + MESON_PIN(GPIOX_20), + MESON_PIN(GPIOX_21), + + MESON_PIN(GPIOY_0), + MESON_PIN(GPIOY_1), + MESON_PIN(GPIOY_3), + MESON_PIN(GPIOY_6), + MESON_PIN(GPIOY_7), + MESON_PIN(GPIOY_8), + MESON_PIN(GPIOY_9), + MESON_PIN(GPIOY_10), + MESON_PIN(GPIOY_11), + MESON_PIN(GPIOY_12), + MESON_PIN(GPIOY_13), + MESON_PIN(GPIOY_14), + + MESON_PIN(GPIODV_9), + MESON_PIN(GPIODV_24), + MESON_PIN(GPIODV_25), + MESON_PIN(GPIODV_26), + MESON_PIN(GPIODV_27), + MESON_PIN(GPIODV_28), + MESON_PIN(GPIODV_29), + + MESON_PIN(GPIOH_0), + MESON_PIN(GPIOH_1), + MESON_PIN(GPIOH_2), + MESON_PIN(GPIOH_3), + MESON_PIN(GPIOH_4), + MESON_PIN(GPIOH_5), + MESON_PIN(GPIOH_6), + MESON_PIN(GPIOH_7), + MESON_PIN(GPIOH_8), + MESON_PIN(GPIOH_9), + + MESON_PIN(CARD_0), + MESON_PIN(CARD_1), + MESON_PIN(CARD_2), + MESON_PIN(CARD_3), + MESON_PIN(CARD_4), + MESON_PIN(CARD_5), + MESON_PIN(CARD_6), + + MESON_PIN(BOOT_0), + MESON_PIN(BOOT_1), + MESON_PIN(BOOT_2), + MESON_PIN(BOOT_3), + MESON_PIN(BOOT_4), + MESON_PIN(BOOT_5), + MESON_PIN(BOOT_6), + MESON_PIN(BOOT_7), + MESON_PIN(BOOT_8), + MESON_PIN(BOOT_9), + MESON_PIN(BOOT_10), + MESON_PIN(BOOT_11), + MESON_PIN(BOOT_12), + MESON_PIN(BOOT_13), + MESON_PIN(BOOT_14), + MESON_PIN(BOOT_15), + MESON_PIN(BOOT_16), + MESON_PIN(BOOT_17), + MESON_PIN(BOOT_18), + + MESON_PIN(DIF_0_P), + MESON_PIN(DIF_0_N), + MESON_PIN(DIF_1_P), + MESON_PIN(DIF_1_N), + MESON_PIN(DIF_2_P), + MESON_PIN(DIF_2_N), + MESON_PIN(DIF_3_P), + MESON_PIN(DIF_3_N), + MESON_PIN(DIF_4_P), + MESON_PIN(DIF_4_N), }; static const struct pinctrl_pin_desc meson8b_aobus_pins[] = { - MESON_PIN(GPIOAO_0, AO_OFF), - MESON_PIN(GPIOAO_1, AO_OFF), - MESON_PIN(GPIOAO_2, AO_OFF), - MESON_PIN(GPIOAO_3, AO_OFF), - MESON_PIN(GPIOAO_4, AO_OFF), - MESON_PIN(GPIOAO_5, AO_OFF), - MESON_PIN(GPIOAO_6, AO_OFF), - MESON_PIN(GPIOAO_7, AO_OFF), - MESON_PIN(GPIOAO_8, AO_OFF), - MESON_PIN(GPIOAO_9, AO_OFF), - MESON_PIN(GPIOAO_10, AO_OFF), - MESON_PIN(GPIOAO_11, AO_OFF), - MESON_PIN(GPIOAO_12, AO_OFF), - MESON_PIN(GPIOAO_13, AO_OFF), + MESON_PIN(GPIOAO_0), + MESON_PIN(GPIOAO_1), + MESON_PIN(GPIOAO_2), + MESON_PIN(GPIOAO_3), + MESON_PIN(GPIOAO_4), + MESON_PIN(GPIOAO_5), + MESON_PIN(GPIOAO_6), + MESON_PIN(GPIOAO_7), + MESON_PIN(GPIOAO_8), + MESON_PIN(GPIOAO_9), + MESON_PIN(GPIOAO_10), + MESON_PIN(GPIOAO_11), + MESON_PIN(GPIOAO_12), + MESON_PIN(GPIOAO_13), /* * The following 2 pins are not mentionned in the public datasheet * According to this datasheet, they can't be used with the gpio * interrupt controller */ - MESON_PIN(GPIO_BSD_EN, AO_OFF), - MESON_PIN(GPIO_TEST_N, AO_OFF), + MESON_PIN(GPIO_BSD_EN), + MESON_PIN(GPIO_TEST_N), }; /* bank X */ -static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) }; -static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) }; -static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) }; -static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) }; -static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) }; -static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0), - PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; -static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), PIN(GPIOX_6, 0), - PIN(GPIOX_7, 0) }; -static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; -static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) }; -static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) }; -static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) }; - -static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, 0) }; -static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0), - PIN(GPIOX_3, 0) }; -static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) }; -static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) }; -static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) }; -static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) }; -static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, 0) }; - -static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, 0) }; -static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, 0) }; -static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, 0) }; -static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, 0) }; -static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, 0) }; - -static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, 0) }; -static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, 0) }; -static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) }; -static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, 0) }; -static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, 0) }; -static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, 0) }; - -static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, 0) }; -static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, 0) }; -static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, 0) }; -static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, 0) }; -static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) }; -static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; -static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) }; +static const unsigned int sd_d0_a_pins[] = { GPIOX_0 }; +static const unsigned int sd_d1_a_pins[] = { GPIOX_1 }; +static const unsigned int sd_d2_a_pins[] = { GPIOX_2 }; +static const unsigned int sd_d3_a_pins[] = { GPIOX_3 }; +static const unsigned int sdxc_d0_0_a_pins[] = { GPIOX_4 }; +static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, + GPIOX_6, GPIOX_7 }; +static const unsigned int sdxc_d13_0_a_pins[] = { GPIOX_5, GPIOX_6, + GPIOX_7 }; +static const unsigned int sd_clk_a_pins[] = { GPIOX_8 }; +static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 }; +static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 }; +static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 }; +static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 }; +static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 }; +static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 }; +static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 }; + +static const unsigned int sdxc_d0_1_a_pins[] = { GPIOX_0 }; +static const unsigned int sdxc_d13_1_a_pins[] = { GPIOX_1, GPIOX_2, + GPIOX_3 }; +static const unsigned int pcm_out_a_pins[] = { GPIOX_4 }; +static const unsigned int pcm_in_a_pins[] = { GPIOX_5 }; +static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 }; +static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 }; +static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 }; +static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 }; +static const unsigned int pwm_vs_0_pins[] = { GPIOX_10 }; +static const unsigned int pwm_e_pins[] = { GPIOX_10 }; +static const unsigned int pwm_vs_1_pins[] = { GPIOX_11 }; + +static const unsigned int uart_tx_a_pins[] = { GPIOX_4 }; +static const unsigned int uart_rx_a_pins[] = { GPIOX_5 }; +static const unsigned int uart_cts_a_pins[] = { GPIOX_6 }; +static const unsigned int uart_rts_a_pins[] = { GPIOX_7 }; +static const unsigned int uart_tx_b1_pins[] = { GPIOX_8 }; +static const unsigned int uart_rx_b1_pins[] = { GPIOX_9 }; +static const unsigned int uart_cts_b1_pins[] = { GPIOX_10 }; +static const unsigned int uart_rts_b1_pins[] = { GPIOX_20 }; + +static const unsigned int iso7816_0_clk_pins[] = { GPIOX_6 }; +static const unsigned int iso7816_0_data_pins[] = { GPIOX_7 }; +static const unsigned int spi_sclk_0_pins[] = { GPIOX_8 }; +static const unsigned int spi_miso_0_pins[] = { GPIOX_9 }; +static const unsigned int spi_mosi_0_pins[] = { GPIOX_10 }; +static const unsigned int iso7816_det_pins[] = { GPIOX_16 }; +static const unsigned int iso7816_reset_pins[] = { GPIOX_17 }; +static const unsigned int iso7816_1_clk_pins[] = { GPIOX_18 }; +static const unsigned int iso7816_1_data_pins[] = { GPIOX_19 }; +static const unsigned int spi_ss0_0_pins[] = { GPIOX_20 }; + +static const unsigned int tsin_clk_b_pins[] = { GPIOX_8 }; +static const unsigned int tsin_sop_b_pins[] = { GPIOX_9 }; +static const unsigned int tsin_d0_b_pins[] = { GPIOX_10 }; +static const unsigned int pwm_b_pins[] = { GPIOX_11 }; +static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 }; +static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 }; +static const unsigned int tsin_d_valid_b_pins[] = { GPIOX_20 }; /* bank Y */ -static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) }; -static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, 0) }; -static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, 0), PIN(GPIOY_7, 0), - PIN(GPIOY_10, 0), PIN(GPIOY_11, 0), - PIN(GPIOY_12, 0), PIN(GPIOY_13, 0), - PIN(GPIOY_14, 0) }; -static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, 0) }; -static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, 0) }; +static const unsigned int tsin_d_valid_a_pins[] = { GPIOY_0 }; +static const unsigned int tsin_sop_a_pins[] = { GPIOY_1 }; +static const unsigned int tsin_d17_a_pins[] = { + GPIOY_6, GPIOY_7, GPIOY_10, GPIOY_11, GPIOY_12, GPIOY_13, GPIOY_14, +}; +static const unsigned int tsin_clk_a_pins[] = { GPIOY_8 }; +static const unsigned int tsin_d0_a_pins[] = { GPIOY_9 }; -static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, 0) }; +static const unsigned int spdif_out_0_pins[] = { GPIOY_3 }; -static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, 0) }; -static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, 0) }; -static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) }; +static const unsigned int xtal_24m_pins[] = { GPIOY_3 }; +static const unsigned int iso7816_2_clk_pins[] = { GPIOY_13 }; +static const unsigned int iso7816_2_data_pins[] = { GPIOY_14 }; /* bank DV */ -static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) }; -static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int pwm_d_pins[] = { GPIODV_28 }; +static const unsigned int pwm_c0_pins[] = { GPIODV_29 }; -static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, 0) }; -static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, 0) }; -static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int pwm_vs_2_pins[] = { GPIODV_9 }; +static const unsigned int pwm_vs_3_pins[] = { GPIODV_28 }; +static const unsigned int pwm_vs_4_pins[] = { GPIODV_29 }; -static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int xtal24_out_pins[] = { GPIODV_29 }; -static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, 0) }; -static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, 0) }; -static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, 0) }; -static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, 0) }; +static const unsigned int uart_tx_c_pins[] = { GPIODV_24 }; +static const unsigned int uart_rx_c_pins[] = { GPIODV_25 }; +static const unsigned int uart_cts_c_pins[] = { GPIODV_26 }; +static const unsigned int uart_rts_c_pins[] = { GPIODV_27 }; -static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, 0) }; +static const unsigned int pwm_c1_pins[] = { GPIODV_9 }; -static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, 0) }; -static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, 0) }; -static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, 0) }; -static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, 0) }; -static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, 0) }; -static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; +static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; +static const unsigned int i2c_sda_b0_pins[] = { GPIODV_26 }; +static const unsigned int i2c_sck_b0_pins[] = { GPIODV_27 }; +static const unsigned int i2c_sda_c0_pins[] = { GPIODV_28 }; +static const unsigned int i2c_sck_c0_pins[] = { GPIODV_29 }; /* bank H */ -static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; -static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; -static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) }; -static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, 0) }; -static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, 0) }; -static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, 0) }; -static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, 0) }; - -static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, 0) }; -static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, 0) }; -static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, 0) }; -static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, 0) }; -static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, 0) }; -static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, 0) }; - -static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, 0) }; -static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, 0) }; -static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, 0) }; - -static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, 0) }; -static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, 0) }; -static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, 0) }; -static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, 0) }; -static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) }; -static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) }; +static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; +static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; +static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; +static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 }; +static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 }; +static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 }; +static const unsigned int clk_24m_out_pins[] = { GPIOH_9 }; + +static const unsigned int spi_ss1_pins[] = { GPIOH_0 }; +static const unsigned int spi_ss2_pins[] = { GPIOH_1 }; +static const unsigned int spi_ss0_1_pins[] = { GPIOH_3 }; +static const unsigned int spi_miso_1_pins[] = { GPIOH_4 }; +static const unsigned int spi_mosi_1_pins[] = { GPIOH_5 }; +static const unsigned int spi_sclk_1_pins[] = { GPIOH_6 }; + +static const unsigned int eth_txd3_pins[] = { GPIOH_7 }; +static const unsigned int eth_txd2_pins[] = { GPIOH_8 }; +static const unsigned int eth_tx_clk_pins[] = { GPIOH_9 }; + +static const unsigned int i2c_sda_b1_pins[] = { GPIOH_3 }; +static const unsigned int i2c_sck_b1_pins[] = { GPIOH_4 }; +static const unsigned int i2c_sda_c1_pins[] = { GPIOH_5 }; +static const unsigned int i2c_sck_c1_pins[] = { GPIOH_6 }; +static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 }; +static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 }; /* bank BOOT */ -static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0), - PIN(BOOT_2, 0), PIN(BOOT_3, 0), - PIN(BOOT_4, 0), PIN(BOOT_5, 0), - PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; -static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) }; -static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) }; -static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) }; -static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; -static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; -static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; -static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; -static const unsigned int nand_dqs_15_pins[] = { PIN(BOOT_15, 0) }; -static const unsigned int nand_dqs_18_pins[] = { PIN(BOOT_18, 0) }; - -static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; -static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0), - PIN(BOOT_3, 0) }; -static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0), - PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; -static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, 0) }; -static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, 0) }; -static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) }; -static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) }; -static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) }; -static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) }; - -static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; -static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; -static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) }; -static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) }; -static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, 0) }; -static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, 0) }; +static const unsigned int nand_io_pins[] = { + BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 +}; +static const unsigned int nand_io_ce0_pins[] = { BOOT_8 }; +static const unsigned int nand_io_ce1_pins[] = { BOOT_9 }; +static const unsigned int nand_io_rb0_pins[] = { BOOT_10 }; +static const unsigned int nand_ale_pins[] = { BOOT_11 }; +static const unsigned int nand_cle_pins[] = { BOOT_12 }; +static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; +static const unsigned int nand_ren_clk_pins[] = { BOOT_14 }; +static const unsigned int nand_dqs_15_pins[] = { BOOT_15 }; +static const unsigned int nand_dqs_18_pins[] = { BOOT_18 }; + +static const unsigned int sdxc_d0_c_pins[] = { BOOT_0}; +static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, + BOOT_3 }; +static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, + BOOT_6, BOOT_7 }; +static const unsigned int sdxc_clk_c_pins[] = { BOOT_8 }; +static const unsigned int sdxc_cmd_c_pins[] = { BOOT_10 }; +static const unsigned int nor_d_pins[] = { BOOT_11 }; +static const unsigned int nor_q_pins[] = { BOOT_12 }; +static const unsigned int nor_c_pins[] = { BOOT_13 }; +static const unsigned int nor_cs_pins[] = { BOOT_18 }; + +static const unsigned int sd_d0_c_pins[] = { BOOT_0 }; +static const unsigned int sd_d1_c_pins[] = { BOOT_1 }; +static const unsigned int sd_d2_c_pins[] = { BOOT_2 }; +static const unsigned int sd_d3_c_pins[] = { BOOT_3 }; +static const unsigned int sd_cmd_c_pins[] = { BOOT_8 }; +static const unsigned int sd_clk_c_pins[] = { BOOT_10 }; /* bank CARD */ -static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) }; -static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) }; -static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) }; -static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) }; -static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) }; -static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) }; - -static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0), - PIN(CARD_5, 0) }; -static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) }; -static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) }; -static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) }; +static const unsigned int sd_d1_b_pins[] = { CARD_0 }; +static const unsigned int sd_d0_b_pins[] = { CARD_1 }; +static const unsigned int sd_clk_b_pins[] = { CARD_2 }; +static const unsigned int sd_cmd_b_pins[] = { CARD_3 }; +static const unsigned int sd_d3_b_pins[] = { CARD_4 }; +static const unsigned int sd_d2_b_pins[] = { CARD_5 }; + +static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, + CARD_5 }; +static const unsigned int sdxc_d0_b_pins[] = { CARD_1 }; +static const unsigned int sdxc_clk_b_pins[] = { CARD_2 }; +static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 }; /* bank AO */ -static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) }; -static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) }; -static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; -static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; -static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; -static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, AO_OFF) }; -static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; -static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, AO_OFF) }; -static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, AO_OFF) }; - -static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, AO_OFF) }; -static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; -static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, AO_OFF) }; -static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, AO_OFF) }; -static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, AO_OFF) }; -static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, AO_OFF) }; -static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, AO_OFF) }; - -static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) }; -static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) }; -static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, AO_OFF) }; -static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, AO_OFF) }; -static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) }; -static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; -static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, AO_OFF) }; - -static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, AO_OFF) }; -static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, AO_OFF) }; -static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, AO_OFF) }; +static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; +static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; +static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; +static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; +static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 }; +static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 }; +static const unsigned int clk_32k_in_out_pins[] = { GPIOAO_6 }; +static const unsigned int remote_input_pins[] = { GPIOAO_7 }; +static const unsigned int hdmi_cec_1_pins[] = { GPIOAO_12 }; +static const unsigned int ir_blaster_pins[] = { GPIOAO_13 }; + +static const unsigned int pwm_c2_pins[] = { GPIOAO_3 }; +static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 }; +static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 }; +static const unsigned int ir_remote_out_pins[] = { GPIOAO_7 }; +static const unsigned int i2s_am_clk_out_pins[] = { GPIOAO_8 }; +static const unsigned int i2s_ao_clk_out_pins[] = { GPIOAO_9 }; +static const unsigned int i2s_lr_clk_out_pins[] = { GPIOAO_10 }; +static const unsigned int i2s_out_01_pins[] = { GPIOAO_11 }; + +static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 }; +static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 }; +static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 }; +static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 }; +static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 }; +static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 }; +static const unsigned int spdif_out_1_pins[] = { GPIOAO_6 }; + +static const unsigned int i2s_in_ch01_pins[] = { GPIOAO_6 }; +static const unsigned int i2s_ao_clk_in_pins[] = { GPIOAO_9 }; +static const unsigned int i2s_lr_clk_in_pins[] = { GPIOAO_10 }; /* bank DIF */ -static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, 0) }; -static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, 0) }; -static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, 0) }; -static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, 0) }; -static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, 0) }; -static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, 0) }; -static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, 0) }; -static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, 0) }; -static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) }; -static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) }; +static const unsigned int eth_rxd1_pins[] = { DIF_0_P }; +static const unsigned int eth_rxd0_pins[] = { DIF_0_N }; +static const unsigned int eth_rx_dv_pins[] = { DIF_1_P }; +static const unsigned int eth_rx_clk_pins[] = { DIF_1_N }; +static const unsigned int eth_txd0_1_pins[] = { DIF_2_P }; +static const unsigned int eth_txd1_1_pins[] = { DIF_2_N }; +static const unsigned int eth_tx_en_pins[] = { DIF_3_P }; +static const unsigned int eth_ref_clk_pins[] = { DIF_3_N }; +static const unsigned int eth_mdc_pins[] = { DIF_4_P }; +static const unsigned int eth_mdio_en_pins[] = { DIF_4_N }; static struct meson_pmx_group meson8b_cbus_groups[] = { - GPIO_GROUP(GPIOX_0, 0), - GPIO_GROUP(GPIOX_1, 0), - GPIO_GROUP(GPIOX_2, 0), - GPIO_GROUP(GPIOX_3, 0), - GPIO_GROUP(GPIOX_4, 0), - GPIO_GROUP(GPIOX_5, 0), - GPIO_GROUP(GPIOX_6, 0), - GPIO_GROUP(GPIOX_7, 0), - GPIO_GROUP(GPIOX_8, 0), - GPIO_GROUP(GPIOX_9, 0), - GPIO_GROUP(GPIOX_10, 0), - GPIO_GROUP(GPIOX_11, 0), - GPIO_GROUP(GPIOX_16, 0), - GPIO_GROUP(GPIOX_17, 0), - GPIO_GROUP(GPIOX_18, 0), - GPIO_GROUP(GPIOX_19, 0), - GPIO_GROUP(GPIOX_20, 0), - GPIO_GROUP(GPIOX_21, 0), - - GPIO_GROUP(GPIOY_0, 0), - GPIO_GROUP(GPIOY_1, 0), - GPIO_GROUP(GPIOY_3, 0), - GPIO_GROUP(GPIOY_6, 0), - GPIO_GROUP(GPIOY_7, 0), - GPIO_GROUP(GPIOY_8, 0), - GPIO_GROUP(GPIOY_9, 0), - GPIO_GROUP(GPIOY_10, 0), - GPIO_GROUP(GPIOY_11, 0), - GPIO_GROUP(GPIOY_12, 0), - GPIO_GROUP(GPIOY_13, 0), - GPIO_GROUP(GPIOY_14, 0), - - GPIO_GROUP(GPIODV_9, 0), - GPIO_GROUP(GPIODV_24, 0), - GPIO_GROUP(GPIODV_25, 0), - GPIO_GROUP(GPIODV_26, 0), - GPIO_GROUP(GPIODV_27, 0), - GPIO_GROUP(GPIODV_28, 0), - GPIO_GROUP(GPIODV_29, 0), - - GPIO_GROUP(GPIOH_0, 0), - GPIO_GROUP(GPIOH_1, 0), - GPIO_GROUP(GPIOH_2, 0), - GPIO_GROUP(GPIOH_3, 0), - GPIO_GROUP(GPIOH_4, 0), - GPIO_GROUP(GPIOH_5, 0), - GPIO_GROUP(GPIOH_6, 0), - GPIO_GROUP(GPIOH_7, 0), - GPIO_GROUP(GPIOH_8, 0), - GPIO_GROUP(GPIOH_9, 0), - - GPIO_GROUP(DIF_0_P, 0), - GPIO_GROUP(DIF_0_N, 0), - GPIO_GROUP(DIF_1_P, 0), - GPIO_GROUP(DIF_1_N, 0), - GPIO_GROUP(DIF_2_P, 0), - GPIO_GROUP(DIF_2_N, 0), - GPIO_GROUP(DIF_3_P, 0), - GPIO_GROUP(DIF_3_N, 0), - GPIO_GROUP(DIF_4_P, 0), - GPIO_GROUP(DIF_4_N, 0), + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + GPIO_GROUP(GPIOX_20), + GPIO_GROUP(GPIOX_21), + + GPIO_GROUP(GPIOY_0), + GPIO_GROUP(GPIOY_1), + GPIO_GROUP(GPIOY_3), + GPIO_GROUP(GPIOY_6), + GPIO_GROUP(GPIOY_7), + GPIO_GROUP(GPIOY_8), + GPIO_GROUP(GPIOY_9), + GPIO_GROUP(GPIOY_10), + GPIO_GROUP(GPIOY_11), + GPIO_GROUP(GPIOY_12), + GPIO_GROUP(GPIOY_13), + GPIO_GROUP(GPIOY_14), + + GPIO_GROUP(GPIODV_9), + GPIO_GROUP(GPIODV_24), + GPIO_GROUP(GPIODV_25), + GPIO_GROUP(GPIODV_26), + GPIO_GROUP(GPIODV_27), + GPIO_GROUP(GPIODV_28), + GPIO_GROUP(GPIODV_29), + + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + GPIO_GROUP(GPIOH_4), + GPIO_GROUP(GPIOH_5), + GPIO_GROUP(GPIOH_6), + GPIO_GROUP(GPIOH_7), + GPIO_GROUP(GPIOH_8), + GPIO_GROUP(GPIOH_9), + + GPIO_GROUP(DIF_0_P), + GPIO_GROUP(DIF_0_N), + GPIO_GROUP(DIF_1_P), + GPIO_GROUP(DIF_1_N), + GPIO_GROUP(DIF_2_P), + GPIO_GROUP(DIF_2_N), + GPIO_GROUP(DIF_3_P), + GPIO_GROUP(DIF_3_N), + GPIO_GROUP(DIF_4_P), + GPIO_GROUP(DIF_4_N), /* bank X */ GROUP(sd_d0_a, 8, 5), @@ -577,22 +574,22 @@ static struct meson_pmx_group meson8b_cbus_groups[] = { }; static struct meson_pmx_group meson8b_aobus_groups[] = { - GPIO_GROUP(GPIOAO_0, AO_OFF), - GPIO_GROUP(GPIOAO_1, AO_OFF), - GPIO_GROUP(GPIOAO_2, AO_OFF), - GPIO_GROUP(GPIOAO_3, AO_OFF), - GPIO_GROUP(GPIOAO_4, AO_OFF), - GPIO_GROUP(GPIOAO_5, AO_OFF), - GPIO_GROUP(GPIOAO_6, AO_OFF), - GPIO_GROUP(GPIOAO_7, AO_OFF), - GPIO_GROUP(GPIOAO_8, AO_OFF), - GPIO_GROUP(GPIOAO_9, AO_OFF), - GPIO_GROUP(GPIOAO_10, AO_OFF), - GPIO_GROUP(GPIOAO_11, AO_OFF), - GPIO_GROUP(GPIOAO_12, AO_OFF), - GPIO_GROUP(GPIOAO_13, AO_OFF), - GPIO_GROUP(GPIO_BSD_EN, AO_OFF), - GPIO_GROUP(GPIO_TEST_N, AO_OFF), + GPIO_GROUP(GPIOAO_0), + GPIO_GROUP(GPIOAO_1), + GPIO_GROUP(GPIOAO_2), + GPIO_GROUP(GPIOAO_3), + GPIO_GROUP(GPIOAO_4), + GPIO_GROUP(GPIOAO_5), + GPIO_GROUP(GPIOAO_6), + GPIO_GROUP(GPIOAO_7), + GPIO_GROUP(GPIOAO_8), + GPIO_GROUP(GPIOAO_9), + GPIO_GROUP(GPIOAO_10), + GPIO_GROUP(GPIOAO_11), + GPIO_GROUP(GPIOAO_12), + GPIO_GROUP(GPIOAO_13), + GPIO_GROUP(GPIO_BSD_EN), + GPIO_GROUP(GPIO_TEST_N), /* bank AO */ GROUP(uart_tx_ao_a, 0, 12), @@ -887,30 +884,29 @@ static struct meson_pmx_func meson8b_aobus_functions[] = { }; static struct meson_bank meson8b_cbus_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 97, 118, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), - BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 80, 96, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 59, 79, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), - BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), - BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), - BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), + /* name first last irq pullen pull dir out in */ + BANK("X", GPIOX_0, GPIOX_21, 97, 118, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", GPIOY_0, GPIOY_14, 80, 96, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", GPIODV_9, GPIODV_29, 59, 79, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), + BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), /* * The following bank is not mentionned in the public datasheet * There is no information whether it can be used with the gpio * interrupt controller */ - BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), + BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), }; static struct meson_bank meson8b_aobus_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first lastc irq pullen pull dir out in */ + BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; -struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { +static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { .name = "cbus-banks", - .pin_base = 0, .pins = meson8b_cbus_pins, .groups = meson8b_cbus_groups, .funcs = meson8b_cbus_functions, @@ -919,11 +915,11 @@ struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson8b_cbus_groups), .num_funcs = ARRAY_SIZE(meson8b_cbus_functions), .num_banks = ARRAY_SIZE(meson8b_cbus_banks), + .pmx_ops = &meson8_pmx_ops, }; -struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { +static struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { .name = "aobus-banks", - .pin_base = 130, .pins = meson8b_aobus_pins, .groups = meson8b_aobus_groups, .funcs = meson8b_aobus_functions, @@ -932,4 +928,26 @@ struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { .num_groups = ARRAY_SIZE(meson8b_aobus_groups), .num_funcs = ARRAY_SIZE(meson8b_aobus_functions), .num_banks = ARRAY_SIZE(meson8b_aobus_banks), + .pmx_ops = &meson8_pmx_ops, +}; + +static const struct of_device_id meson8b_pinctrl_dt_match[] = { + { + .compatible = "amlogic,meson8b-cbus-pinctrl", + .data = &meson8b_cbus_pinctrl_data, + }, + { + .compatible = "amlogic,meson8b-aobus-pinctrl", + .data = &meson8b_aobus_pinctrl_data, + }, + { }, +}; + +static struct platform_driver meson8b_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "meson8b-pinctrl", + .of_match_table = meson8b_pinctrl_dt_match, + }, }; +builtin_platform_driver(meson8b_pinctrl_driver); diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile index 5b03fd55e28d..cd082dca4482 100644 --- a/drivers/pinctrl/mvebu/Makefile +++ b/drivers/pinctrl/mvebu/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 71b944748304..d45af31b86b4 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -576,6 +576,19 @@ static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_FALLING: val |= (BIT(d->hwirq % GPIO_PER_REG)); break; + case IRQ_TYPE_EDGE_BOTH: { + u32 in_val, in_reg = INPUT_VAL; + + armada_37xx_irq_update_reg(&in_reg, d); + regmap_read(info->regmap, in_reg, &in_val); + + /* Set initial polarity based on current input level. */ + if (in_val & d->mask) + val |= d->mask; /* falling */ + else + val &= ~d->mask; /* rising */ + break; + } default: spin_unlock_irqrestore(&info->irq_lock, flags); return -EINVAL; @@ -586,13 +599,47 @@ static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) return 0; } +static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info, + u32 pin_idx) +{ + u32 reg_idx = pin_idx / GPIO_PER_REG; + u32 bit_num = pin_idx % GPIO_PER_REG; + u32 p, l, ret; + unsigned long flags; + + regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l); + + spin_lock_irqsave(&info->irq_lock, flags); + p = readl(info->base + IRQ_POL + 4 * reg_idx); + if ((p ^ l) & (1 << bit_num)) { + /* + * For the gpios which are used for both-edge irqs, when their + * interrupts happen, their input levels are changed, + * yet their interrupt polarities are kept in old values, we + * should synchronize their interrupt polarities; for example, + * at first a gpio's input level is low and its interrupt + * polarity control is "Detect rising edge", then the gpio has + * a interrupt , its level turns to high, we should change its + * polarity control to "Detect falling edge" correspondingly. + */ + p ^= 1 << bit_num; + writel(p, info->base + IRQ_POL + 4 * reg_idx); + ret = 0; + } else { + /* Spurious irq */ + ret = -1; + } + + spin_unlock_irqrestore(&info->irq_lock, flags); + return ret; +} static void armada_37xx_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); - struct irq_domain *d = gc->irqdomain; + struct irq_domain *d = gc->irq.domain; int i; chained_irq_enter(chip, desc); @@ -609,6 +656,23 @@ static void armada_37xx_irq_handler(struct irq_desc *desc) u32 hwirq = ffs(status) - 1; u32 virq = irq_find_mapping(d, hwirq + i * GPIO_PER_REG); + u32 t = irq_get_trigger_type(virq); + + if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { + /* Swap polarity (race with GPIO line) */ + if (armada_37xx_edge_both_irq_swap_pol(info, + hwirq + i * GPIO_PER_REG)) { + /* + * For spurious irq, which gpio level + * is not as expected after incoming + * edge, just ack the gpio irq. + */ + writel(1 << hwirq, + info->base + + IRQ_STATUS + 4 * i); + continue; + } + } generic_handle_irq(virq); @@ -626,15 +690,13 @@ static void armada_37xx_irq_handler(struct irq_desc *desc) static unsigned int armada_37xx_irq_startup(struct irq_data *d) { - struct gpio_chip *chip = irq_data_get_irq_chip_data(d); - int irq = d->hwirq - chip->irq_base; /* * The mask field is a "precomputed bitmask for accessing the * chip registers" which was introduced for the generic * irqchip framework. As we don't use this framework, we can * reuse this field for our own usage. */ - d->mask = BIT(irq % GPIO_PER_REG); + d->mask = BIT(d->hwirq % GPIO_PER_REG); armada_37xx_irq_unmask(d); diff --git a/drivers/pinctrl/nomadik/Makefile b/drivers/pinctrl/nomadik/Makefile index 30b27f18cd52..bf8b7517ee4a 100644 --- a/drivers/pinctrl/nomadik/Makefile +++ b/drivers/pinctrl/nomadik/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Nomadik family pin control drivers obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.h b/drivers/pinctrl/nomadik/pinctrl-abx500.h index 2beef3bfe9ca..43f9b718a8ef 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.h +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef PINCTRL_PINCTRL_ABx500_H #define PINCTRL_PINCTRL_ABx500_H diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c index af4814479eb0..726c0b5501fa 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include <linux/kernel.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-nomadik.h" diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c index 2860eafd1b42..ae3ac7b799a6 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include <linux/kernel.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-nomadik.h" diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c index e852048c4c04..7e814764da7d 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include <linux/kernel.h> #include <linux/pinctrl/pinctrl.h> #include "pinctrl-nomadik.h" diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index a53f1a9b1ed2..f0e7a8c114b2 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -413,7 +413,7 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) u32 falling = nmk_chip->fimsc & BIT(offset); u32 rising = nmk_chip->rimsc & BIT(offset); int gpio = nmk_chip->chip.base + offset; - int irq = irq_find_mapping(nmk_chip->chip.irqdomain, offset); + int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset); struct irq_data *d = irq_get_irq_data(irq); if (!rising && !falling) @@ -815,7 +815,7 @@ static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) while (status) { int bit = __ffs(status); - generic_handle_irq(irq_find_mapping(chip->irqdomain, bit)); + generic_handle_irq(irq_find_mapping(chip->irq.domain, bit)); status &= ~BIT(bit); } diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.h b/drivers/pinctrl/nomadik/pinctrl-nomadik.h index 30bba2a75a58..ae0bac06639f 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.h +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef PINCTRL_PINCTRL_NOMADIK_H #define PINCTRL_PINCTRL_NOMADIK_H diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 8eaa25c3384f..b4f7f8a458ea 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -49,6 +49,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), + PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true), }; static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, @@ -181,6 +182,7 @@ static const struct pinconf_generic_params dt_params[] = { { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, + { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 }, }; /** diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 3f6b34febbf1..61d830c2bc17 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -532,10 +532,18 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) regval = readl(regs + i); if (!(regval & PIN_IRQ_PENDING)) continue; - irq = irq_find_mapping(gc->irqdomain, irqnr + i); + irq = irq_find_mapping(gc->irq.domain, irqnr + i); generic_handle_irq(irq); - /* Clear interrupt */ + + /* Clear interrupt. + * We must read the pin register again, in case the + * value was changed while executing + * generic_handle_irq() above. + */ + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + regval = readl(regs + i); writel(regval, regs + i); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); ret = IRQ_HANDLED; } } @@ -745,7 +753,7 @@ static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) return false; } -int amd_gpio_suspend(struct device *dev) +static int amd_gpio_suspend(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); @@ -764,7 +772,7 @@ int amd_gpio_suspend(struct device *dev) return 0; } -int amd_gpio_resume(struct device *dev) +static int amd_gpio_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 569bc28cb909..03492e3c09fa 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1603,7 +1603,7 @@ static void gpio_irq_handler(struct irq_desc *desc) for_each_set_bit(n, &isr, BITS_PER_LONG) { generic_handle_irq(irq_find_mapping( - gpio_chip->irqdomain, n)); + gpio_chip->irq.domain, n)); } } chained_irq_exit(chip, desc); diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index ac155e7d3412..7939b178c6ae 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -517,7 +517,7 @@ static void u300_gpio_irq_handler(struct irq_desc *desc) for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { int offset = pinoffset + irqoffset; - int pin_irq = irq_find_mapping(chip->irqdomain, offset); + int pin_irq = irq_find_mapping(chip->irq.domain, offset); dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", pin_irq, offset); diff --git a/drivers/pinctrl/pinctrl-coh901.h b/drivers/pinctrl/pinctrl-coh901.h index 87294222583e..ba2678665168 100644 --- a/drivers/pinctrl/pinctrl-coh901.h +++ b/drivers/pinctrl/pinctrl-coh901.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 */ int u300_gpio_config_get(struct gpio_chip *chip, unsigned offset, unsigned long *config); diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index 39e6221e7100..e9b83e291edf 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -13,6 +13,8 @@ #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/regmap.h> @@ -22,6 +24,19 @@ #define DRIVER_NAME "pinctrl-gemini" /** + * struct gemini_pin_conf - information about configuring a pin + * @pin: the pin number + * @reg: config register + * @mask: the bits affecting the configuration of the pin + */ +struct gemini_pin_conf { + unsigned int pin; + u32 reg; + u32 mask; +}; + +/** + * struct gemini_pmx - state holder for the gemini pin controller * @dev: a pointer back to containing device * @virtbase: the offset to the controller in virtual memory * @map: regmap to access registers @@ -29,6 +44,8 @@ * @is_3516: whether the SoC/package is the 3516 variant * @flash_pin: whether the flash pin (extended pins for parallel * flash) is set + * @confs: pin config information + * @nconfs: number of pin config information items */ struct gemini_pmx { struct device *dev; @@ -37,6 +54,8 @@ struct gemini_pmx { bool is_3512; bool is_3516; bool flash_pin; + const struct gemini_pin_conf *confs; + unsigned int nconfs; }; /** @@ -57,6 +76,13 @@ struct gemini_pin_group { u32 value; }; +/* Some straight-forward control registers */ +#define GLOBAL_WORD_ID 0x00 +#define GLOBAL_STATUS 0x04 +#define GLOBAL_STATUS_FLPIN BIT(20) +#define GLOBAL_GMAC_CTRL_SKEW 0x1c +#define GLOBAL_GMAC0_DATA_SKEW 0x20 +#define GLOBAL_GMAC1_DATA_SKEW 0x24 /* * Global Miscellaneous Control Register * This register controls all Gemini pad/pin multiplexing @@ -69,10 +95,14 @@ struct gemini_pin_group { * DISABLED again. So you select a flash configuration once, and then * you are stuck with it. */ -#define GLOBAL_WORD_ID 0x00 -#define GLOBAL_STATUS 0x04 -#define GLOBAL_STATUS_FLPIN BIT(20) #define GLOBAL_MISC_CTRL 0x30 +#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27) +/* Not really used */ +#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28) +/* Activated with GMAC1 */ +#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27) +/* This will be the default */ +#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0 #define TVC_CLK_PAD_ENABLE BIT(20) #define PCI_CLK_PAD_ENABLE BIT(17) #define LPC_CLK_PAD_ENABLE BIT(16) @@ -86,8 +116,8 @@ struct gemini_pin_group { #define NAND_PADS_DISABLE BIT(2) #define PFLASH_PADS_DISABLE BIT(1) #define SFLASH_PADS_DISABLE BIT(0) -#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20)) -#define PADS_MAXBIT 20 +#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27)) +#define PADS_MAXBIT 27 /* Ordered by bit index */ static const char * const gemini_padgroups[] = { @@ -106,6 +136,8 @@ static const char * const gemini_padgroups[] = { "PCI CLK", NULL, NULL, "TVC CLK", + NULL, NULL, NULL, NULL, NULL, + "GMAC1", }; static const struct pinctrl_pin_desc gemini_3512_pins[] = { @@ -493,9 +525,12 @@ static const unsigned int usb_3512_pins[] = { }; /* GMII, ethernet pins */ -static const unsigned int gmii_3512_pins[] = { - 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296, - 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281 +static const unsigned int gmii_gmac0_3512_pins[] = { + 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313 +}; + +static const unsigned int gmii_gmac1_3512_pins[] = { + 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317 }; static const unsigned int pci_3512_pins[] = { @@ -645,10 +680,10 @@ static const unsigned int gpio1c_3512_pins[] = { /* The GPIO1D (28-31) pins overlap with LCD and TVC */ static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; -/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ +/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; -/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ +/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; /* The GPIO2C (8-31) pins overlap with PCI */ @@ -715,9 +750,16 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = { .num_pins = ARRAY_SIZE(usb_3512_pins), }, { - .name = "gmiigrp", - .pins = gmii_3512_pins, - .num_pins = ARRAY_SIZE(gmii_3512_pins), + .name = "gmii_gmac0_grp", + .pins = gmii_gmac0_3512_pins, + .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), + }, + { + .name = "gmii_gmac1_grp", + .pins = gmii_gmac1_3512_pins, + .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), + /* Bring out RGMII on the GMAC1 pins */ + .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, }, { .name = "pcigrp", @@ -931,14 +973,15 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = { .name = "gpio2agrp", .pins = gpio2a_3512_pins, .num_pins = ARRAY_SIZE(gpio2a_3512_pins), - /* Conflict with GMII and extended parallel flash */ + .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, + /* Conflict with GMII GMAC1 and extended parallel flash */ }, { .name = "gpio2bgrp", .pins = gpio2b_3512_pins, .num_pins = ARRAY_SIZE(gpio2b_3512_pins), - /* Conflict with GMII, extended parallel flash and LCD */ - .mask = LCD_PADS_ENABLE, + /* Conflict with GMII GMAC1, extended parallel flash and LCD */ + .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, }, { .name = "gpio2cgrp", @@ -1418,9 +1461,12 @@ static const unsigned int usb_3516_pins[] = { }; /* GMII, ethernet pins */ -static const unsigned int gmii_3516_pins[] = { - 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347, - 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391 +static const unsigned int gmii_gmac0_3516_pins[] = { + 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387 +}; + +static const unsigned int gmii_gmac1_3516_pins[] = { + 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391 }; static const unsigned int pci_3516_pins[] = { @@ -1562,10 +1608,10 @@ static const unsigned int gpio1c_3516_pins[] = { /* The GPIO1D (28-31) pins overlap with TVC */ static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; -/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ +/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; -/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ +/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; /* The GPIO2C (8-31) pins overlap with PCI */ @@ -1637,9 +1683,16 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = { .num_pins = ARRAY_SIZE(usb_3516_pins), }, { - .name = "gmiigrp", - .pins = gmii_3516_pins, - .num_pins = ARRAY_SIZE(gmii_3516_pins), + .name = "gmii_gmac0_grp", + .pins = gmii_gmac0_3516_pins, + .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), + }, + { + .name = "gmii_gmac1_grp", + .pins = gmii_gmac1_3516_pins, + .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), + /* Bring out RGMII on the GMAC1 pins */ + .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, }, { .name = "pcigrp", @@ -1838,14 +1891,15 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = { .name = "gpio2agrp", .pins = gpio2a_3516_pins, .num_pins = ARRAY_SIZE(gpio2a_3516_pins), - /* Conflict with GMII and extended parallel flash */ + .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, + /* Conflict with GMII GMAC1 and extended parallel flash */ }, { .name = "gpio2bgrp", .pins = gpio2b_3516_pins, .num_pins = ARRAY_SIZE(gpio2b_3516_pins), - /* Conflict with GMII, extended parallel flash and LCD */ - .mask = LCD_PADS_ENABLE, + /* Conflict with GMII GMAC1, extended parallel flash and LCD */ + .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, }, { .name = "gpio2cgrp", @@ -1918,73 +1972,13 @@ static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, " " DRIVER_NAME); } -static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, - unsigned int *reserved_maps, - unsigned int *num_maps) -{ - int ret; - const char *function = NULL; - const char *group; - struct property *prop; - - ret = of_property_read_string(np, "function", &function); - if (ret < 0) - return ret; - - ret = of_property_count_strings(np, "groups"); - if (ret < 0) - return ret; - - ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, - num_maps, ret); - if (ret < 0) - return ret; - - of_property_for_each_string(np, "groups", prop, group) { - ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, - num_maps, group, function); - if (ret < 0) - return ret; - pr_debug("ADDED FUNCTION %s <-> GROUP %s\n", - function, group); - } - - return 0; -} - -static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - unsigned int *num_maps) -{ - unsigned int reserved_maps = 0; - struct device_node *np; - int ret; - - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map, - &reserved_maps, num_maps); - if (ret < 0) { - pinctrl_utils_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; -}; - static const struct pinctrl_ops gemini_pctrl_ops = { .get_groups_count = gemini_get_groups_count, .get_group_name = gemini_get_group_name, .get_group_pins = gemini_get_group_pins, .pin_dbg_show = gemini_pin_dbg_show, - .dt_node_to_map = gemini_pinctrl_dt_node_to_map, - .dt_free_map = pinctrl_utils_free_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, }; /** @@ -2008,7 +2002,7 @@ static const char * const icegrps[] = { "icegrp" }; static const char * const idegrps[] = { "idegrp" }; static const char * const satagrps[] = { "satagrp" }; static const char * const usbgrps[] = { "usbgrp" }; -static const char * const gmiigrps[] = { "gmiigrp" }; +static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" }; static const char * const pcigrps[] = { "pcigrp" }; static const char * const lpcgrps[] = { "lpcgrp" }; static const char * const lcdgrps[] = { "lcdgrp" }; @@ -2074,6 +2068,16 @@ static const struct gemini_pmx_func gemini_pmx_functions[] = { .num_groups = ARRAY_SIZE(satagrps), }, { + .name = "usb", + .groups = usbgrps, + .num_groups = ARRAY_SIZE(usbgrps), + }, + { + .name = "gmii", + .groups = gmiigrps, + .num_groups = ARRAY_SIZE(gmiigrps), + }, + { .name = "pci", .groups = pcigrps, .num_groups = ARRAY_SIZE(pcigrps), @@ -2251,10 +2255,155 @@ static const struct pinmux_ops gemini_pmx_ops = { .set_mux = gemini_pmx_set_mux, }; +#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \ + .pin = _n, \ + .reg = _r, \ + .mask = GENMASK(_hb, _lb) \ +} + +static const struct gemini_pin_conf gemini_confs_3512[] = { + GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ + GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ + GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ + GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ + GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ + GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ + GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ + GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ + GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ + GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ + GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ + GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ + GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ + GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ + GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ + GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ + GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ + GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ + GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ + GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ + GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ + GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ + GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ + GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ +}; + +static const struct gemini_pin_conf gemini_confs_3516[] = { + GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */ + GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */ + GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */ + GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */ + GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */ + GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */ + GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */ + GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */ + GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */ + GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */ + GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */ + GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */ + GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */ + GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */ + GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */ + GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */ + GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */ + GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */ + GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */ + GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */ + GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */ + GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */ + GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */ + GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */ +}; + +static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx, + unsigned int pin) +{ + const struct gemini_pin_conf *retconf; + int i; + + for (i = 0; i < pmx->nconfs; i++) { + retconf = &gemini_confs_3516[i]; + if (retconf->pin == pin) + return retconf; + } + return NULL; +} + +static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + const struct gemini_pin_conf *conf; + u32 val; + + switch (param) { + case PIN_CONFIG_SKEW_DELAY: + conf = gemini_get_pin_conf(pmx, pin); + if (!conf) + return -ENOTSUPP; + regmap_read(pmx->map, conf->reg, &val); + val &= conf->mask; + val >>= (ffs(conf->mask) - 1); + *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val); + break; + default: + return -ENOTSUPP; + } + + return 0; +} + +static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct gemini_pin_conf *conf; + enum pin_config_param param; + u32 arg; + int ret = 0; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_SKEW_DELAY: + if (arg > 0xf) + return -EINVAL; + conf = gemini_get_pin_conf(pmx, pin); + if (!conf) { + dev_err(pmx->dev, + "invalid pin for skew delay %d\n", pin); + return -ENOTSUPP; + } + arg <<= (ffs(conf->mask) - 1); + dev_dbg(pmx->dev, + "set pin %d to skew delay mask %08x, val %08x\n", + pin, conf->mask, arg); + regmap_update_bits(pmx->map, conf->reg, conf->mask, arg); + break; + default: + dev_err(pmx->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + } + + return ret; +} + +static const struct pinconf_ops gemini_pinconf_ops = { + .pin_config_get = gemini_pinconf_get, + .pin_config_set = gemini_pinconf_set, + .is_generic = true, +}; + static struct pinctrl_desc gemini_pmx_desc = { .name = DRIVER_NAME, .pctlops = &gemini_pctrl_ops, .pmxops = &gemini_pmx_ops, + .confops = &gemini_pinconf_ops, .owner = THIS_MODULE, }; @@ -2297,11 +2446,15 @@ static int gemini_pmx_probe(struct platform_device *pdev) val &= 0xffff; if (val == 0x3512) { pmx->is_3512 = true; + pmx->confs = gemini_confs_3512; + pmx->nconfs = ARRAY_SIZE(gemini_confs_3512); gemini_pmx_desc.pins = gemini_3512_pins; gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); dev_info(dev, "detected 3512 chip variant\n"); } else if (val == 0x3516) { pmx->is_3516 = true; + pmx->confs = gemini_confs_3516; + pmx->nconfs = ARRAY_SIZE(gemini_confs_3516); gemini_pmx_desc.pins = gemini_3516_pins; gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); dev_info(dev, "detected 3516 chip variant\n"); diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index d84761822243..372ddf386bdb 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -717,7 +717,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = { {}, }; -int ingenic_pinctrl_probe(struct platform_device *pdev) +static int ingenic_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct ingenic_pinctrl *jzpc; diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c index b8d2180a2bea..a7f37063518e 100644 --- a/drivers/pinctrl/pinctrl-max77620.c +++ b/drivers/pinctrl/pinctrl-max77620.c @@ -420,11 +420,9 @@ static int max77620_pinconf_set(struct pinctrl_dev *pctldev, MAX77620_REG_GPIO0 + pin, MAX77620_CNFG_GPIO_DRV_MASK, val); - if (ret < 0) { - dev_err(dev, "Reg 0x%02x update failed %d\n", - MAX77620_REG_GPIO0 + pin, ret); - return ret; - } + if (ret) + goto report_update_failure; + mpci->pin_info[pin].drv_type = val ? MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; break; @@ -435,11 +433,9 @@ static int max77620_pinconf_set(struct pinctrl_dev *pctldev, MAX77620_REG_GPIO0 + pin, MAX77620_CNFG_GPIO_DRV_MASK, val); - if (ret < 0) { - dev_err(dev, "Reg 0x%02x update failed %d\n", - MAX77620_REG_GPIO0 + pin, ret); - return ret; - } + if (ret) + goto report_update_failure; + mpci->pin_info[pin].drv_type = val ? MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; break; @@ -536,6 +532,11 @@ static int max77620_pinconf_set(struct pinctrl_dev *pctldev, } return 0; + +report_update_failure: + dev_err(dev, "Reg 0x%02x update failed %d\n", + MAX77620_REG_GPIO0 + pin, ret); + return ret; } static const struct pinconf_ops max77620_pinconf_ops = { diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 3e40d4245512..4a6ea159c65d 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -25,6 +25,7 @@ #define MCP_TYPE_008 2 #define MCP_TYPE_017 3 #define MCP_TYPE_S18 4 +#define MCP_TYPE_018 5 #define MCP_MAX_DEV_PER_CS 8 @@ -278,8 +279,7 @@ static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, { struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param; - u32 arg, mask; - u16 val; + u32 arg; int ret = 0; int i; @@ -289,8 +289,6 @@ static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_PULL_UP: - val = arg ? 0xFFFF : 0x0000; - mask = BIT(pin); ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); break; default: @@ -407,10 +405,10 @@ static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) ret = mcp_read(mcp, MCP_GPIO, &status); if (ret < 0) status = 0; - else + else { + mcp->cached_gpio = status; status = !!(status & (1 << offset)); - - mcp->cached_gpio = status; + } mutex_unlock(&mcp->lock); return status; @@ -537,7 +535,7 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) ((gpio_bit_changed || intcap_changed) && (BIT(i) & mcp->irq_fall) && !gpio_set) || defval_changed) { - child_irq = irq_find_mapping(mcp->chip.irqdomain, i); + child_irq = irq_find_mapping(mcp->chip.irq.domain, i); handle_nested_irq(child_irq); } } @@ -837,6 +835,13 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->chip.ngpio = 16; mcp->chip.label = "mcp23017"; break; + + case MCP_TYPE_018: + mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23018"; + break; #endif /* CONFIG_I2C */ default: @@ -883,7 +888,7 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, if (mirror) status |= IOCON_MIRROR | (IOCON_MIRROR << 8); - if (type == MCP_TYPE_S18) + if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) status |= IOCON_INTCC | (IOCON_INTCC << 8); ret = mcp_write(mcp, MCP_IOCON, status); @@ -964,6 +969,10 @@ static const struct of_device_id mcp23s08_i2c_of_match[] = { .compatible = "microchip,mcp23017", .data = (void *) MCP_TYPE_017, }, + { + .compatible = "microchip,mcp23018", + .data = (void *) MCP_TYPE_018, + }, /* NOTE: The use of the mcp prefix is deprecated and will be removed. */ { .compatible = "mcp,mcp23008", @@ -1013,6 +1022,7 @@ static int mcp230xx_probe(struct i2c_client *client, static const struct i2c_device_id mcp230xx_id[] = { { "mcp23008", MCP_TYPE_008 }, { "mcp23017", MCP_TYPE_017 }, + { "mcp23018", MCP_TYPE_018 }, { }, }; MODULE_DEVICE_TABLE(i2c, mcp230xx_id); diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c index 494ec9a7573a..53ec22a51f5c 100644 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ b/drivers/pinctrl/pinctrl-oxnas.c @@ -1064,7 +1064,7 @@ static void oxnas_gpio_irq_handler(struct irq_desc *desc) stat = readl(bank->reg_base + IRQ_PENDING); for_each_set_bit(pin, &stat, BITS_PER_LONG) - generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin)); + generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin)); chained_irq_exit(chip, desc); } diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index 31ceb958b3fe..96390228d388 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -2106,7 +2106,7 @@ static void pic32_gpio_irq_handler(struct irq_desc *desc) pending = pic32_gpio_get_pending(gc, stat); for_each_set_bit(pin, &pending, BITS_PER_LONG) - generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin)); + generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin)); chained_irq_exit(chip, desc); } diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c index 55375b1b3cc8..302190d1558d 100644 --- a/drivers/pinctrl/pinctrl-pistachio.c +++ b/drivers/pinctrl/pinctrl-pistachio.c @@ -1307,7 +1307,7 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc) pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) & gpio_readl(bank, GPIO_INTERRUPT_EN); for_each_set_bit(pin, &pending, 16) - generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin)); + generic_handle_irq(irq_linear_revmap(gc->irq.domain, pin)); chained_irq_exit(chip, desc); } diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index b5cb7858ffdc..2ba17548ad5b 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -884,6 +884,24 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = { }, }; +static struct rockchip_mux_route_data rk3288_mux_route_data[] = { + { + /* edphdmi_cecinoutt1 */ + .bank_num = 7, + .pin = 16, + .func = 2, + .route_offset = 0x264, + .route_val = BIT(16 + 12) | BIT(12), + }, { + /* edphdmi_cecinout */ + .bank_num = 7, + .pin = 23, + .func = 4, + .route_offset = 0x264, + .route_val = BIT(16 + 12), + }, +}; + static struct rockchip_mux_route_data rk3328_mux_route_data[] = { { /* uart2dbg_rxm0 */ @@ -900,12 +918,19 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = { .route_offset = 0x50, .route_val = BIT(16) | BIT(16 + 1) | BIT(0), }, { - /* gmac-m1-optimized_rxd0 */ + /* gmac-m1_rxd0 */ .bank_num = 1, .pin = 11, .func = 2, .route_offset = 0x50, - .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10), + .route_val = BIT(16 + 2) | BIT(2), + }, { + /* gmac-m1-optimized_rxd3 */ + .bank_num = 1, + .pin = 14, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 10) | BIT(10), }, { /* pdm_sdi0m0 */ .bank_num = 2, @@ -3391,6 +3416,8 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .type = RK3288, .grf_mux_offset = 0x0, .pmu_mux_offset = 0x84, + .iomux_routes = rk3288_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), .pull_calc_reg = rk3288_calc_pull_reg_and_bit, .drv_calc_reg = rk3288_calc_drv_reg_and_bit, }; @@ -3456,8 +3483,8 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { DRV_TYPE_IO_1V8_ONLY, DRV_TYPE_IO_DEFAULT, DRV_TYPE_IO_DEFAULT, - 0x0, - 0x8, + 0x80, + 0x88, -1, -1, PULL_TYPE_IO_1V8_ONLY, @@ -3473,10 +3500,10 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { DRV_TYPE_IO_1V8_OR_3V0, DRV_TYPE_IO_1V8_OR_3V0, DRV_TYPE_IO_1V8_OR_3V0, - 0x20, - 0x28, - 0x30, - 0x38 + 0xa0, + 0xa8, + 0xb0, + 0xb8 ), PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, DRV_TYPE_IO_1V8_OR_3V0, diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index 04d058706b80..717c0f4449a0 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -303,6 +303,134 @@ static const struct rza1_pinmux_conf rza1h_pmx_conf = { }; /* ---------------------------------------------------------------------------- + * RZ/A1L (r7s72102) pinmux flags + */ + +static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = { + { .pin = 0, .func = 2 }, + { .pin = 1, .func = 2 }, + { .pin = 2, .func = 2 }, + { .pin = 4, .func = 2 }, + { .pin = 5, .func = 2 }, + { .pin = 10, .func = 2 }, + { .pin = 11, .func = 2 }, + { .pin = 12, .func = 2 }, + { .pin = 13, .func = 2 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = { + { .pin = 1, .func = 4 }, + { .pin = 2, .func = 2 }, + { .pin = 3, .func = 2 }, + { .pin = 6, .func = 2 }, + { .pin = 7, .func = 2 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, + { .pin = 8, .func = 1 }, + { .pin = 9, .func = 1 }, + { .pin = 10, .func = 1 }, + { .pin = 11, .func = 1 }, + { .pin = 12, .func = 1 }, + { .pin = 13, .func = 1 }, + { .pin = 14, .func = 1 }, + { .pin = 15, .func = 1 }, + { .pin = 0, .func = 2 }, + { .pin = 1, .func = 2 }, + { .pin = 2, .func = 2 }, + { .pin = 3, .func = 2 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, + { .pin = 8, .func = 1 }, + { .pin = 9, .func = 1 }, + { .pin = 10, .func = 1 }, + { .pin = 11, .func = 1 }, + { .pin = 12, .func = 1 }, + { .pin = 13, .func = 1 }, + { .pin = 14, .func = 1 }, + { .pin = 15, .func = 1 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = { + { .pin = 2, .func = 2 }, + { .pin = 3, .func = 2 }, + { .pin = 5, .func = 2 }, + { .pin = 6, .func = 2 }, + { .pin = 7, .func = 2 }, + { .pin = 2, .func = 3 }, + { .pin = 3, .func = 3 }, + { .pin = 5, .func = 3 }, + { .pin = 6, .func = 3 }, + { .pin = 7, .func = 3 }, +}; + +static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = { + { .pin = 1, .func = 2 }, + { .pin = 0, .func = 3 }, + { .pin = 1, .func = 3 }, + { .pin = 3, .func = 3 }, + { .pin = 4, .func = 3 }, + { .pin = 5, .func = 3 }, +}; + +static const struct rza1_swio_pin rza1l_swio_pins[] = { + { .port = 2, .pin = 8, .func = 2, .input = 0 }, + { .port = 5, .pin = 6, .func = 3, .input = 0 }, + { .port = 6, .pin = 6, .func = 3, .input = 0 }, + { .port = 6, .pin = 10, .func = 3, .input = 0 }, + { .port = 7, .pin = 10, .func = 2, .input = 0 }, + { .port = 8, .pin = 2, .func = 3, .input = 0 }, +}; + +static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = { + [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 }, + [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 }, + [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 }, + [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 }, + [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 }, + [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 }, + [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 }, +}; + +static const struct rza1_swio_entry rza1l_swio_entries[] = { + [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, +}; + +/* RZ/A1L (r7s72102x) pinmux flags table */ +static const struct rza1_pinmux_conf rza1l_pmx_conf = { + .bidir_entries = rza1l_bidir_entries, + .swio_entries = rza1l_swio_entries, +}; + +/* ---------------------------------------------------------------------------- * RZ/A1 types */ /** @@ -1283,9 +1411,15 @@ static int rza1_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rza1_pinctrl_of_match[] = { { + /* RZ/A1H, RZ/A1M */ .compatible = "renesas,r7s72100-ports", .data = &rza1h_pmx_conf, }, + { + /* RZ/A1L */ + .compatible = "renesas,r7s72102-ports", + .data = &rza1l_pmx_conf, + }, { } }; diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index b8b3d932cd73..e6cd8de793e2 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -873,13 +873,13 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, int i = 0, nconfs = 0; unsigned long *settings = NULL, *s = NULL; struct pcs_conf_vals *conf = NULL; - struct pcs_conf_type prop2[] = { + static const struct pcs_conf_type prop2[] = { { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, }; - struct pcs_conf_type prop4[] = { + static const struct pcs_conf_type prop4[] = { { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, { "pinctrl-single,input-schmitt-enable", diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index a5205b94b2e6..2081c67667a8 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1408,7 +1408,7 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank) continue; } - generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n)); + generic_handle_irq(irq_find_mapping(bank->gpio_chip.irq.domain, n)); } } } diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 7450f5118445..fb242c542dc9 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -561,7 +561,7 @@ static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) status = val; for_each_set_bit(n, &status, pctl->data->ngpios) - handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n)); + handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n)); return IRQ_HANDLED; } @@ -1087,7 +1087,7 @@ static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; } -const struct regmap_config sx150x_regmap_config = { +static const struct regmap_config sx150x_regmap_config = { .reg_bits = 8, .val_bits = 32, diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 06c8b2ace05f..a1db345ded1c 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Qualcomm pin control drivers obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index ff491da64dab..7a960590ecaa 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -795,7 +795,7 @@ static void msm_gpio_irq_handler(struct irq_desc *desc) g = &pctrl->soc->groups[i]; val = readl(pctrl->regs + g->intr_status_reg); if (val & BIT(g->intr_status_bit)) { - irq_pin = irq_find_mapping(gc->irqdomain, i); + irq_pin = irq_find_mapping(gc->irq.domain, i); generic_handle_irq(irq_pin); handled++; } diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index c2c0bab04257..3e66e0d10010 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -453,6 +453,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, pad = pctldev->desc->pins[pin].drv_data; + pad->is_enabled = true; for (i = 0; i < nconfs; i++) { param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); @@ -600,6 +601,10 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, return ret; } + val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; + + ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); + return ret; } @@ -1032,6 +1037,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ + { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */ { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ { .compatible = "qcom,spmi-gpio" }, /* Generic */ { }, diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig index 0357f9701eb9..ecfb90059eeb 100644 --- a/drivers/pinctrl/samsung/Kconfig +++ b/drivers/pinctrl/samsung/Kconfig @@ -29,7 +29,7 @@ config PINCTRL_EXYNOS5440 config PINCTRL_S3C24XX bool "Samsung S3C24XX SoC pinctrl driver" - depends on ARCH_S3C24XX + depends on ARCH_S3C24XX && OF select PINCTRL_SAMSUNG config PINCTRL_S3C64XX diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile index 595995851ea5..df426561d067 100644 --- a/drivers/pinctrl/samsung/Makefile +++ b/drivers/pinctrl/samsung/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Samsung pin control drivers obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 1d4f05a96bd4..a7903904b64e 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 0c5e952461fd..cf4ae4bc9115 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -24,6 +24,7 @@ #include <linux/of_device.h> #include <linux/pinctrl/machine.h> #include <linux/platform_device.h> +#include <linux/psci.h> #include <linux/slab.h> #include "core.h" @@ -175,19 +176,19 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, BUG(); } -u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width) +u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) { - return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width); + return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32); } -void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) +void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) { if (pfc->info->unlock_reg) sh_pfc_write_raw_reg( sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, ~data); - sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data); + sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data); } static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, @@ -389,15 +390,20 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) return 0; } -const struct sh_pfc_bias_info * -sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, - unsigned int num, unsigned int pin) +const struct pinmux_bias_reg * +sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, + unsigned int *bit) { - unsigned int i; + unsigned int i, j; - for (i = 0; i < num; i++) - if (info[i].pin == pin) - return &info[i]; + for (i = 0; pfc->info->bias_regs[i].puen; i++) { + for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { + if (pfc->info->bias_regs[i].pins[j] == pin) { + *bit = j; + return &pfc->info->bias_regs[i]; + } + } + } WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); @@ -567,9 +573,99 @@ static const struct of_device_id sh_pfc_of_table[] = { }; #endif +#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW) +static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) +{ +} + +static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) +{ + pfc->saved_regs[idx] = sh_pfc_read(pfc, reg); +} + +static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx) +{ + sh_pfc_write(pfc, reg, pfc->saved_regs[idx]); +} + +static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc, + void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx)) +{ + unsigned int i, n = 0; + + if (pfc->info->cfg_regs) + for (i = 0; pfc->info->cfg_regs[i].reg; i++) + do_reg(pfc, pfc->info->cfg_regs[i].reg, n++); + + if (pfc->info->drive_regs) + for (i = 0; pfc->info->drive_regs[i].reg; i++) + do_reg(pfc, pfc->info->drive_regs[i].reg, n++); + + if (pfc->info->bias_regs) + for (i = 0; pfc->info->bias_regs[i].puen; i++) { + do_reg(pfc, pfc->info->bias_regs[i].puen, n++); + if (pfc->info->bias_regs[i].pud) + do_reg(pfc, pfc->info->bias_regs[i].pud, n++); + } + + if (pfc->info->ioctrl_regs) + for (i = 0; pfc->info->ioctrl_regs[i].reg; i++) + do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++); + + return n; +} + +static int sh_pfc_suspend_init(struct sh_pfc *pfc) +{ + unsigned int n; + + /* This is the best we can do to check for the presence of PSCI */ + if (!psci_ops.cpu_suspend) + return 0; + + n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg); + if (!n) + return 0; + + pfc->saved_regs = devm_kmalloc_array(pfc->dev, n, + sizeof(*pfc->saved_regs), + GFP_KERNEL); + if (!pfc->saved_regs) + return -ENOMEM; + + dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n); + return 0; +} + +static int sh_pfc_suspend_noirq(struct device *dev) +{ + struct sh_pfc *pfc = dev_get_drvdata(dev); + + if (pfc->saved_regs) + sh_pfc_walk_regs(pfc, sh_pfc_save_reg); + return 0; +} + +static int sh_pfc_resume_noirq(struct device *dev) +{ + struct sh_pfc *pfc = dev_get_drvdata(dev); + + if (pfc->saved_regs) + sh_pfc_walk_regs(pfc, sh_pfc_restore_reg); + return 0; +} + +static const struct dev_pm_ops sh_pfc_pm = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq) +}; +#define DEV_PM_OPS &sh_pfc_pm +#else +static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } +#define DEV_PM_OPS NULL +#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */ + static int sh_pfc_probe(struct platform_device *pdev) { - const struct platform_device_id *platid = platform_get_device_id(pdev); #ifdef CONFIG_OF struct device_node *np = pdev->dev.of_node; #endif @@ -582,10 +678,7 @@ static int sh_pfc_probe(struct platform_device *pdev) info = of_device_get_match_data(&pdev->dev); else #endif - info = platid ? (const void *)platid->driver_data : NULL; - - if (info == NULL) - return -ENODEV; + info = (const void *)platform_get_device_id(pdev)->driver_data; pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); if (pfc == NULL) @@ -609,6 +702,10 @@ static int sh_pfc_probe(struct platform_device *pdev) info = pfc->info; } + ret = sh_pfc_suspend_init(pfc); + if (ret) + return ret; + /* Enable dummy states for those platforms without pinctrl support */ if (!of_have_populated_dt()) pinctrl_provide_dummies(); @@ -683,7 +780,6 @@ static const struct platform_device_id sh_pfc_id_table[] = { #ifdef CONFIG_PINCTRL_PFC_SHX3 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, #endif - { "sh-pfc", 0 }, { }, }; @@ -693,6 +789,7 @@ static struct platform_driver sh_pfc_driver = { .driver = { .name = DRV_NAME, .of_match_table = of_match_ptr(sh_pfc_of_table), + .pm = DEV_PM_OPS, }, }; diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h index 6d598dd63720..5af8ee26c03e 100644 --- a/drivers/pinctrl/sh-pfc/core.h +++ b/drivers/pinctrl/sh-pfc/core.h @@ -26,15 +26,14 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc); u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width); void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, u32 data); -u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width); -void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, - u32 data); +u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg); +void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data); int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); -const struct sh_pfc_bias_info * -sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, - unsigned int num, unsigned int pin); +const struct pinmux_bias_reg * +sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, + unsigned int *bit); #endif /* __SH_PFC_CORE_H__ */ diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 6b5422766f13..946d9be50b62 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -139,12 +139,12 @@ static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) if (idx < 0 || pfc->info->pins[idx].enum_id == 0) return -EINVAL; - return pinctrl_request_gpio(offset); + return pinctrl_gpio_request(offset); } static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) { - return pinctrl_free_gpio(offset); + return pinctrl_gpio_free(offset); } static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index c3af9ebee4af..00d61d175249 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -2912,189 +2912,230 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -#define PUPR0 0x100 -#define PUPR1 0x104 -#define PUPR2 0x108 -#define PUPR3 0x10c -#define PUPR4 0x110 -#define PUPR5 0x114 - -static const struct sh_pfc_bias_info bias_info[] = { - { RCAR_GP_PIN(0, 6), PUPR0, 0 }, /* A0 */ - { RCAR_GP_PIN(0, 7), PUPR0, 1 }, /* A1 */ - { RCAR_GP_PIN(0, 8), PUPR0, 2 }, /* A2 */ - { RCAR_GP_PIN(0, 9), PUPR0, 3 }, /* A3 */ - { RCAR_GP_PIN(0, 10), PUPR0, 4 }, /* A4 */ - { RCAR_GP_PIN(0, 11), PUPR0, 5 }, /* A5 */ - { RCAR_GP_PIN(0, 12), PUPR0, 6 }, /* A6 */ - { RCAR_GP_PIN(0, 13), PUPR0, 7 }, /* A7 */ - { RCAR_GP_PIN(0, 14), PUPR0, 8 }, /* A8 */ - { RCAR_GP_PIN(0, 15), PUPR0, 9 }, /* A9 */ - { RCAR_GP_PIN(0, 16), PUPR0, 10 }, /* A10 */ - { RCAR_GP_PIN(0, 17), PUPR0, 11 }, /* A11 */ - { RCAR_GP_PIN(0, 18), PUPR0, 12 }, /* A12 */ - { RCAR_GP_PIN(0, 19), PUPR0, 13 }, /* A13 */ - { RCAR_GP_PIN(0, 20), PUPR0, 14 }, /* A14 */ - { RCAR_GP_PIN(0, 21), PUPR0, 15 }, /* A15 */ - { RCAR_GP_PIN(0, 22), PUPR0, 16 }, /* A16 */ - { RCAR_GP_PIN(0, 23), PUPR0, 17 }, /* A17 */ - { RCAR_GP_PIN(0, 24), PUPR0, 18 }, /* A18 */ - { RCAR_GP_PIN(0, 25), PUPR0, 19 }, /* A19 */ - { RCAR_GP_PIN(0, 26), PUPR0, 20 }, /* A20 */ - { RCAR_GP_PIN(0, 27), PUPR0, 21 }, /* A21 */ - { RCAR_GP_PIN(0, 28), PUPR0, 22 }, /* A22 */ - { RCAR_GP_PIN(0, 29), PUPR0, 23 }, /* A23 */ - { RCAR_GP_PIN(0, 30), PUPR0, 24 }, /* A24 */ - { RCAR_GP_PIN(0, 31), PUPR0, 25 }, /* A25 */ - { RCAR_GP_PIN(1, 3), PUPR0, 26 }, /* /EX_CS0 */ - { RCAR_GP_PIN(1, 4), PUPR0, 27 }, /* /EX_CS1 */ - { RCAR_GP_PIN(1, 5), PUPR0, 28 }, /* /EX_CS2 */ - { RCAR_GP_PIN(1, 6), PUPR0, 29 }, /* /EX_CS3 */ - { RCAR_GP_PIN(1, 7), PUPR0, 30 }, /* /EX_CS4 */ - { RCAR_GP_PIN(1, 8), PUPR0, 31 }, /* /EX_CS5 */ - - { RCAR_GP_PIN(0, 0), PUPR1, 0 }, /* /PRESETOUT */ - { RCAR_GP_PIN(0, 5), PUPR1, 1 }, /* /BS */ - { RCAR_GP_PIN(1, 0), PUPR1, 2 }, /* RD//WR */ - { RCAR_GP_PIN(1, 1), PUPR1, 3 }, /* /WE0 */ - { RCAR_GP_PIN(1, 2), PUPR1, 4 }, /* /WE1 */ - { RCAR_GP_PIN(1, 11), PUPR1, 5 }, /* EX_WAIT0 */ - { RCAR_GP_PIN(1, 9), PUPR1, 6 }, /* DREQ0 */ - { RCAR_GP_PIN(1, 10), PUPR1, 7 }, /* DACK0 */ - { RCAR_GP_PIN(1, 12), PUPR1, 8 }, /* IRQ0 */ - { RCAR_GP_PIN(1, 13), PUPR1, 9 }, /* IRQ1 */ - - { RCAR_GP_PIN(1, 22), PUPR2, 0 }, /* DU0_DR0 */ - { RCAR_GP_PIN(1, 23), PUPR2, 1 }, /* DU0_DR1 */ - { RCAR_GP_PIN(1, 24), PUPR2, 2 }, /* DU0_DR2 */ - { RCAR_GP_PIN(1, 25), PUPR2, 3 }, /* DU0_DR3 */ - { RCAR_GP_PIN(1, 26), PUPR2, 4 }, /* DU0_DR4 */ - { RCAR_GP_PIN(1, 27), PUPR2, 5 }, /* DU0_DR5 */ - { RCAR_GP_PIN(1, 28), PUPR2, 6 }, /* DU0_DR6 */ - { RCAR_GP_PIN(1, 29), PUPR2, 7 }, /* DU0_DR7 */ - { RCAR_GP_PIN(1, 30), PUPR2, 8 }, /* DU0_DG0 */ - { RCAR_GP_PIN(1, 31), PUPR2, 9 }, /* DU0_DG1 */ - { RCAR_GP_PIN(2, 0), PUPR2, 10 }, /* DU0_DG2 */ - { RCAR_GP_PIN(2, 1), PUPR2, 11 }, /* DU0_DG3 */ - { RCAR_GP_PIN(2, 2), PUPR2, 12 }, /* DU0_DG4 */ - { RCAR_GP_PIN(2, 3), PUPR2, 13 }, /* DU0_DG5 */ - { RCAR_GP_PIN(2, 4), PUPR2, 14 }, /* DU0_DG6 */ - { RCAR_GP_PIN(2, 5), PUPR2, 15 }, /* DU0_DG7 */ - { RCAR_GP_PIN(2, 6), PUPR2, 16 }, /* DU0_DB0 */ - { RCAR_GP_PIN(2, 7), PUPR2, 17 }, /* DU0_DB1 */ - { RCAR_GP_PIN(2, 8), PUPR2, 18 }, /* DU0_DB2 */ - { RCAR_GP_PIN(2, 9), PUPR2, 19 }, /* DU0_DB3 */ - { RCAR_GP_PIN(2, 10), PUPR2, 20 }, /* DU0_DB4 */ - { RCAR_GP_PIN(2, 11), PUPR2, 21 }, /* DU0_DB5 */ - { RCAR_GP_PIN(2, 12), PUPR2, 22 }, /* DU0_DB6 */ - { RCAR_GP_PIN(2, 13), PUPR2, 23 }, /* DU0_DB7 */ - { RCAR_GP_PIN(2, 14), PUPR2, 24 }, /* DU0_DOTCLKIN */ - { RCAR_GP_PIN(2, 15), PUPR2, 25 }, /* DU0_DOTCLKOUT0 */ - { RCAR_GP_PIN(2, 17), PUPR2, 26 }, /* DU0_HSYNC */ - { RCAR_GP_PIN(2, 18), PUPR2, 27 }, /* DU0_VSYNC */ - { RCAR_GP_PIN(2, 19), PUPR2, 28 }, /* DU0_EXODDF */ - { RCAR_GP_PIN(2, 20), PUPR2, 29 }, /* DU0_DISP */ - { RCAR_GP_PIN(2, 21), PUPR2, 30 }, /* DU0_CDE */ - { RCAR_GP_PIN(2, 16), PUPR2, 31 }, /* DU0_DOTCLKOUT1 */ - - { RCAR_GP_PIN(3, 24), PUPR3, 0 }, /* VI0_CLK */ - { RCAR_GP_PIN(3, 25), PUPR3, 1 }, /* VI0_CLKENB */ - { RCAR_GP_PIN(3, 26), PUPR3, 2 }, /* VI0_FIELD */ - { RCAR_GP_PIN(3, 27), PUPR3, 3 }, /* /VI0_HSYNC */ - { RCAR_GP_PIN(3, 28), PUPR3, 4 }, /* /VI0_VSYNC */ - { RCAR_GP_PIN(3, 29), PUPR3, 5 }, /* VI0_DATA0 */ - { RCAR_GP_PIN(3, 30), PUPR3, 6 }, /* VI0_DATA1 */ - { RCAR_GP_PIN(3, 31), PUPR3, 7 }, /* VI0_DATA2 */ - { RCAR_GP_PIN(4, 0), PUPR3, 8 }, /* VI0_DATA3 */ - { RCAR_GP_PIN(4, 1), PUPR3, 9 }, /* VI0_DATA4 */ - { RCAR_GP_PIN(4, 2), PUPR3, 10 }, /* VI0_DATA5 */ - { RCAR_GP_PIN(4, 3), PUPR3, 11 }, /* VI0_DATA6 */ - { RCAR_GP_PIN(4, 4), PUPR3, 12 }, /* VI0_DATA7 */ - { RCAR_GP_PIN(4, 5), PUPR3, 13 }, /* VI0_G2 */ - { RCAR_GP_PIN(4, 6), PUPR3, 14 }, /* VI0_G3 */ - { RCAR_GP_PIN(4, 7), PUPR3, 15 }, /* VI0_G4 */ - { RCAR_GP_PIN(4, 8), PUPR3, 16 }, /* VI0_G5 */ - { RCAR_GP_PIN(4, 21), PUPR3, 17 }, /* VI1_DATA12 */ - { RCAR_GP_PIN(4, 22), PUPR3, 18 }, /* VI1_DATA13 */ - { RCAR_GP_PIN(4, 23), PUPR3, 19 }, /* VI1_DATA14 */ - { RCAR_GP_PIN(4, 24), PUPR3, 20 }, /* VI1_DATA15 */ - { RCAR_GP_PIN(4, 9), PUPR3, 21 }, /* ETH_REF_CLK */ - { RCAR_GP_PIN(4, 10), PUPR3, 22 }, /* ETH_TXD0 */ - { RCAR_GP_PIN(4, 11), PUPR3, 23 }, /* ETH_TXD1 */ - { RCAR_GP_PIN(4, 12), PUPR3, 24 }, /* ETH_CRS_DV */ - { RCAR_GP_PIN(4, 13), PUPR3, 25 }, /* ETH_TX_EN */ - { RCAR_GP_PIN(4, 14), PUPR3, 26 }, /* ETH_RX_ER */ - { RCAR_GP_PIN(4, 15), PUPR3, 27 }, /* ETH_RXD0 */ - { RCAR_GP_PIN(4, 16), PUPR3, 28 }, /* ETH_RXD1 */ - { RCAR_GP_PIN(4, 17), PUPR3, 29 }, /* ETH_MDC */ - { RCAR_GP_PIN(4, 18), PUPR3, 30 }, /* ETH_MDIO */ - { RCAR_GP_PIN(4, 19), PUPR3, 31 }, /* ETH_LINK */ - - { RCAR_GP_PIN(3, 6), PUPR4, 0 }, /* SSI_SCK012 */ - { RCAR_GP_PIN(3, 7), PUPR4, 1 }, /* SSI_WS012 */ - { RCAR_GP_PIN(3, 10), PUPR4, 2 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(3, 9), PUPR4, 3 }, /* SSI_SDATA1 */ - { RCAR_GP_PIN(3, 8), PUPR4, 4 }, /* SSI_SDATA2 */ - { RCAR_GP_PIN(3, 2), PUPR4, 5 }, /* SSI_SCK34 */ - { RCAR_GP_PIN(3, 3), PUPR4, 6 }, /* SSI_WS34 */ - { RCAR_GP_PIN(3, 5), PUPR4, 7 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(3, 4), PUPR4, 8 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(2, 31), PUPR4, 9 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(3, 0), PUPR4, 10 }, /* SSI_WS5 */ - { RCAR_GP_PIN(3, 1), PUPR4, 11 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(2, 28), PUPR4, 12 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(2, 29), PUPR4, 13 }, /* SSI_WS6 */ - { RCAR_GP_PIN(2, 30), PUPR4, 14 }, /* SSI_SDATA6 */ - { RCAR_GP_PIN(2, 24), PUPR4, 15 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(2, 25), PUPR4, 16 }, /* SSI_WS78 */ - { RCAR_GP_PIN(2, 27), PUPR4, 17 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(2, 26), PUPR4, 18 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(3, 23), PUPR4, 19 }, /* TCLK0 */ - { RCAR_GP_PIN(3, 11), PUPR4, 20 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 12), PUPR4, 21 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 13), PUPR4, 22 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 14), PUPR4, 23 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 15), PUPR4, 24 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 16), PUPR4, 25 }, /* SD0_DAT3 */ - { RCAR_GP_PIN(3, 17), PUPR4, 26 }, /* SD0_CD */ - { RCAR_GP_PIN(3, 18), PUPR4, 27 }, /* SD0_WP */ - { RCAR_GP_PIN(2, 22), PUPR4, 28 }, /* AUDIO_CLKA */ - { RCAR_GP_PIN(2, 23), PUPR4, 29 }, /* AUDIO_CLKB */ - { RCAR_GP_PIN(1, 14), PUPR4, 30 }, /* IRQ2 */ - { RCAR_GP_PIN(1, 15), PUPR4, 31 }, /* IRQ3 */ - - { RCAR_GP_PIN(0, 1), PUPR5, 0 }, /* PENC0 */ - { RCAR_GP_PIN(0, 2), PUPR5, 1 }, /* PENC1 */ - { RCAR_GP_PIN(0, 3), PUPR5, 2 }, /* USB_OVC0 */ - { RCAR_GP_PIN(0, 4), PUPR5, 3 }, /* USB_OVC1 */ - { RCAR_GP_PIN(1, 16), PUPR5, 4 }, /* SCIF_CLK */ - { RCAR_GP_PIN(1, 17), PUPR5, 5 }, /* TX0 */ - { RCAR_GP_PIN(1, 18), PUPR5, 6 }, /* RX0 */ - { RCAR_GP_PIN(1, 19), PUPR5, 7 }, /* SCK0 */ - { RCAR_GP_PIN(1, 20), PUPR5, 8 }, /* /CTS0 */ - { RCAR_GP_PIN(1, 21), PUPR5, 9 }, /* /RTS0 */ - { RCAR_GP_PIN(3, 19), PUPR5, 10 }, /* HSPI_CLK0 */ - { RCAR_GP_PIN(3, 20), PUPR5, 11 }, /* /HSPI_CS0 */ - { RCAR_GP_PIN(3, 21), PUPR5, 12 }, /* HSPI_RX0 */ - { RCAR_GP_PIN(3, 22), PUPR5, 13 }, /* HSPI_TX0 */ - { RCAR_GP_PIN(4, 20), PUPR5, 14 }, /* ETH_MAGIC */ - { RCAR_GP_PIN(4, 25), PUPR5, 15 }, /* AVS1 */ - { RCAR_GP_PIN(4, 26), PUPR5, 16 }, /* AVS2 */ +#define PIN_NONE U16_MAX + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 6), /* A0 */ + [ 1] = RCAR_GP_PIN(0, 7), /* A1 */ + [ 2] = RCAR_GP_PIN(0, 8), /* A2 */ + [ 3] = RCAR_GP_PIN(0, 9), /* A3 */ + [ 4] = RCAR_GP_PIN(0, 10), /* A4 */ + [ 5] = RCAR_GP_PIN(0, 11), /* A5 */ + [ 6] = RCAR_GP_PIN(0, 12), /* A6 */ + [ 7] = RCAR_GP_PIN(0, 13), /* A7 */ + [ 8] = RCAR_GP_PIN(0, 14), /* A8 */ + [ 9] = RCAR_GP_PIN(0, 15), /* A9 */ + [10] = RCAR_GP_PIN(0, 16), /* A10 */ + [11] = RCAR_GP_PIN(0, 17), /* A11 */ + [12] = RCAR_GP_PIN(0, 18), /* A12 */ + [13] = RCAR_GP_PIN(0, 19), /* A13 */ + [14] = RCAR_GP_PIN(0, 20), /* A14 */ + [15] = RCAR_GP_PIN(0, 21), /* A15 */ + [16] = RCAR_GP_PIN(0, 22), /* A16 */ + [17] = RCAR_GP_PIN(0, 23), /* A17 */ + [18] = RCAR_GP_PIN(0, 24), /* A18 */ + [19] = RCAR_GP_PIN(0, 25), /* A19 */ + [20] = RCAR_GP_PIN(0, 26), /* A20 */ + [21] = RCAR_GP_PIN(0, 27), /* A21 */ + [22] = RCAR_GP_PIN(0, 28), /* A22 */ + [23] = RCAR_GP_PIN(0, 29), /* A23 */ + [24] = RCAR_GP_PIN(0, 30), /* A24 */ + [25] = RCAR_GP_PIN(0, 31), /* A25 */ + [26] = RCAR_GP_PIN(1, 3), /* /EX_CS0 */ + [27] = RCAR_GP_PIN(1, 4), /* /EX_CS1 */ + [28] = RCAR_GP_PIN(1, 5), /* /EX_CS2 */ + [29] = RCAR_GP_PIN(1, 6), /* /EX_CS3 */ + [30] = RCAR_GP_PIN(1, 7), /* /EX_CS4 */ + [31] = RCAR_GP_PIN(1, 8), /* /EX_CS5 */ + } }, + { PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 0), /* /PRESETOUT */ + [ 1] = RCAR_GP_PIN(0, 5), /* /BS */ + [ 2] = RCAR_GP_PIN(1, 0), /* RD//WR */ + [ 3] = RCAR_GP_PIN(1, 1), /* /WE0 */ + [ 4] = RCAR_GP_PIN(1, 2), /* /WE1 */ + [ 5] = RCAR_GP_PIN(1, 11), /* EX_WAIT0 */ + [ 6] = RCAR_GP_PIN(1, 9), /* DREQ0 */ + [ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */ + [ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */ + [ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */ + [10] = PIN_NONE, + [11] = PIN_NONE, + [12] = PIN_NONE, + [13] = PIN_NONE, + [14] = PIN_NONE, + [15] = PIN_NONE, + [16] = PIN_NONE, + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */ + [ 1] = RCAR_GP_PIN(1, 23), /* DU0_DR1 */ + [ 2] = RCAR_GP_PIN(1, 24), /* DU0_DR2 */ + [ 3] = RCAR_GP_PIN(1, 25), /* DU0_DR3 */ + [ 4] = RCAR_GP_PIN(1, 26), /* DU0_DR4 */ + [ 5] = RCAR_GP_PIN(1, 27), /* DU0_DR5 */ + [ 6] = RCAR_GP_PIN(1, 28), /* DU0_DR6 */ + [ 7] = RCAR_GP_PIN(1, 29), /* DU0_DR7 */ + [ 8] = RCAR_GP_PIN(1, 30), /* DU0_DG0 */ + [ 9] = RCAR_GP_PIN(1, 31), /* DU0_DG1 */ + [10] = RCAR_GP_PIN(2, 0), /* DU0_DG2 */ + [11] = RCAR_GP_PIN(2, 1), /* DU0_DG3 */ + [12] = RCAR_GP_PIN(2, 2), /* DU0_DG4 */ + [13] = RCAR_GP_PIN(2, 3), /* DU0_DG5 */ + [14] = RCAR_GP_PIN(2, 4), /* DU0_DG6 */ + [15] = RCAR_GP_PIN(2, 5), /* DU0_DG7 */ + [16] = RCAR_GP_PIN(2, 6), /* DU0_DB0 */ + [17] = RCAR_GP_PIN(2, 7), /* DU0_DB1 */ + [18] = RCAR_GP_PIN(2, 8), /* DU0_DB2 */ + [19] = RCAR_GP_PIN(2, 9), /* DU0_DB3 */ + [20] = RCAR_GP_PIN(2, 10), /* DU0_DB4 */ + [21] = RCAR_GP_PIN(2, 11), /* DU0_DB5 */ + [22] = RCAR_GP_PIN(2, 12), /* DU0_DB6 */ + [23] = RCAR_GP_PIN(2, 13), /* DU0_DB7 */ + [24] = RCAR_GP_PIN(2, 14), /* DU0_DOTCLKIN */ + [25] = RCAR_GP_PIN(2, 15), /* DU0_DOTCLKOUT0 */ + [26] = RCAR_GP_PIN(2, 17), /* DU0_HSYNC */ + [27] = RCAR_GP_PIN(2, 18), /* DU0_VSYNC */ + [28] = RCAR_GP_PIN(2, 19), /* DU0_EXODDF */ + [29] = RCAR_GP_PIN(2, 20), /* DU0_DISP */ + [30] = RCAR_GP_PIN(2, 21), /* DU0_CDE */ + [31] = RCAR_GP_PIN(2, 16), /* DU0_DOTCLKOUT1 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 24), /* VI0_CLK */ + [ 1] = RCAR_GP_PIN(3, 25), /* VI0_CLKENB */ + [ 2] = RCAR_GP_PIN(3, 26), /* VI0_FIELD */ + [ 3] = RCAR_GP_PIN(3, 27), /* /VI0_HSYNC */ + [ 4] = RCAR_GP_PIN(3, 28), /* /VI0_VSYNC */ + [ 5] = RCAR_GP_PIN(3, 29), /* VI0_DATA0 */ + [ 6] = RCAR_GP_PIN(3, 30), /* VI0_DATA1 */ + [ 7] = RCAR_GP_PIN(3, 31), /* VI0_DATA2 */ + [ 8] = RCAR_GP_PIN(4, 0), /* VI0_DATA3 */ + [ 9] = RCAR_GP_PIN(4, 1), /* VI0_DATA4 */ + [10] = RCAR_GP_PIN(4, 2), /* VI0_DATA5 */ + [11] = RCAR_GP_PIN(4, 3), /* VI0_DATA6 */ + [12] = RCAR_GP_PIN(4, 4), /* VI0_DATA7 */ + [13] = RCAR_GP_PIN(4, 5), /* VI0_G2 */ + [14] = RCAR_GP_PIN(4, 6), /* VI0_G3 */ + [15] = RCAR_GP_PIN(4, 7), /* VI0_G4 */ + [16] = RCAR_GP_PIN(4, 8), /* VI0_G5 */ + [17] = RCAR_GP_PIN(4, 21), /* VI1_DATA12 */ + [18] = RCAR_GP_PIN(4, 22), /* VI1_DATA13 */ + [19] = RCAR_GP_PIN(4, 23), /* VI1_DATA14 */ + [20] = RCAR_GP_PIN(4, 24), /* VI1_DATA15 */ + [21] = RCAR_GP_PIN(4, 9), /* ETH_REF_CLK */ + [22] = RCAR_GP_PIN(4, 10), /* ETH_TXD0 */ + [23] = RCAR_GP_PIN(4, 11), /* ETH_TXD1 */ + [24] = RCAR_GP_PIN(4, 12), /* ETH_CRS_DV */ + [25] = RCAR_GP_PIN(4, 13), /* ETH_TX_EN */ + [26] = RCAR_GP_PIN(4, 14), /* ETH_RX_ER */ + [27] = RCAR_GP_PIN(4, 15), /* ETH_RXD0 */ + [28] = RCAR_GP_PIN(4, 16), /* ETH_RXD1 */ + [29] = RCAR_GP_PIN(4, 17), /* ETH_MDC */ + [30] = RCAR_GP_PIN(4, 18), /* ETH_MDIO */ + [31] = RCAR_GP_PIN(4, 19), /* ETH_LINK */ + } }, + { PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 6), /* SSI_SCK012 */ + [ 1] = RCAR_GP_PIN(3, 7), /* SSI_WS012 */ + [ 2] = RCAR_GP_PIN(3, 10), /* SSI_SDATA0 */ + [ 3] = RCAR_GP_PIN(3, 9), /* SSI_SDATA1 */ + [ 4] = RCAR_GP_PIN(3, 8), /* SSI_SDATA2 */ + [ 5] = RCAR_GP_PIN(3, 2), /* SSI_SCK34 */ + [ 6] = RCAR_GP_PIN(3, 3), /* SSI_WS34 */ + [ 7] = RCAR_GP_PIN(3, 5), /* SSI_SDATA3 */ + [ 8] = RCAR_GP_PIN(3, 4), /* SSI_SDATA4 */ + [ 9] = RCAR_GP_PIN(2, 31), /* SSI_SCK5 */ + [10] = RCAR_GP_PIN(3, 0), /* SSI_WS5 */ + [11] = RCAR_GP_PIN(3, 1), /* SSI_SDATA5 */ + [12] = RCAR_GP_PIN(2, 28), /* SSI_SCK6 */ + [13] = RCAR_GP_PIN(2, 29), /* SSI_WS6 */ + [14] = RCAR_GP_PIN(2, 30), /* SSI_SDATA6 */ + [15] = RCAR_GP_PIN(2, 24), /* SSI_SCK78 */ + [16] = RCAR_GP_PIN(2, 25), /* SSI_WS78 */ + [17] = RCAR_GP_PIN(2, 27), /* SSI_SDATA7 */ + [18] = RCAR_GP_PIN(2, 26), /* SSI_SDATA8 */ + [19] = RCAR_GP_PIN(3, 23), /* TCLK0 */ + [20] = RCAR_GP_PIN(3, 11), /* SD0_CLK */ + [21] = RCAR_GP_PIN(3, 12), /* SD0_CMD */ + [22] = RCAR_GP_PIN(3, 13), /* SD0_DAT0 */ + [23] = RCAR_GP_PIN(3, 14), /* SD0_DAT1 */ + [24] = RCAR_GP_PIN(3, 15), /* SD0_DAT2 */ + [25] = RCAR_GP_PIN(3, 16), /* SD0_DAT3 */ + [26] = RCAR_GP_PIN(3, 17), /* SD0_CD */ + [27] = RCAR_GP_PIN(3, 18), /* SD0_WP */ + [28] = RCAR_GP_PIN(2, 22), /* AUDIO_CLKA */ + [29] = RCAR_GP_PIN(2, 23), /* AUDIO_CLKB */ + [30] = RCAR_GP_PIN(1, 14), /* IRQ2 */ + [31] = RCAR_GP_PIN(1, 15), /* IRQ3 */ + } }, + { PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 1), /* PENC0 */ + [ 1] = RCAR_GP_PIN(0, 2), /* PENC1 */ + [ 2] = RCAR_GP_PIN(0, 3), /* USB_OVC0 */ + [ 3] = RCAR_GP_PIN(0, 4), /* USB_OVC1 */ + [ 4] = RCAR_GP_PIN(1, 16), /* SCIF_CLK */ + [ 5] = RCAR_GP_PIN(1, 17), /* TX0 */ + [ 6] = RCAR_GP_PIN(1, 18), /* RX0 */ + [ 7] = RCAR_GP_PIN(1, 19), /* SCK0 */ + [ 8] = RCAR_GP_PIN(1, 20), /* /CTS0 */ + [ 9] = RCAR_GP_PIN(1, 21), /* /RTS0 */ + [10] = RCAR_GP_PIN(3, 19), /* HSPI_CLK0 */ + [11] = RCAR_GP_PIN(3, 20), /* /HSPI_CS0 */ + [12] = RCAR_GP_PIN(3, 21), /* HSPI_RX0 */ + [13] = RCAR_GP_PIN(3, 22), /* HSPI_TX0 */ + [14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */ + [15] = RCAR_GP_PIN(4, 25), /* AVS1 */ + [16] = RCAR_GP_PIN(4, 26), /* AVS2 */ + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { /* sentinel */ }, }; static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - const struct sh_pfc_bias_info *info; + const struct pinmux_bias_reg *reg; void __iomem *addr; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return PIN_CONFIG_BIAS_DISABLE; - addr = pfc->windows->virt + info->reg; + addr = pfc->windows->virt + reg->puen; - if (ioread32(addr) & BIT(info->bit)) + if (ioread32(addr) & BIT(bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_DISABLE; @@ -3103,21 +3144,20 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - const struct sh_pfc_bias_info *info; + const struct pinmux_bias_reg *reg; void __iomem *addr; + unsigned int bit; u32 value; - u32 bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return; - addr = pfc->windows->virt + info->reg; - bit = BIT(info->bit); + addr = pfc->windows->virt + reg->puen; - value = ioread32(addr) & ~bit; + value = ioread32(addr) & ~BIT(bit); if (bias == PIN_CONFIG_BIAS_PULL_UP) - value |= bit; + value |= BIT(bit); iowrite32(value, addr); } @@ -3144,6 +3184,7 @@ const struct sh_pfc_soc_info r8a7778_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index a0ed220071f5..333a3470e842 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -5097,6 +5097,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A7745 const struct sh_pfc_soc_info r8a7745_pinmux_info = { .name = "r8a77450_pfc", + .ops = &r8a7794_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index 95fd0994893a..1d4d84f34d60 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -1443,12 +1443,13 @@ static const u16 pinmux_data[] = { }; /* - * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. + * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs. * Physical layout rows: A - AW, cols: 1 - 39. */ #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +#define PIN_NONE U16_MAX static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), @@ -3774,6 +3775,23 @@ static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; +/* - USB30 ------------------------------------------------------------------ */ +static const unsigned int usb30_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int usb30_mux[] = { + USB30_PWEN_MARK, USB30_OVC_MARK, +}; +/* - USB31 ------------------------------------------------------------------ */ +static const unsigned int usb31_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), +}; +static const unsigned int usb31_mux[] = { + USB31_PWEN_MARK, USB31_OVC_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(audio_clk_a_a), SH_PFC_PIN_GROUP(audio_clk_a_b), @@ -4080,6 +4098,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), + SH_PFC_PIN_GROUP(usb30), + SH_PFC_PIN_GROUP(usb31), }; static const char * const audio_clk_groups[] = { @@ -4537,6 +4557,14 @@ static const char * const usb2_groups[] = { "usb2", }; +static const char * const usb30_groups[] = { + "usb30", +}; + +static const char * const usb31_groups[] = { + "usb31", +}; + static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), @@ -4588,6 +4616,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(usb30), + SH_PFC_FUNCTION(usb31), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5393,12 +5423,21 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { }, }; +enum ioctrl_regs { + POCCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POCCTRL] = { 0xe6060380, }, + { /* sentinel */ }, +}; + static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; - *pocctrl = 0xe6060380; + *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) bit = pin & 0x1f; @@ -5409,242 +5448,261 @@ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, return bit; } -#define PUEN 0xe6060400 -#define PUD 0xe6060440 - -#define PU0 0x00 -#define PU1 0x04 -#define PU2 0x08 -#define PU3 0x0c -#define PU4 0x10 -#define PU5 0x14 -#define PU6 0x18 - -static const struct sh_pfc_bias_info bias_info[] = { - { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ - { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ - { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ - { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ - { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ - { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ - { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ - { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ - { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ - { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ - { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ - { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ - { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ - { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ - { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ - { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ - { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ - { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ - - { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ - { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ - { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ - { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ - { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ - { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ - { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ - { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ - { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ - { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ - { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ - { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ - { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ - { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ - { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ - { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ - { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ - { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ - { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ - { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ - { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ - { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ - { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ - { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ - { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ - { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ - { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ - - { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ - { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ - { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ - { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ - { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ - { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ - { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ - { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ - { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ - { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ - { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ - { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ - { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ - { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ - { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ - { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ - { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ - { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ - { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ - { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ - { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ - { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ - { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ - { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ - { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ - { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ - { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ - { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ - { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ - { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ - { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ - - { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ - { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ - { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ - { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ - { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ - { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ - /* bit 8 n/a */ - { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ - { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ - { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ - { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ - { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ - { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ - { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ - - { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ - { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ - { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ - { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ - { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ - { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ - { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ - { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ - { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ - { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ - { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ - { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ - { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ - { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ - { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ - { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ - { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ - { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ - { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ - { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ - { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ - - { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ - { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ - { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ - { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ - { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ - { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ - { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ - { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ - { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ - { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ - { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ - { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ - { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ - - { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ - { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ - { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ + [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ + [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ + [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ + [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ + [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ + [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ + [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ + [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ + [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ + [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ + [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ + [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ + [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ + [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ + [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ + [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ + [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ + [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ + [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ + [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ + [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ + [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ + [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ + [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ + [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ + [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ + [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ + [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ + [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ + [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ + [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ + [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ + [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ + [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ + [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ + [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ + [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ + [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ + [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ + [12] = RCAR_GP_PIN(1, 0), /* A0 */ + [13] = RCAR_GP_PIN(1, 1), /* A1 */ + [14] = RCAR_GP_PIN(1, 2), /* A2 */ + [15] = RCAR_GP_PIN(1, 3), /* A3 */ + [16] = RCAR_GP_PIN(1, 4), /* A4 */ + [17] = RCAR_GP_PIN(1, 5), /* A5 */ + [18] = RCAR_GP_PIN(1, 6), /* A6 */ + [19] = RCAR_GP_PIN(1, 7), /* A7 */ + [20] = RCAR_GP_PIN(1, 8), /* A8 */ + [21] = RCAR_GP_PIN(1, 9), /* A9 */ + [22] = RCAR_GP_PIN(1, 10), /* A10 */ + [23] = RCAR_GP_PIN(1, 11), /* A11 */ + [24] = RCAR_GP_PIN(1, 12), /* A12 */ + [25] = RCAR_GP_PIN(1, 13), /* A13 */ + [26] = RCAR_GP_PIN(1, 14), /* A14 */ + [27] = RCAR_GP_PIN(1, 15), /* A15 */ + [28] = RCAR_GP_PIN(1, 16), /* A16 */ + [29] = RCAR_GP_PIN(1, 17), /* A17 */ + [30] = RCAR_GP_PIN(1, 18), /* A18 */ + [31] = RCAR_GP_PIN(1, 19), /* A19 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */ + [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ + [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */ + [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ + [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ + [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ + [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ + [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ + [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ + [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [10] = RCAR_GP_PIN(0, 0), /* D0 */ + [11] = RCAR_GP_PIN(0, 1), /* D1 */ + [12] = RCAR_GP_PIN(0, 2), /* D2 */ + [13] = RCAR_GP_PIN(0, 3), /* D3 */ + [14] = RCAR_GP_PIN(0, 4), /* D4 */ + [15] = RCAR_GP_PIN(0, 5), /* D5 */ + [16] = RCAR_GP_PIN(0, 6), /* D6 */ + [17] = RCAR_GP_PIN(0, 7), /* D7 */ + [18] = RCAR_GP_PIN(0, 8), /* D8 */ + [19] = RCAR_GP_PIN(0, 9), /* D9 */ + [20] = RCAR_GP_PIN(0, 10), /* D10 */ + [21] = RCAR_GP_PIN(0, 11), /* D11 */ + [22] = RCAR_GP_PIN(0, 12), /* D12 */ + [23] = RCAR_GP_PIN(0, 13), /* D13 */ + [24] = RCAR_GP_PIN(0, 14), /* D14 */ + [25] = RCAR_GP_PIN(0, 15), /* D15 */ + [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ + [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ + [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */ + [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ + [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */ + [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ + [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */ + [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ + [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ + [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ + [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ + [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ + [ 8] = PIN_NONE, + [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ + [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ + [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ + [13] = RCAR_GP_PIN(5, 1), /* RX0 */ + [14] = RCAR_GP_PIN(5, 2), /* TX0 */ + [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ + [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */ + [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ + [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ + [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ + [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */ + [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ + [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ + [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ + [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ + [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ + [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ + [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ + [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ + [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ + [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ + [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { + [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ + [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ + [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ + [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ + [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ + [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ + [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ + [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ + [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ + [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ + [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ + [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ + [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ + [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ + [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ + [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ + [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ + [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ + [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ + [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ + [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ + [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ + [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ + [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ + [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ + [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ + [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ + [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ + [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ + [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ + [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ + } }, + { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { + [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ + [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ + [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ + [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ + [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ + [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */ + [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */ + [ 7] = PIN_NONE, + [ 8] = PIN_NONE, + [ 9] = PIN_NONE, + [10] = PIN_NONE, + [11] = PIN_NONE, + [12] = PIN_NONE, + [13] = PIN_NONE, + [14] = PIN_NONE, + [15] = PIN_NONE, + [16] = PIN_NONE, + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { /* sentinel */ }, }; static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - const struct sh_pfc_bias_info *info; - u32 reg; - u32 bit; + const struct pinmux_bias_reg *reg; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return PIN_CONFIG_BIAS_DISABLE; - reg = info->reg; - bit = BIT(info->bit); - - if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_PULL_DOWN; @@ -5653,28 +5711,24 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - const struct sh_pfc_bias_info *info; + const struct pinmux_bias_reg *reg; u32 enable, updown; - u32 reg; - u32 bit; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return; - reg = info->reg; - bit = BIT(info->bit); - - enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= bit; + enable |= BIT(bit); - updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= bit; + updown |= BIT(bit); - sh_pfc_write_reg(pfc, PUD + reg, 32, updown); - sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); } static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = { @@ -5699,6 +5753,8 @@ const struct sh_pfc_soc_info r8a7795es1_pinmux_info = { .cfg_regs = pinmux_config_regs, .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 8b35772cda98..d1cec6d12e81 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -1508,12 +1508,13 @@ static const u16 pinmux_data[] = { }; /* - * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. + * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs. * Physical layout rows: A - AW, cols: 1 - 39. */ #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +#define PIN_NONE U16_MAX static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), @@ -1572,6 +1573,127 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; +/* - AUDIO CLOCK ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(6, 22), +}; +static const unsigned int audio_clk_a_a_mux[] = { + AUDIO_CLKA_A_MARK, +}; +static const unsigned int audio_clk_a_b_pins[] = { + /* CLK A */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int audio_clk_a_b_mux[] = { + AUDIO_CLKA_B_MARK, +}; +static const unsigned int audio_clk_a_c_pins[] = { + /* CLK A */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int audio_clk_a_c_mux[] = { + AUDIO_CLKA_C_MARK, +}; +static const unsigned int audio_clk_b_a_pins[] = { + /* CLK B */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int audio_clk_b_a_mux[] = { + AUDIO_CLKB_A_MARK, +}; +static const unsigned int audio_clk_b_b_pins[] = { + /* CLK B */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int audio_clk_b_b_mux[] = { + AUDIO_CLKB_B_MARK, +}; +static const unsigned int audio_clk_c_a_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int audio_clk_c_a_mux[] = { + AUDIO_CLKC_A_MARK, +}; +static const unsigned int audio_clk_c_b_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int audio_clk_c_b_mux[] = { + AUDIO_CLKC_B_MARK, +}; +static const unsigned int audio_clkout_a_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int audio_clkout_a_mux[] = { + AUDIO_CLKOUT_A_MARK, +}; +static const unsigned int audio_clkout_b_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int audio_clkout_b_mux[] = { + AUDIO_CLKOUT_B_MARK, +}; +static const unsigned int audio_clkout_c_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int audio_clkout_c_mux[] = { + AUDIO_CLKOUT_C_MARK, +}; +static const unsigned int audio_clkout_d_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int audio_clkout_d_mux[] = { + AUDIO_CLKOUT_D_MARK, +}; +static const unsigned int audio_clkout1_a_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int audio_clkout1_a_mux[] = { + AUDIO_CLKOUT1_A_MARK, +}; +static const unsigned int audio_clkout1_b_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int audio_clkout1_b_mux[] = { + AUDIO_CLKOUT1_B_MARK, +}; +static const unsigned int audio_clkout2_a_pins[] = { + /* CLKOUT2 */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int audio_clkout2_a_mux[] = { + AUDIO_CLKOUT2_A_MARK, +}; +static const unsigned int audio_clkout2_b_pins[] = { + /* CLKOUT2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int audio_clkout2_b_mux[] = { + AUDIO_CLKOUT2_B_MARK, +}; +static const unsigned int audio_clkout3_a_pins[] = { + /* CLKOUT3 */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int audio_clkout3_a_mux[] = { + AUDIO_CLKOUT3_A_MARK, +}; +static const unsigned int audio_clkout3_b_pins[] = { + /* CLKOUT3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int audio_clkout3_b_mux[] = { + AUDIO_CLKOUT3_B_MARK, +}; + /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { /* AVB_LINK */ @@ -1659,6 +1781,221 @@ static const unsigned int avb_avtp_capture_b_mux[] = { AVB_AVTP_CAPTURE_B_MARK, }; +/* - DRIF0 --------------------------------------------------------------- */ +static const unsigned int drif0_ctrl_a_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int drif0_ctrl_a_mux[] = { + RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, +}; +static const unsigned int drif0_data0_a_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int drif0_data0_a_mux[] = { + RIF0_D0_A_MARK, +}; +static const unsigned int drif0_data1_a_pins[] = { + /* D1 */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int drif0_data1_a_mux[] = { + RIF0_D1_A_MARK, +}; +static const unsigned int drif0_ctrl_b_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), +}; +static const unsigned int drif0_ctrl_b_mux[] = { + RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, +}; +static const unsigned int drif0_data0_b_pins[] = { + /* D0 */ + RCAR_GP_PIN(5, 1), +}; +static const unsigned int drif0_data0_b_mux[] = { + RIF0_D0_B_MARK, +}; +static const unsigned int drif0_data1_b_pins[] = { + /* D1 */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int drif0_data1_b_mux[] = { + RIF0_D1_B_MARK, +}; +static const unsigned int drif0_ctrl_c_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), +}; +static const unsigned int drif0_ctrl_c_mux[] = { + RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, +}; +static const unsigned int drif0_data0_c_pins[] = { + /* D0 */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int drif0_data0_c_mux[] = { + RIF0_D0_C_MARK, +}; +static const unsigned int drif0_data1_c_pins[] = { + /* D1 */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int drif0_data1_c_mux[] = { + RIF0_D1_C_MARK, +}; +/* - DRIF1 --------------------------------------------------------------- */ +static const unsigned int drif1_ctrl_a_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int drif1_ctrl_a_mux[] = { + RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, +}; +static const unsigned int drif1_data0_a_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int drif1_data0_a_mux[] = { + RIF1_D0_A_MARK, +}; +static const unsigned int drif1_data1_a_pins[] = { + /* D1 */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int drif1_data1_a_mux[] = { + RIF1_D1_A_MARK, +}; +static const unsigned int drif1_ctrl_b_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), +}; +static const unsigned int drif1_ctrl_b_mux[] = { + RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, +}; +static const unsigned int drif1_data0_b_pins[] = { + /* D0 */ + RCAR_GP_PIN(5, 7), +}; +static const unsigned int drif1_data0_b_mux[] = { + RIF1_D0_B_MARK, +}; +static const unsigned int drif1_data1_b_pins[] = { + /* D1 */ + RCAR_GP_PIN(5, 8), +}; +static const unsigned int drif1_data1_b_mux[] = { + RIF1_D1_B_MARK, +}; +static const unsigned int drif1_ctrl_c_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), +}; +static const unsigned int drif1_ctrl_c_mux[] = { + RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, +}; +static const unsigned int drif1_data0_c_pins[] = { + /* D0 */ + RCAR_GP_PIN(5, 6), +}; +static const unsigned int drif1_data0_c_mux[] = { + RIF1_D0_C_MARK, +}; +static const unsigned int drif1_data1_c_pins[] = { + /* D1 */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int drif1_data1_c_mux[] = { + RIF1_D1_C_MARK, +}; +/* - DRIF2 --------------------------------------------------------------- */ +static const unsigned int drif2_ctrl_a_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int drif2_ctrl_a_mux[] = { + RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, +}; +static const unsigned int drif2_data0_a_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int drif2_data0_a_mux[] = { + RIF2_D0_A_MARK, +}; +static const unsigned int drif2_data1_a_pins[] = { + /* D1 */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int drif2_data1_a_mux[] = { + RIF2_D1_A_MARK, +}; +static const unsigned int drif2_ctrl_b_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +}; +static const unsigned int drif2_ctrl_b_mux[] = { + RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, +}; +static const unsigned int drif2_data0_b_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int drif2_data0_b_mux[] = { + RIF2_D0_B_MARK, +}; +static const unsigned int drif2_data1_b_pins[] = { + /* D1 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int drif2_data1_b_mux[] = { + RIF2_D1_B_MARK, +}; +/* - DRIF3 --------------------------------------------------------------- */ +static const unsigned int drif3_ctrl_a_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int drif3_ctrl_a_mux[] = { + RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, +}; +static const unsigned int drif3_data0_a_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int drif3_data0_a_mux[] = { + RIF3_D0_A_MARK, +}; +static const unsigned int drif3_data1_a_pins[] = { + /* D1 */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int drif3_data1_a_mux[] = { + RIF3_D1_A_MARK, +}; +static const unsigned int drif3_ctrl_b_pins[] = { + /* CLK, SYNC */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int drif3_ctrl_b_mux[] = { + RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, +}; +static const unsigned int drif3_data0_b_pins[] = { + /* D0 */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int drif3_data0_b_mux[] = { + RIF3_D0_B_MARK, +}; +static const unsigned int drif3_data1_b_pins[] = { + /* D1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int drif3_data1_b_mux[] = { + RIF3_D1_B_MARK, +}; + /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -1740,6 +2077,308 @@ static const unsigned int du_disp_mux[] = { DU_DISP_MARK, }; +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), +}; +static const unsigned int hscif1_data_a_mux[] = { + HRX1_A_MARK, HTX1_A_MARK, +}; +static const unsigned int hscif1_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int hscif1_clk_a_mux[] = { + HSCK1_A_MARK, +}; +static const unsigned int hscif1_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7), +}; +static const unsigned int hscif1_ctrl_a_mux[] = { + HRTS1_N_A_MARK, HCTS1_N_A_MARK, +}; + +static const unsigned int hscif1_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int hscif1_data_b_mux[] = { + HRX1_B_MARK, HTX1_B_MARK, +}; +static const unsigned int hscif1_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int hscif1_clk_b_mux[] = { + HSCK1_B_MARK, +}; +static const unsigned int hscif1_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3), +}; +static const unsigned int hscif1_ctrl_b_mux[] = { + HRTS1_N_B_MARK, HCTS1_N_B_MARK, +}; +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int hscif2_data_a_mux[] = { + HRX2_A_MARK, HTX2_A_MARK, +}; +static const unsigned int hscif2_clk_a_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int hscif2_clk_a_mux[] = { + HSCK2_A_MARK, +}; +static const unsigned int hscif2_ctrl_a_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6), +}; +static const unsigned int hscif2_ctrl_a_mux[] = { + HRTS2_N_A_MARK, HCTS2_N_A_MARK, +}; + +static const unsigned int hscif2_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int hscif2_data_b_mux[] = { + HRX2_B_MARK, HTX2_B_MARK, +}; +static const unsigned int hscif2_clk_b_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int hscif2_clk_b_mux[] = { + HSCK2_B_MARK, +}; +static const unsigned int hscif2_ctrl_b_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19), +}; +static const unsigned int hscif2_ctrl_b_mux[] = { + HRTS2_N_B_MARK, HCTS2_N_B_MARK, +}; + +static const unsigned int hscif2_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), +}; +static const unsigned int hscif2_data_c_mux[] = { + HRX2_C_MARK, HTX2_C_MARK, +}; +static const unsigned int hscif2_clk_c_pins[] = { + /* SCK */ + RCAR_GP_PIN(6, 24), +}; +static const unsigned int hscif2_clk_c_mux[] = { + HSCK2_C_MARK, +}; +static const unsigned int hscif2_ctrl_c_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27), +}; +static const unsigned int hscif2_ctrl_c_mux[] = { + HRTS2_N_C_MARK, HCTS2_N_C_MARK, +}; +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24), +}; +static const unsigned int hscif3_data_a_mux[] = { + HRX3_A_MARK, HTX3_A_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 22), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +static const unsigned int hscif3_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), +}; +static const unsigned int hscif3_data_b_mux[] = { + HRX3_B_MARK, HTX3_B_MARK, +}; +static const unsigned int hscif3_data_c_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), +}; +static const unsigned int hscif3_data_c_mux[] = { + HRX3_C_MARK, HTX3_C_MARK, +}; +static const unsigned int hscif3_data_d_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; +static const unsigned int hscif3_data_d_mux[] = { + HRX3_D_MARK, HTX3_D_MARK, +}; +/* - HSCIF4 ----------------------------------------------------------------- */ +static const unsigned int hscif4_data_a_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), +}; +static const unsigned int hscif4_data_a_mux[] = { + HRX4_A_MARK, HTX4_A_MARK, +}; +static const unsigned int hscif4_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int hscif4_clk_mux[] = { + HSCK4_MARK, +}; +static const unsigned int hscif4_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), +}; +static const unsigned int hscif4_ctrl_mux[] = { + HRTS4_N_MARK, HCTS4_N_MARK, +}; + +static const unsigned int hscif4_data_b_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int hscif4_data_b_mux[] = { + HRX4_B_MARK, HTX4_B_MARK, +}; + +/* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c1_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), +}; +static const unsigned int i2c1_a_mux[] = { + SDA1_A_MARK, SCL1_A_MARK, +}; +static const unsigned int i2c1_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23), +}; +static const unsigned int i2c1_b_mux[] = { + SDA1_B_MARK, SCL1_B_MARK, +}; +static const unsigned int i2c2_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), +}; +static const unsigned int i2c2_a_mux[] = { + SDA2_A_MARK, SCL2_A_MARK, +}; +static const unsigned int i2c2_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), +}; +static const unsigned int i2c2_b_mux[] = { + SDA2_B_MARK, SCL2_B_MARK, +}; +static const unsigned int i2c6_a_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), +}; +static const unsigned int i2c6_a_mux[] = { + SDA6_A_MARK, SCL6_A_MARK, +}; +static const unsigned int i2c6_b_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), +}; +static const unsigned int i2c6_b_mux[] = { + SDA6_B_MARK, SCL6_B_MARK, +}; +static const unsigned int i2c6_c_pins[] = { + /* SDA, SCL */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), +}; +static const unsigned int i2c6_c_mux[] = { + SDA6_C_MARK, SCL6_C_MARK, +}; + +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2750,6 +3389,390 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 2), +}; +static const unsigned int sdhi0_data1_mux[] = { + SD0_DAT0_MARK, +}; +static const unsigned int sdhi0_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int sdhi0_data4_mux[] = { + SD0_DAT0_MARK, SD0_DAT1_MARK, + SD0_DAT2_MARK, SD0_DAT3_MARK, +}; +static const unsigned int sdhi0_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), +}; +static const unsigned int sdhi0_ctrl_mux[] = { + SD0_CLK_MARK, SD0_CMD_MARK, +}; +static const unsigned int sdhi0_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 12), +}; +static const unsigned int sdhi0_cd_mux[] = { + SD0_CD_MARK, +}; +static const unsigned int sdhi0_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int sdhi0_wp_mux[] = { + SD0_WP_MARK, +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int sdhi1_data1_mux[] = { + SD1_DAT0_MARK, +}; +static const unsigned int sdhi1_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int sdhi1_data4_mux[] = { + SD1_DAT0_MARK, SD1_DAT1_MARK, + SD1_DAT2_MARK, SD1_DAT3_MARK, +}; +static const unsigned int sdhi1_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), +}; +static const unsigned int sdhi1_ctrl_mux[] = { + SD1_CLK_MARK, SD1_CMD_MARK, +}; +static const unsigned int sdhi1_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int sdhi1_cd_mux[] = { + SD1_CD_MARK, +}; +static const unsigned int sdhi1_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int sdhi1_wp_mux[] = { + SD1_WP_MARK, +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 2), +}; +static const unsigned int sdhi2_data1_mux[] = { + SD2_DAT0_MARK, +}; +static const unsigned int sdhi2_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), +}; +static const unsigned int sdhi2_data4_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, + SD2_DAT2_MARK, SD2_DAT3_MARK, +}; +static const unsigned int sdhi2_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), +}; +static const unsigned int sdhi2_data8_mux[] = { + SD2_DAT0_MARK, SD2_DAT1_MARK, + SD2_DAT2_MARK, SD2_DAT3_MARK, + SD2_DAT4_MARK, SD2_DAT5_MARK, + SD2_DAT6_MARK, SD2_DAT7_MARK, +}; +static const unsigned int sdhi2_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), +}; +static const unsigned int sdhi2_ctrl_mux[] = { + SD2_CLK_MARK, SD2_CMD_MARK, +}; +static const unsigned int sdhi2_cd_a_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 13), +}; +static const unsigned int sdhi2_cd_a_mux[] = { + SD2_CD_A_MARK, +}; +static const unsigned int sdhi2_cd_b_pins[] = { + /* CD */ + RCAR_GP_PIN(5, 10), +}; +static const unsigned int sdhi2_cd_b_mux[] = { + SD2_CD_B_MARK, +}; +static const unsigned int sdhi2_wp_a_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 14), +}; +static const unsigned int sdhi2_wp_a_mux[] = { + SD2_WP_A_MARK, +}; +static const unsigned int sdhi2_wp_b_pins[] = { + /* WP */ + RCAR_GP_PIN(5, 11), +}; +static const unsigned int sdhi2_wp_b_mux[] = { + SD2_WP_B_MARK, +}; +static const unsigned int sdhi2_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int sdhi2_ds_mux[] = { + SD2_DS_MARK, +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { + /* D0 */ + RCAR_GP_PIN(4, 9), +}; +static const unsigned int sdhi3_data1_mux[] = { + SD3_DAT0_MARK, +}; +static const unsigned int sdhi3_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), +}; +static const unsigned int sdhi3_data4_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, +}; +static const unsigned int sdhi3_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi3_data8_mux[] = { + SD3_DAT0_MARK, SD3_DAT1_MARK, + SD3_DAT2_MARK, SD3_DAT3_MARK, + SD3_DAT4_MARK, SD3_DAT5_MARK, + SD3_DAT6_MARK, SD3_DAT7_MARK, +}; +static const unsigned int sdhi3_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), +}; +static const unsigned int sdhi3_ctrl_mux[] = { + SD3_CLK_MARK, SD3_CMD_MARK, +}; +static const unsigned int sdhi3_cd_pins[] = { + /* CD */ + RCAR_GP_PIN(4, 15), +}; +static const unsigned int sdhi3_cd_mux[] = { + SD3_CD_MARK, +}; +static const unsigned int sdhi3_wp_pins[] = { + /* WP */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int sdhi3_wp_mux[] = { + SD3_WP_MARK, +}; +static const unsigned int sdhi3_ds_pins[] = { + /* DS */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int sdhi3_ds_mux[] = { + SD3_DS_MARK, +}; + +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; +static const unsigned int ssi01239_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; +static const unsigned int ssi01239_ctrl_mux[] = { + SSI_SCK01239_MARK, SSI_WS01239_MARK, +}; +static const unsigned int ssi1_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 3), +}; +static const unsigned int ssi1_data_a_mux[] = { + SSI_SDATA1_A_MARK, +}; +static const unsigned int ssi1_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int ssi1_data_b_mux[] = { + SSI_SDATA1_B_MARK, +}; +static const unsigned int ssi1_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +}; +static const unsigned int ssi1_ctrl_a_mux[] = { + SSI_SCK1_A_MARK, SSI_WS1_A_MARK, +}; +static const unsigned int ssi1_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), +}; +static const unsigned int ssi1_ctrl_b_mux[] = { + SSI_SCK1_B_MARK, SSI_WS1_B_MARK, +}; +static const unsigned int ssi2_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 4), +}; +static const unsigned int ssi2_data_a_mux[] = { + SSI_SDATA2_A_MARK, +}; +static const unsigned int ssi2_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int ssi2_data_b_mux[] = { + SSI_SDATA2_B_MARK, +}; +static const unsigned int ssi2_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), +}; +static const unsigned int ssi2_ctrl_a_mux[] = { + SSI_SCK2_A_MARK, SSI_WS2_A_MARK, +}; +static const unsigned int ssi2_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int ssi2_ctrl_b_mux[] = { + SSI_SCK2_B_MARK, SSI_WS2_B_MARK, +}; +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; +static const unsigned int ssi349_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), +}; +static const unsigned int ssi349_ctrl_mux[] = { + SSI_SCK349_MARK, SSI_WS349_MARK, +}; +static const unsigned int ssi4_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; +static const unsigned int ssi5_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 13), +}; +static const unsigned int ssi5_data_mux[] = { + SSI_SDATA5_MARK, +}; +static const unsigned int ssi5_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; +static const unsigned int ssi5_ctrl_mux[] = { + SSI_SCK5_MARK, SSI_WS5_MARK, +}; +static const unsigned int ssi6_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 16), +}; +static const unsigned int ssi6_data_mux[] = { + SSI_SDATA6_MARK, +}; +static const unsigned int ssi6_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; +static const unsigned int ssi6_ctrl_mux[] = { + SSI_SCK6_MARK, SSI_WS6_MARK, +}; +static const unsigned int ssi7_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; +static const unsigned int ssi8_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; +static const unsigned int ssi9_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int ssi9_data_a_mux[] = { + SSI_SDATA9_A_MARK, +}; +static const unsigned int ssi9_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int ssi9_data_b_mux[] = { + SSI_SDATA9_B_MARK, +}; +static const unsigned int ssi9_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int ssi9_ctrl_a_mux[] = { + SSI_SCK9_A_MARK, SSI_WS9_A_MARK, +}; +static const unsigned int ssi9_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), +}; +static const unsigned int ssi9_ctrl_b_mux[] = { + SSI_SCK9_B_MARK, SSI_WS9_B_MARK, +}; + /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { /* PWEN, OVC */ @@ -2783,7 +3806,33 @@ static const unsigned int usb2_ch3_mux[] = { USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, }; +/* - USB30 ------------------------------------------------------------------ */ +static const unsigned int usb30_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int usb30_mux[] = { + USB30_PWEN_MARK, USB30_OVC_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a_a), + SH_PFC_PIN_GROUP(audio_clk_a_b), + SH_PFC_PIN_GROUP(audio_clk_a_c), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), @@ -2794,6 +3843,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_avtp_capture_a), SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(drif0_ctrl_a), + SH_PFC_PIN_GROUP(drif0_data0_a), + SH_PFC_PIN_GROUP(drif0_data1_a), + SH_PFC_PIN_GROUP(drif0_ctrl_b), + SH_PFC_PIN_GROUP(drif0_data0_b), + SH_PFC_PIN_GROUP(drif0_data1_b), + SH_PFC_PIN_GROUP(drif0_ctrl_c), + SH_PFC_PIN_GROUP(drif0_data0_c), + SH_PFC_PIN_GROUP(drif0_data1_c), + SH_PFC_PIN_GROUP(drif1_ctrl_a), + SH_PFC_PIN_GROUP(drif1_data0_a), + SH_PFC_PIN_GROUP(drif1_data1_a), + SH_PFC_PIN_GROUP(drif1_ctrl_b), + SH_PFC_PIN_GROUP(drif1_data0_b), + SH_PFC_PIN_GROUP(drif1_data1_b), + SH_PFC_PIN_GROUP(drif1_ctrl_c), + SH_PFC_PIN_GROUP(drif1_data0_c), + SH_PFC_PIN_GROUP(drif1_data1_c), + SH_PFC_PIN_GROUP(drif2_ctrl_a), + SH_PFC_PIN_GROUP(drif2_data0_a), + SH_PFC_PIN_GROUP(drif2_data1_a), + SH_PFC_PIN_GROUP(drif2_ctrl_b), + SH_PFC_PIN_GROUP(drif2_data0_b), + SH_PFC_PIN_GROUP(drif2_data1_b), + SH_PFC_PIN_GROUP(drif3_ctrl_a), + SH_PFC_PIN_GROUP(drif3_data0_a), + SH_PFC_PIN_GROUP(drif3_data1_a), + SH_PFC_PIN_GROUP(drif3_ctrl_b), + SH_PFC_PIN_GROUP(drif3_data0_b), + SH_PFC_PIN_GROUP(drif3_data1_b), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -2802,6 +3881,47 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(du_oddf), SH_PFC_PIN_GROUP(du_cde), SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_a), + SH_PFC_PIN_GROUP(hscif1_clk_a), + SH_PFC_PIN_GROUP(hscif1_ctrl_a), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_a), + SH_PFC_PIN_GROUP(hscif2_clk_a), + SH_PFC_PIN_GROUP(hscif2_ctrl_a), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_clk_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_ctrl_c), + SH_PFC_PIN_GROUP(hscif3_data_a), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(hscif3_data_b), + SH_PFC_PIN_GROUP(hscif3_data_c), + SH_PFC_PIN_GROUP(hscif3_data_d), + SH_PFC_PIN_GROUP(hscif4_data_a), + SH_PFC_PIN_GROUP(hscif4_clk), + SH_PFC_PIN_GROUP(hscif4_ctrl), + SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c1_a), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c2_a), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c6_a), + SH_PFC_PIN_GROUP(i2c6_b), + SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2943,10 +4063,82 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_data8), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd_a), + SH_PFC_PIN_GROUP(sdhi2_wp_a), + SH_PFC_PIN_GROUP(sdhi2_cd_b), + SH_PFC_PIN_GROUP(sdhi2_wp_b), + SH_PFC_PIN_GROUP(sdhi2_ds), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_data8), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(sdhi3_ds), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data_a), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl_a), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data_a), + SH_PFC_PIN_GROUP(ssi2_data_b), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi349_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data_a), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), + SH_PFC_PIN_GROUP(usb30), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a_a", + "audio_clk_a_b", + "audio_clk_a_c", + "audio_clk_b_a", + "audio_clk_b_b", + "audio_clk_c_a", + "audio_clk_c_b", + "audio_clkout_a", + "audio_clkout_b", + "audio_clkout_c", + "audio_clkout_d", + "audio_clkout1_a", + "audio_clkout1_b", + "audio_clkout2_a", + "audio_clkout2_b", + "audio_clkout3_a", + "audio_clkout3_b", }; static const char * const avb_groups[] = { @@ -2962,6 +4154,48 @@ static const char * const avb_groups[] = { "avb_avtp_capture_b", }; +static const char * const drif0_groups[] = { + "drif0_ctrl_a", + "drif0_data0_a", + "drif0_data1_a", + "drif0_ctrl_b", + "drif0_data0_b", + "drif0_data1_b", + "drif0_ctrl_c", + "drif0_data0_c", + "drif0_data1_c", +}; + +static const char * const drif1_groups[] = { + "drif1_ctrl_a", + "drif1_data0_a", + "drif1_data1_a", + "drif1_ctrl_b", + "drif1_data0_b", + "drif1_data1_b", + "drif1_ctrl_c", + "drif1_data0_c", + "drif1_data1_c", +}; + +static const char * const drif2_groups[] = { + "drif2_ctrl_a", + "drif2_data0_a", + "drif2_data1_a", + "drif2_ctrl_b", + "drif2_data0_b", + "drif2_data1_b", +}; + +static const char * const drif3_groups[] = { + "drif3_ctrl_a", + "drif3_data0_a", + "drif3_data1_a", + "drif3_ctrl_b", + "drif3_data0_b", + "drif3_data1_b", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -2973,6 +4207,74 @@ static const char * const du_groups[] = { "du_disp", }; +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data_a", + "hscif1_clk_a", + "hscif1_ctrl_a", + "hscif1_data_b", + "hscif1_clk_b", + "hscif1_ctrl_b", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data_a", + "hscif2_clk_a", + "hscif2_ctrl_a", + "hscif2_data_b", + "hscif2_clk_b", + "hscif2_ctrl_b", + "hscif2_data_c", + "hscif2_clk_c", + "hscif2_ctrl_c", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data_a", + "hscif3_clk", + "hscif3_ctrl", + "hscif3_data_b", + "hscif3_data_c", + "hscif3_data_d", +}; + +static const char * const hscif4_groups[] = { + "hscif4_data_a", + "hscif4_clk", + "hscif4_ctrl", + "hscif4_data_b", +}; + +static const char * const i2c1_groups[] = { + "i2c1_a", + "i2c1_b", +}; + +static const char * const i2c2_groups[] = { + "i2c2_a", + "i2c2_b", +}; + +static const char * const i2c6_groups[] = { + "i2c6_a", + "i2c6_b", + "i2c6_c", +}; + +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3168,6 +4470,72 @@ static const char * const scif_clk_groups[] = { "scif_clk_b", }; +static const char * const sdhi0_groups[] = { + "sdhi0_data1", + "sdhi0_data4", + "sdhi0_ctrl", + "sdhi0_cd", + "sdhi0_wp", +}; + +static const char * const sdhi1_groups[] = { + "sdhi1_data1", + "sdhi1_data4", + "sdhi1_ctrl", + "sdhi1_cd", + "sdhi1_wp", +}; + +static const char * const sdhi2_groups[] = { + "sdhi2_data1", + "sdhi2_data4", + "sdhi2_data8", + "sdhi2_ctrl", + "sdhi2_cd_a", + "sdhi2_wp_a", + "sdhi2_cd_b", + "sdhi2_wp_b", + "sdhi2_ds", +}; + +static const char * const sdhi3_groups[] = { + "sdhi3_data1", + "sdhi3_data4", + "sdhi3_data8", + "sdhi3_ctrl", + "sdhi3_cd", + "sdhi3_wp", + "sdhi3_ds", +}; + +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi01239_ctrl", + "ssi1_data_a", + "ssi1_data_b", + "ssi1_ctrl_a", + "ssi1_ctrl_b", + "ssi2_data_a", + "ssi2_data_b", + "ssi2_ctrl_a", + "ssi2_ctrl_b", + "ssi3_data", + "ssi349_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5_data", + "ssi5_ctrl", + "ssi6_data", + "ssi6_ctrl", + "ssi7_data", + "ssi78_ctrl", + "ssi8_data", + "ssi9_data_a", + "ssi9_data_b", + "ssi9_ctrl_a", + "ssi9_ctrl_b", +}; + static const char * const usb0_groups[] = { "usb0", }; @@ -3184,9 +4552,27 @@ static const char * const usb2_ch3_groups[] = { "usb2_ch3", }; +static const char * const usb30_groups[] = { + "usb30", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(drif0), + SH_PFC_FUNCTION(drif1), + SH_PFC_FUNCTION(drif2), + SH_PFC_FUNCTION(drif3), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -3205,10 +4591,16 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), SH_PFC_FUNCTION(usb2_ch3), + SH_PFC_FUNCTION(usb30), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -4021,11 +5413,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { }, }; +enum ioctrl_regs { + POCCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POCCTRL] = { 0xe6060380, }, + { /* sentinel */ }, +}; + static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; - *pocctrl = 0xe6060380; + *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) bit = pin & 0x1f; @@ -4036,242 +5437,261 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return bit; } -#define PUEN 0xe6060400 -#define PUD 0xe6060440 - -#define PU0 0x00 -#define PU1 0x04 -#define PU2 0x08 -#define PU3 0x0c -#define PU4 0x10 -#define PU5 0x14 -#define PU6 0x18 - -static const struct sh_pfc_bias_info bias_info[] = { - { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ - { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ - { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ - { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ - { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ - { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ - { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ - { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ - { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ - { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ - { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ - { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ - { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ - { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ - { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ - { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ - { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ - { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ - - { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ - { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ - { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ - { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ - { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ - { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ - { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ - { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ - { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ - { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ - { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ - { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ - { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ - { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ - { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ - { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ - { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ - { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ - { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ - { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ - { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ - { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ - { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ - { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ - { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ - { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ - { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ - - { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ - { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ - { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ - { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ - { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ - { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ - { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ - { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ - { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ - { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ - { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ - { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ - { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ - { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ - { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ - { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ - { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ - { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ - { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ - { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ - { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ - { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ - { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ - { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ - { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ - { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ - { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ - { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ - { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ - { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ - { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ - - { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ - { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ - { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ - { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ - { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ - { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ - /* bit 8 n/a */ - { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ - { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ - { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ - { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ - { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ - { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ - { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ - { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ - - { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ - { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ - { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ - { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ - { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ - { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ - { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ - { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ - { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ - { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ - { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ - { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ - { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ - { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ - { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ - { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ - { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ - { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ - { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ - { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ - { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ - - { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ - { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ - { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ - { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ - { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ - { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ - { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ - { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ - { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ - { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ - { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ - { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ - { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ - - { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */ - { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */ - { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ + [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ + [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ + [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ + [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ + [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ + [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ + [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ + [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ + [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ + [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ + [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ + [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ + [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ + [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ + [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ + [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ + [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ + [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ + [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ + [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ + [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ + [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ + [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ + [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ + [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ + [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ + [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ + [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ + [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ + [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ + [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ + [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ + [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ + [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ + [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ + [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ + [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ + [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ + [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ + [12] = RCAR_GP_PIN(1, 0), /* A0 */ + [13] = RCAR_GP_PIN(1, 1), /* A1 */ + [14] = RCAR_GP_PIN(1, 2), /* A2 */ + [15] = RCAR_GP_PIN(1, 3), /* A3 */ + [16] = RCAR_GP_PIN(1, 4), /* A4 */ + [17] = RCAR_GP_PIN(1, 5), /* A5 */ + [18] = RCAR_GP_PIN(1, 6), /* A6 */ + [19] = RCAR_GP_PIN(1, 7), /* A7 */ + [20] = RCAR_GP_PIN(1, 8), /* A8 */ + [21] = RCAR_GP_PIN(1, 9), /* A9 */ + [22] = RCAR_GP_PIN(1, 10), /* A10 */ + [23] = RCAR_GP_PIN(1, 11), /* A11 */ + [24] = RCAR_GP_PIN(1, 12), /* A12 */ + [25] = RCAR_GP_PIN(1, 13), /* A13 */ + [26] = RCAR_GP_PIN(1, 14), /* A14 */ + [27] = RCAR_GP_PIN(1, 15), /* A15 */ + [28] = RCAR_GP_PIN(1, 16), /* A16 */ + [29] = RCAR_GP_PIN(1, 17), /* A17 */ + [30] = RCAR_GP_PIN(1, 18), /* A18 */ + [31] = RCAR_GP_PIN(1, 19), /* A19 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */ + [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ + [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ + [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ + [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ + [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ + [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ + [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ + [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ + [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [10] = RCAR_GP_PIN(0, 0), /* D0 */ + [11] = RCAR_GP_PIN(0, 1), /* D1 */ + [12] = RCAR_GP_PIN(0, 2), /* D2 */ + [13] = RCAR_GP_PIN(0, 3), /* D3 */ + [14] = RCAR_GP_PIN(0, 4), /* D4 */ + [15] = RCAR_GP_PIN(0, 5), /* D5 */ + [16] = RCAR_GP_PIN(0, 6), /* D6 */ + [17] = RCAR_GP_PIN(0, 7), /* D7 */ + [18] = RCAR_GP_PIN(0, 8), /* D8 */ + [19] = RCAR_GP_PIN(0, 9), /* D9 */ + [20] = RCAR_GP_PIN(0, 10), /* D10 */ + [21] = RCAR_GP_PIN(0, 11), /* D11 */ + [22] = RCAR_GP_PIN(0, 12), /* D12 */ + [23] = RCAR_GP_PIN(0, 13), /* D13 */ + [24] = RCAR_GP_PIN(0, 14), /* D14 */ + [25] = RCAR_GP_PIN(0, 15), /* D15 */ + [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ + [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ + [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */ + [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ + [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */ + [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */ + [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */ + [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ + [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ + [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ + [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ + [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ + [ 8] = PIN_NONE, + [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ + [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ + [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ + [13] = RCAR_GP_PIN(5, 1), /* RX0 */ + [14] = RCAR_GP_PIN(5, 2), /* TX0 */ + [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ + [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */ + [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ + [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ + [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ + [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */ + [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ + [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ + [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ + [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ + [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ + [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ + [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ + [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ + [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ + [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ + [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { + [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ + [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ + [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ + [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ + [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ + [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ + [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ + [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ + [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ + [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ + [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ + [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ + [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ + [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ + [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ + [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ + [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ + [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ + [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ + [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ + [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ + [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ + [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ + [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ + [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ + [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ + [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ + [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ + [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ + [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ + [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ + } }, + { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { + [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ + [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ + [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ + [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ + [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ + [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ + [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ + [ 7] = PIN_NONE, + [ 8] = PIN_NONE, + [ 9] = PIN_NONE, + [10] = PIN_NONE, + [11] = PIN_NONE, + [12] = PIN_NONE, + [13] = PIN_NONE, + [14] = PIN_NONE, + [15] = PIN_NONE, + [16] = PIN_NONE, + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { /* sentinel */ }, }; static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - const struct sh_pfc_bias_info *info; - u32 reg; - u32 bit; + const struct pinmux_bias_reg *reg; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return PIN_CONFIG_BIAS_DISABLE; - reg = info->reg; - bit = BIT(info->bit); - - if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_PULL_DOWN; @@ -4280,28 +5700,24 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - const struct sh_pfc_bias_info *info; + const struct pinmux_bias_reg *reg; u32 enable, updown; - u32 reg; - u32 bit; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return; - reg = info->reg; - bit = BIT(info->bit); - - enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= bit; + enable |= BIT(bit); - updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= bit; + updown |= BIT(bit); - sh_pfc_write_reg(pfc, PUD + reg, 32, updown); - sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); } static const struct soc_device_attribute r8a7795es1[] = { @@ -4340,6 +5756,8 @@ const struct sh_pfc_soc_info r8a7795_pinmux_info = { .cfg_regs = pinmux_config_regs, .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 200e1f4f6db9..73ed9c74c137 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -495,7 +495,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) -/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ +/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) @@ -1518,6 +1518,7 @@ static const u16 pinmux_data[] = { #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) #define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) +#define PIN_NONE U16_MAX static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), @@ -2392,6 +2393,50 @@ static const unsigned int i2c6_c_mux[] = { SDA6_C_MARK, SCL6_C_MARK, }; +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3922,6 +3967,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -4286,6 +4337,15 @@ static const char * const i2c6_groups[] = { "i2c6_c", }; +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4580,6 +4640,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), @@ -5416,11 +5477,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { }, }; +enum ioctrl_regs { + POCCTRL, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POCCTRL] = { 0xe6060380, }, + { /* sentinel */ }, +}; + static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; - *pocctrl = 0xe6060380; + *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg; if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) bit = pin & 0x1f; @@ -5431,242 +5501,261 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return bit; } -#define PUEN 0xe6060400 -#define PUD 0xe6060440 - -#define PU0 0x00 -#define PU1 0x04 -#define PU2 0x08 -#define PU3 0x0c -#define PU4 0x10 -#define PU5 0x14 -#define PU6 0x18 - -static const struct sh_pfc_bias_info bias_info[] = { - { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ - { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ - { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ - { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ - { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ - { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ - { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ - { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ - { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ - { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ - { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ - { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ - { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ - { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ - { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ - { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ - { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ - { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ - { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ - { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ - { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ - { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ - { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ - { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ - { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ - { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ - { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ - { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ - { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ - { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ - - { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ - { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ - { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ - { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ - { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ - { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ - { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ - { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ - { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ - { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ - { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ - { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ - { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ - { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ - { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ - { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ - { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ - { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ - { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ - { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ - { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ - { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ - { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ - { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ - { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ - { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ - { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ - - { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ - { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ - { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */ - { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ - { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ - { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ - { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ - { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ - { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ - { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ - { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ - { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ - { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ - { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ - { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ - { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ - { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ - { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ - { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ - { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ - { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ - { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ - { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ - { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ - { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ - { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ - { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ - { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ - { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ - { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ - { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ - { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */ - - { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ - { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ - { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ - { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ - { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ - { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ - /* bit 8 n/a */ - { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ - { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ - { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ - { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ - { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ - { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */ - /* bit 1 n/a on M3*/ - { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */ - - { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ - { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ - { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ - { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ - { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ - { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ - { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ - { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ - { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ - { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ - { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ - { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ - { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ - { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ - { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ - { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ - { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ - { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ - { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ - { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ - { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ - - { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ - { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ - { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ - { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ - { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ - { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ - { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ - { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ - { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ - { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ - { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ - { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ - { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ - - { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */ - { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */ - { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */ + [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */ + [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */ + [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */ + [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */ + [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */ + [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */ + [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */ + [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */ + [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */ + [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */ + [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */ + [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */ + [13] = PIN_NUMBER('V', 6), /* RPC_WP# */ + [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */ + [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */ + [16] = PIN_NUMBER('B', 19), /* AVB_RXC */ + [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */ + [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */ + [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */ + [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */ + [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */ + [22] = PIN_NUMBER('A', 19), /* AVB_TXC */ + [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */ + [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */ + [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */ + [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */ + [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */ + [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */ + [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ + [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ + [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ + [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ + [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ + [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ + [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ + [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ + [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ + [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ + [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ + [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */ + [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ + [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ + [12] = RCAR_GP_PIN(1, 0), /* A0 */ + [13] = RCAR_GP_PIN(1, 1), /* A1 */ + [14] = RCAR_GP_PIN(1, 2), /* A2 */ + [15] = RCAR_GP_PIN(1, 3), /* A3 */ + [16] = RCAR_GP_PIN(1, 4), /* A4 */ + [17] = RCAR_GP_PIN(1, 5), /* A5 */ + [18] = RCAR_GP_PIN(1, 6), /* A6 */ + [19] = RCAR_GP_PIN(1, 7), /* A7 */ + [20] = RCAR_GP_PIN(1, 8), /* A8 */ + [21] = RCAR_GP_PIN(1, 9), /* A9 */ + [22] = RCAR_GP_PIN(1, 10), /* A10 */ + [23] = RCAR_GP_PIN(1, 11), /* A11 */ + [24] = RCAR_GP_PIN(1, 12), /* A12 */ + [25] = RCAR_GP_PIN(1, 13), /* A13 */ + [26] = RCAR_GP_PIN(1, 14), /* A14 */ + [27] = RCAR_GP_PIN(1, 15), /* A15 */ + [28] = RCAR_GP_PIN(1, 16), /* A16 */ + [29] = RCAR_GP_PIN(1, 17), /* A17 */ + [30] = RCAR_GP_PIN(1, 18), /* A18 */ + [31] = RCAR_GP_PIN(1, 19), /* A19 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ + [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */ + [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */ + [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */ + [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */ + [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ + [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */ + [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */ + [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ + [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */ + [10] = RCAR_GP_PIN(0, 0), /* D0 */ + [11] = RCAR_GP_PIN(0, 1), /* D1 */ + [12] = RCAR_GP_PIN(0, 2), /* D2 */ + [13] = RCAR_GP_PIN(0, 3), /* D3 */ + [14] = RCAR_GP_PIN(0, 4), /* D4 */ + [15] = RCAR_GP_PIN(0, 5), /* D5 */ + [16] = RCAR_GP_PIN(0, 6), /* D6 */ + [17] = RCAR_GP_PIN(0, 7), /* D7 */ + [18] = RCAR_GP_PIN(0, 8), /* D8 */ + [19] = RCAR_GP_PIN(0, 9), /* D9 */ + [20] = RCAR_GP_PIN(0, 10), /* D10 */ + [21] = RCAR_GP_PIN(0, 11), /* D11 */ + [22] = RCAR_GP_PIN(0, 12), /* D12 */ + [23] = RCAR_GP_PIN(0, 13), /* D13 */ + [24] = RCAR_GP_PIN(0, 14), /* D14 */ + [25] = RCAR_GP_PIN(0, 15), /* D15 */ + [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ + [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ + [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */ + [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ + [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */ + [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */ + [ 1] = PIN_NONE, + [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */ + [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ + [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */ + [ 5] = PIN_A_NUMBER('T', 27), /* TCK */ + [ 6] = PIN_A_NUMBER('R', 30), /* TMS */ + [ 7] = PIN_A_NUMBER('R', 29), /* TDI */ + [ 8] = PIN_NONE, + [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */ + [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ + [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ + [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ + [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ + [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ + [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ + [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ + [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ + [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ + [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ + [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ + [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ + [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ + [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ + [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ + [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ + [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ + [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ + [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ + [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ + [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ + [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ + [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ + [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ + [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ + [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ + [13] = RCAR_GP_PIN(5, 1), /* RX0 */ + [14] = RCAR_GP_PIN(5, 2), /* TX0 */ + [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ + [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */ + [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ + [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ + [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ + [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */ + [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ + [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ + [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ + [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ + [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ + [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ + [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ + [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ + [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ + [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ + [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) { + [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ + [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ + [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ + [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ + [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ + [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ + [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */ + [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ + [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ + [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ + [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ + [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ + [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ + [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ + [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ + [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ + [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ + [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ + [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ + [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ + [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ + [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ + [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ + [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ + [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ + [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ + [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ + [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ + [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ + [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ + [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ + [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ + } }, + { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) { + [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ + [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ + [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ + [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ + [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ + [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ + [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ + [ 7] = PIN_NONE, + [ 8] = PIN_NONE, + [ 9] = PIN_NONE, + [10] = PIN_NONE, + [11] = PIN_NONE, + [12] = PIN_NONE, + [13] = PIN_NONE, + [14] = PIN_NONE, + [15] = PIN_NONE, + [16] = PIN_NONE, + [17] = PIN_NONE, + [18] = PIN_NONE, + [19] = PIN_NONE, + [20] = PIN_NONE, + [21] = PIN_NONE, + [22] = PIN_NONE, + [23] = PIN_NONE, + [24] = PIN_NONE, + [25] = PIN_NONE, + [26] = PIN_NONE, + [27] = PIN_NONE, + [28] = PIN_NONE, + [29] = PIN_NONE, + [30] = PIN_NONE, + [31] = PIN_NONE, + } }, + { /* sentinel */ }, }; static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - const struct sh_pfc_bias_info *info; - u32 reg; - u32 bit; + const struct pinmux_bias_reg *reg; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return PIN_CONFIG_BIAS_DISABLE; - reg = info->reg; - bit = BIT(info->bit); - - if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit)) + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) + else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) return PIN_CONFIG_BIAS_PULL_UP; else return PIN_CONFIG_BIAS_PULL_DOWN; @@ -5675,28 +5764,24 @@ static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - const struct sh_pfc_bias_info *info; + const struct pinmux_bias_reg *reg; u32 enable, updown; - u32 reg; - u32 bit; + unsigned int bit; - info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); - if (!info) + reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); + if (!reg) return; - reg = info->reg; - bit = BIT(info->bit); - - enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= bit; + enable |= BIT(bit); - updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= bit; + updown |= BIT(bit); - sh_pfc_write_reg(pfc, PUD + reg, 32, updown); - sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); + sh_pfc_write(pfc, reg->pud, updown); + sh_pfc_write(pfc, reg->puen, enable); } static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { @@ -5721,6 +5806,8 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = { .cfg_regs = pinmux_config_regs, .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c index 4f5ee1d7317d..89b7541ab1ed 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c @@ -198,8 +198,8 @@ #define GPSR6_0 FM(QSPI0_SPCLK) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ -#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -522,10 +522,8 @@ static const u16 pinmux_data[] = { /* IPSR0 */ PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), - PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN), PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), - PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU), PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), @@ -936,6 +934,129 @@ static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), }; +/* - AUDIO CLOCK ------------------------------------------------------------- */ +static const unsigned int audio_clk_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(4, 1), +}; +static const unsigned int audio_clk_a_mux[] = { + AUDIO_CLKA_MARK, +}; +static const unsigned int audio_clk_b_pins[] = { + /* CLK B */ + RCAR_GP_PIN(2, 27), +}; +static const unsigned int audio_clk_b_mux[] = { + AUDIO_CLKB_MARK, +}; +static const unsigned int audio_clkout_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(4, 5), +}; +static const unsigned int audio_clkout_mux[] = { + AUDIO_CLKOUT_MARK, +}; +static const unsigned int audio_clkout1_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(4, 22), +}; +static const unsigned int audio_clkout1_mux[] = { + AUDIO_CLKOUT1_MARK, +}; + +/* - EtherAVB --------------------------------------------------------------- */ +static const unsigned int avb0_link_pins[] = { + /* AVB0_LINK */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int avb0_link_mux[] = { + AVB0_LINK_MARK, +}; +static const unsigned int avb0_magic_pins[] = { + /* AVB0_MAGIC */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int avb0_magic_mux[] = { + AVB0_MAGIC_MARK, +}; +static const unsigned int avb0_phy_int_pins[] = { + /* AVB0_PHY_INT */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int avb0_phy_int_mux[] = { + AVB0_PHY_INT_MARK, +}; +static const unsigned int avb0_mdc_pins[] = { + /* AVB0_MDC, AVB0_MDIO */ + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16), +}; +static const unsigned int avb0_mdc_mux[] = { + AVB0_MDC_MARK, AVB0_MDIO_MARK, +}; +static const unsigned int avb0_mii_pins[] = { + /* + * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, + * AVB0_TD1, AVB0_TD2, AVB0_TD3, + * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, + * AVB0_RD1, AVB0_RD2, AVB0_RD3, + * AVB0_TXCREFCLK + */ + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 15), +}; +static const unsigned int avb0_mii_mux[] = { + AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK, + AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, + AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK, + AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, + AVB0_TXCREFCLK_MARK, +}; +static const unsigned int avb0_avtp_pps_a_pins[] = { + /* AVB0_AVTP_PPS_A */ + RCAR_GP_PIN(5, 2), +}; +static const unsigned int avb0_avtp_pps_a_mux[] = { + AVB0_AVTP_PPS_A_MARK, +}; +static const unsigned int avb0_avtp_match_a_pins[] = { + /* AVB0_AVTP_MATCH_A */ + RCAR_GP_PIN(5, 1), +}; +static const unsigned int avb0_avtp_match_a_mux[] = { + AVB0_AVTP_MATCH_A_MARK, +}; +static const unsigned int avb0_avtp_capture_a_pins[] = { + /* AVB0_AVTP_CAPTURE_A */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int avb0_avtp_capture_a_mux[] = { + AVB0_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int avb0_avtp_pps_b_pins[] = { + /* AVB0_AVTP_PPS_B */ + RCAR_GP_PIN(4, 16), +}; +static const unsigned int avb0_avtp_pps_b_mux[] = { + AVB0_AVTP_PPS_B_MARK, +}; +static const unsigned int avb0_avtp_match_b_pins[] = { + /* AVB0_AVTP_MATCH_B */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int avb0_avtp_match_b_mux[] = { + AVB0_AVTP_MATCH_B_MARK, +}; +static const unsigned int avb0_avtp_capture_b_pins[] = { + /* AVB0_AVTP_CAPTURE_B */ + RCAR_GP_PIN(4, 17), +}; +static const unsigned int avb0_avtp_capture_b_mux[] = { + AVB0_AVTP_CAPTURE_B_MARK, +}; + /* - I2C -------------------------------------------------------------------- */ static const unsigned int i2c0_pins[] = { /* SCL, SDA */ @@ -1018,6 +1139,118 @@ static const unsigned int mmc_ctrl_mux[] = { MMC_CLK_MARK, MMC_CMD_MARK, }; +/* - PWM0 ------------------------------------------------------------------ */ +static const unsigned int pwm0_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 1), +}; + +static const unsigned int pwm0_a_mux[] = { + PWM0_A_MARK, +}; + +static const unsigned int pwm0_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 18), +}; + +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; + +static const unsigned int pwm0_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 29), +}; + +static const unsigned int pwm0_c_mux[] = { + PWM0_C_MARK, +}; + +/* - PWM1 ------------------------------------------------------------------ */ +static const unsigned int pwm1_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 2), +}; + +static const unsigned int pwm1_a_mux[] = { + PWM1_A_MARK, +}; + +static const unsigned int pwm1_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 19), +}; + +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; + +static const unsigned int pwm1_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 30), +}; + +static const unsigned int pwm1_c_mux[] = { + PWM1_C_MARK, +}; + +/* - PWM2 ------------------------------------------------------------------ */ +static const unsigned int pwm2_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 3), +}; + +static const unsigned int pwm2_a_mux[] = { + PWM2_A_MARK, +}; + +static const unsigned int pwm2_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 22), +}; + +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; + +static const unsigned int pwm2_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 31), +}; + +static const unsigned int pwm2_c_mux[] = { + PWM2_C_MARK, +}; + +/* - PWM3 ------------------------------------------------------------------ */ +static const unsigned int pwm3_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 4), +}; + +static const unsigned int pwm3_a_mux[] = { + PWM3_A_MARK, +}; + +static const unsigned int pwm3_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 27), +}; + +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; + +static const unsigned int pwm3_c_pins[] = { + /* PWM */ + RCAR_GP_PIN(4, 0), +}; + +static const unsigned int pwm3_c_mux[] = { + PWM3_C_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -1202,7 +1435,75 @@ static const unsigned int scif_clk_mux[] = { SCIF_CLK_MARK, }; +/* - SSI ---------------------------------------------------------------*/ +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(4, 3), +}; +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; +static const unsigned int ssi34_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4), +}; +static const unsigned int ssi34_ctrl_mux[] = { + SSI_SCK34_MARK, SSI_WS34_MARK, +}; +static const unsigned int ssi4_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), +}; +static const unsigned int ssi4_ctrl_a_mux[] = { + SSI_SCK4_A_MARK, SSI_WS4_A_MARK, +}; +static const unsigned int ssi4_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int ssi4_data_a_mux[] = { + SSI_SDATA4_A_MARK, +}; +static const unsigned int ssi4_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20), +}; +static const unsigned int ssi4_ctrl_b_mux[] = { + SSI_SCK4_B_MARK, SSI_WS4_B_MARK, +}; +static const unsigned int ssi4_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(2, 16), +}; +static const unsigned int ssi4_data_b_mux[] = { + SSI_SDATA4_B_MARK, +}; + +/* - USB0 ------------------------------------------------------------------- */ +static const unsigned int usb0_pins[] = { + /* PWEN, OVC */ + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), +}; +static const unsigned int usb0_mux[] = { + USB0_PWEN_MARK, USB0_OVC_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(audio_clkout1), + SH_PFC_PIN_GROUP(avb0_link), + SH_PFC_PIN_GROUP(avb0_magic), + SH_PFC_PIN_GROUP(avb0_phy_int), + SH_PFC_PIN_GROUP(avb0_mdc), + SH_PFC_PIN_GROUP(avb0_mii), + SH_PFC_PIN_GROUP(avb0_avtp_pps_a), + SH_PFC_PIN_GROUP(avb0_avtp_match_a), + SH_PFC_PIN_GROUP(avb0_avtp_capture_a), + SH_PFC_PIN_GROUP(avb0_avtp_pps_b), + SH_PFC_PIN_GROUP(avb0_avtp_match_b), + SH_PFC_PIN_GROUP(avb0_avtp_capture_b), SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1), SH_PFC_PIN_GROUP(i2c2_a), @@ -1213,6 +1514,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(mmc_data4), SH_PFC_PIN_GROUP(mmc_data8), SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(pwm0_a), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm0_c), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm1_c), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm2_c), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm3_c), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_data_b), @@ -1238,6 +1551,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_b), SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_ctrl_a), + SH_PFC_PIN_GROUP(ssi4_data_a), + SH_PFC_PIN_GROUP(ssi4_ctrl_b), + SH_PFC_PIN_GROUP(ssi4_data_b), + SH_PFC_PIN_GROUP(usb0), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a", + "audio_clk_b", + "audio_clkout", + "audio_clkout1", +}; + +static const char * const avb0_groups[] = { + "avb0_link", + "avb0_magic", + "avb0_phy_int", + "avb0_mdc", + "avb0_mii", + "avb0_avtp_pps_a", + "avb0_avtp_match_a", + "avb0_avtp_capture_a", + "avb0_avtp_pps_b", + "avb0_avtp_match_b", + "avb0_avtp_capture_b", }; static const char * const i2c0_groups[] = { @@ -1264,6 +1605,30 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +static const char * const pwm0_groups[] = { + "pwm0_a", + "pwm0_b", + "pwm0_c", +}; + +static const char * const pwm1_groups[] = { + "pwm1_a", + "pwm1_b", + "pwm1_c", +}; + +static const char * const pwm2_groups[] = { + "pwm2_a", + "pwm2_b", + "pwm2_c", +}; + +static const char * const pwm3_groups[] = { + "pwm3_a", + "pwm3_b", + "pwm3_c", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_clk_a", @@ -1310,12 +1675,31 @@ static const char * const scif_clk_groups[] = { "scif_clk", }; +static const char * const ssi_groups[] = { + "ssi3_data", + "ssi34_ctrl", + "ssi4_ctrl_a", + "ssi4_data_a", + "ssi4_ctrl_b", + "ssi4_data_b", +}; + +static const char * const usb0_groups[] = { + "usb0", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb0), SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -1323,6 +1707,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(usb0), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c index 29c69133b0ef..0e733bffdb38 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include <linux/init.h> #include <linux/kernel.h> #include <linux/gpio.h> diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 5c9d79981e6d..736634aee500 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -513,7 +513,7 @@ static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, return -EINVAL; spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read_reg(pfc, reg, 32); + val = sh_pfc_read(pfc, reg); spin_unlock_irqrestore(&pfc->lock, flags); val = (val >> offset) & GENMASK(size - 1, 0); @@ -550,11 +550,11 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read_reg(pfc, reg, 32); + val = sh_pfc_read(pfc, reg); val &= ~GENMASK(offset + size - 1, offset); val |= strength << offset; - sh_pfc_write_reg(pfc, reg, 32, val); + sh_pfc_write(pfc, reg, val); spin_unlock_irqrestore(&pfc->lock, flags); @@ -645,7 +645,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, return bit; spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read_reg(pfc, pocctrl, 32); + val = sh_pfc_read(pfc, pocctrl); spin_unlock_irqrestore(&pfc->lock, flags); arg = (val & BIT(bit)) ? 3300 : 1800; @@ -716,12 +716,12 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, return -EINVAL; spin_lock_irqsave(&pfc->lock, flags); - val = sh_pfc_read_reg(pfc, pocctrl, 32); + val = sh_pfc_read(pfc, pocctrl); if (mV == 3300) val |= BIT(bit); else val &= ~BIT(bit); - sh_pfc_write_reg(pfc, pocctrl, 32, val); + sh_pfc_write(pfc, pocctrl, val); spin_unlock_irqrestore(&pfc->lock, flags); break; diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 8688b405e081..213108a058fe 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -148,6 +148,21 @@ struct pinmux_drive_reg { .reg = r, \ .fields = +struct pinmux_bias_reg { + u32 puen; /* Pull-enable or pull-up control register */ + u32 pud; /* Pull-up/down control register (optional) */ + const u16 pins[32]; +}; + +#define PINMUX_BIAS_REG(name1, r1, name2, r2) \ + .puen = r1, \ + .pud = r2, \ + .pins = + +struct pinmux_ioctrl_reg { + u32 reg; +}; + struct pinmux_data_reg { u32 reg; u8 reg_width; @@ -189,12 +204,6 @@ struct sh_pfc_window { unsigned long size; }; -struct sh_pfc_bias_info { - u16 pin; - u16 reg : 11; - u16 bit : 5; -}; - struct sh_pfc_pin_range; struct sh_pfc { @@ -213,6 +222,7 @@ struct sh_pfc { unsigned int nr_gpio_pins; struct sh_pfc_chip *gpio; + u32 *saved_regs; }; struct sh_pfc_soc_operations { @@ -245,6 +255,8 @@ struct sh_pfc_soc_info { const struct pinmux_cfg_reg *cfg_regs; const struct pinmux_drive_reg *drive_regs; + const struct pinmux_bias_reg *bias_regs; + const struct pinmux_ioctrl_reg *ioctrl_regs; const struct pinmux_data_reg *data_regs; const u16 *pinmux_data; diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 4db9323251e3..3abb028f6158 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -5820,7 +5820,7 @@ static void atlas7_gpio_handle_irq(struct irq_desc *desc) __func__, gc->label, bank->gpio_offset + pin_in_bank); generic_handle_irq( - irq_find_mapping(gc->irqdomain, + irq_find_mapping(gc->irq.domain, bank->gpio_offset + pin_in_bank)); } @@ -5860,7 +5860,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip, if (ret < 0) return ret; - if (pinctrl_request_gpio(chip->base + gpio)) + if (pinctrl_gpio_request(chip->base + gpio)) return -ENODEV; raw_spin_lock_irqsave(&a7gc->lock, flags); @@ -5890,7 +5890,7 @@ static void atlas7_gpio_free(struct gpio_chip *chip, raw_spin_unlock_irqrestore(&a7gc->lock, flags); - pinctrl_free_gpio(chip->base + gpio); + pinctrl_gpio_free(chip->base + gpio); } static int atlas7_gpio_direction_input(struct gpio_chip *chip, diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index d3ef05973901..ca2347d0d579 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -587,7 +587,7 @@ static void sirfsoc_gpio_handle_irq(struct irq_desc *desc) if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { pr_debug("%s: gpio id %d idx %d happens\n", __func__, bank->id, idx); - generic_handle_irq(irq_find_mapping(gc->irqdomain, idx + + generic_handle_irq(irq_find_mapping(gc->irq.domain, idx + bank->id * SIRFSOC_GPIO_BANK_SIZE)); } @@ -614,7 +614,7 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset) struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); unsigned long flags; - if (pinctrl_request_gpio(chip->base + offset)) + if (pinctrl_gpio_request(chip->base + offset)) return -ENODEV; spin_lock_irqsave(&bank->lock, flags); @@ -644,7 +644,7 @@ static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset) spin_unlock_irqrestore(&bank->lock, flags); - pinctrl_free_gpio(chip->base + offset); + pinctrl_gpio_free(chip->base + offset); } static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile index 37b8412ac8a3..da52d17550a3 100644 --- a/drivers/pinctrl/spear/Makefile +++ b/drivers/pinctrl/spear/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # SPEAr pinmux support obj-$(CONFIG_PINCTRL_SPEAR_PLGPIO) += pinctrl-plgpio.o diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c index cf6d68c7345b..6a0ed8ab33b9 100644 --- a/drivers/pinctrl/spear/pinctrl-plgpio.c +++ b/drivers/pinctrl/spear/pinctrl-plgpio.c @@ -204,7 +204,7 @@ static int plgpio_request(struct gpio_chip *chip, unsigned offset) if (offset >= chip->ngpio) return -EINVAL; - ret = pinctrl_request_gpio(gpio); + ret = pinctrl_gpio_request(gpio); if (ret) return ret; @@ -242,7 +242,7 @@ err1: if (!IS_ERR(plgpio->clk)) clk_disable(plgpio->clk); err0: - pinctrl_free_gpio(gpio); + pinctrl_gpio_free(gpio); return ret; } @@ -273,7 +273,7 @@ disable_clk: if (!IS_ERR(plgpio->clk)) clk_disable(plgpio->clk); - pinctrl_free_gpio(gpio); + pinctrl_gpio_free(gpio); } /* PLGPIO IRQ */ @@ -401,7 +401,7 @@ static void plgpio_irq_handler(struct irq_desc *desc) /* get correct irq line number */ pin = i * MAX_GPIO_PER_REG + pin; generic_handle_irq( - irq_find_mapping(gc->irqdomain, pin)); + irq_find_mapping(gc->irq.domain, pin)); } } chained_irq_exit(irqchip, desc); diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile index 5f379f5153f1..d13ca3573486 100644 --- a/drivers/pinctrl/stm32/Makefile +++ b/drivers/pinctrl/stm32/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Core obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 50299ad96659..a276c61be217 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -150,12 +150,12 @@ static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) return -EINVAL; } - return pinctrl_request_gpio(chip->base + offset); + return pinctrl_gpio_request(chip->base + offset); } static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) { - pinctrl_free_gpio(chip->base + offset); + pinctrl_gpio_free(chip->base + offset); } static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) @@ -289,13 +289,14 @@ static int stm32_gpio_domain_translate(struct irq_domain *d, return 0; } -static void stm32_gpio_domain_activate(struct irq_domain *d, - struct irq_data *irq_data) +static int stm32_gpio_domain_activate(struct irq_domain *d, + struct irq_data *irq_data, bool early) { struct stm32_gpio_bank *bank = d->host_data; struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr); + return 0; } static int stm32_gpio_domain_alloc(struct irq_domain *d, diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index dc6c9619e41c..12a752e836ef 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # Core obj-y += pinctrl-sunxi.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index f763d8d62d6e..295e48fc94bc 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -1289,6 +1289,7 @@ static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { .npins = ARRAY_SIZE(sun4i_a10_pins), .irq_banks = 1, .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i.c b/drivers/pinctrl/sunxi/pinctrl-sun5i.c index 47afd558b114..27ec99e81c4c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun5i.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun5i.c @@ -713,6 +713,7 @@ static const struct sunxi_pinctrl_desc sun5i_pinctrl_data = { .pins = sun5i_pins, .npins = ARRAY_SIZE(sun5i_pins), .irq_banks = 1, + .disable_strict_mode = true, }; static int sun5i_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c index 49a1deb97bb7..a00246d3dd49 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c @@ -106,6 +106,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = { .npins = ARRAY_SIZE(sun6i_a31_r_pins), .pin_base = PL_BASE, .irq_banks = 2, + .disable_strict_mode = true, }; static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c index 951a25c18815..82ffaf466892 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c @@ -965,6 +965,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = { .pins = sun6i_a31_pins, .npins = ARRAY_SIZE(sun6i_a31_pins), .irq_banks = 4, + .disable_strict_mode = true, }; static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c index 67ee6f9b3b68..8a08c4afc6a8 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -93,6 +93,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = { .npins = ARRAY_SIZE(sun8i_a23_r_pins), .pin_base = PL_BASE, .irq_banks = 1, + .disable_strict_mode = true, }; static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c index 721b6935baf3..402fd7d21e7b 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c @@ -563,6 +563,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = { .pins = sun8i_a23_pins, .npins = ARRAY_SIZE(sun8i_a23_pins), .irq_banks = 3, + .disable_strict_mode = true, }; static int sun8i_a23_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c index ef1e0bef4099..da387211a75e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c @@ -486,6 +486,7 @@ static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = { .npins = ARRAY_SIZE(sun8i_a33_pins), .irq_banks = 2, .irq_bank_base = 1, + .disable_strict_mode = true, }; static int sun8i_a33_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c index ebfd9a26628c..b795a199e240 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c @@ -82,7 +82,8 @@ static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = { .npins = ARRAY_SIZE(sun8i_h3_r_pins), .irq_banks = 1, .pin_base = PL_BASE, - .irq_read_needs_mux = true + .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c index 518a92df4418..d1719a738c20 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c @@ -491,7 +491,8 @@ static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = { .pins = sun8i_h3_pins, .npins = ARRAY_SIZE(sun8i_h3_pins), .irq_banks = 2, - .irq_read_needs_mux = true + .irq_read_needs_mux = true, + .disable_strict_mode = true, }; static int sun8i_h3_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c index 92a873f73697..c63086c98335 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c @@ -152,6 +152,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = { .npins = ARRAY_SIZE(sun9i_a80_r_pins), .pin_base = PL_BASE, .irq_banks = 2, + .disable_strict_mode = true, }; static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index bc14e954d7a2..472ef0d91b99 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -721,6 +721,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { .pins = sun9i_a80_pins, .npins = ARRAY_SIZE(sun9i_a80_pins), .irq_banks = 5, + .disable_strict_mode = true, }; static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 52edf3b5988d..4b6cb25bc796 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -696,6 +696,7 @@ static const struct pinmux_ops sunxi_pmx_ops = { .get_function_groups = sunxi_pmx_get_func_groups, .set_mux = sunxi_pmx_set_mux, .gpio_set_direction = sunxi_pmx_gpio_set_direction, + .strict = true, }; static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, @@ -1245,6 +1246,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, struct pinctrl_desc *pctrl_desc; struct pinctrl_pin_desc *pins; struct sunxi_pinctrl *pctl; + struct pinmux_ops *pmxops; struct resource *res; int i, ret, last_pin, pin_idx; struct clk *clk; @@ -1305,7 +1307,16 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, pctrl_desc->npins = pctl->ngroups; pctrl_desc->confops = &sunxi_pconf_ops; pctrl_desc->pctlops = &sunxi_pctrl_ops; - pctrl_desc->pmxops = &sunxi_pmx_ops; + + pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops), + GFP_KERNEL); + if (!pmxops) + return -ENOMEM; + + if (desc->disable_strict_mode) + pmxops->strict = false; + + pctrl_desc->pmxops = pmxops; pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); if (IS_ERR(pctl->pctl_dev)) { diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 1bfc0d8a55df..11b128f54ed2 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -112,6 +112,7 @@ struct sunxi_pinctrl_desc { unsigned irq_banks; unsigned irq_bank_base; bool irq_read_needs_mux; + bool disable_strict_mode; }; struct sunxi_pinctrl_function { diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile index d9ea2be69cc4..bbcb043c34a2 100644 --- a/drivers/pinctrl/tegra/Makefile +++ b/drivers/pinctrl/tegra/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 5c1b6325d80d..a8a6510183b6 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -575,11 +575,9 @@ static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned long *config) { struct ti_iodelay_device *iod; - struct device *dev; struct ti_iodelay_pingroup *group; iod = pinctrl_dev_get_drvdata(pctldev); - dev = iod->dev; group = ti_iodelay_get_pingroup(iod, selector); if (!group) @@ -693,12 +691,10 @@ static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, unsigned int selector) { struct ti_iodelay_device *iod; - struct device *dev; struct ti_iodelay_pingroup *group; int i; iod = pinctrl_dev_get_drvdata(pctldev); - dev = iod->dev; group = ti_iodelay_get_pingroup(iod, selector); if (!group) return; diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile index d592ff77d60f..ec66c86e276e 100644 --- a/drivers/pinctrl/uniphier/Makefile +++ b/drivers/pinctrl/uniphier/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 obj-y += pinctrl-uniphier-core.o obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index f9267fabe6b0..26fda5c53e65 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -204,9 +204,10 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev, const struct pin_desc *desc = pin_desc_get(pctldev, pin); enum uniphier_pin_drv_type type = uniphier_pin_get_drv_type(desc->drv_data); - const unsigned int strength_1bit[] = {4, 8}; - const unsigned int strength_2bit[] = {8, 12, 16, 20}; - const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16}; + static const unsigned int strength_1bit[] = {4, 8}; + static const unsigned int strength_2bit[] = {8, 12, 16, 20}; + static const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, + 14, 16}; const unsigned int *supported_strength; unsigned int drvctrl, reg, shift, mask, width, val; int ret; @@ -399,9 +400,10 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev, const struct pin_desc *desc = pin_desc_get(pctldev, pin); enum uniphier_pin_drv_type type = uniphier_pin_get_drv_type(desc->drv_data); - const unsigned int strength_1bit[] = {4, 8, -1}; - const unsigned int strength_2bit[] = {8, 12, 16, 20, -1}; - const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16, -1}; + static const unsigned int strength_1bit[] = {4, 8, -1}; + static const unsigned int strength_2bit[] = {8, 12, 16, 20, -1}; + static const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, + 16, -1}; const unsigned int *supported_strength; unsigned int drvctrl, reg, shift, mask, width, val; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 9c5e359a63de..8a5ecd6277d8 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -472,8 +472,8 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = { static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142}; static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; -static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25}; -static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25}; +static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29}; static const int emmc_dat8_muxvals[] = {0, 0, 0, 0}; static const unsigned ether_rmii_pins[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 83341284dc44..3be7967edae0 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -553,8 +553,8 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = { static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142}; static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; -static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25}; -static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25}; +static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29}; static const int emmc_dat8_muxvals[] = {0, 0, 0, 0}; static const unsigned ether_rgmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 38, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index d9f166f0cc86..dbe94a9a0353 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -776,8 +776,8 @@ static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = { 250, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned int emmc_pins[] = {31, 32, 33, 34, 35, 36, 37, 38}; -static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38}; +static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; static const unsigned int emmc_dat8_pins[] = {39, 40, 41, 42}; static const int emmc_dat8_muxvals[] = {0, 0, 0, 0}; static const unsigned int ether_rgmii_pins[] = {52, 53, 54, 55, 56, 57, 58, 59, diff --git a/drivers/pinctrl/vt8500/Makefile b/drivers/pinctrl/vt8500/Makefile index 24ec45dd0d80..c6a5c3b14e9e 100644 --- a/drivers/pinctrl/vt8500/Makefile +++ b/drivers/pinctrl/vt8500/Makefile @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 # VIA/Wondermedia pinctrl support obj-$(CONFIG_PINCTRL_WMT) += pinctrl-wmt.o |