diff options
Diffstat (limited to 'drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c')
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 4c0d26606b6c..69a05a03dd63 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -279,7 +279,7 @@ FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); #define B20 32 SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); -SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0); SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC); SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE); PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN); @@ -299,7 +299,7 @@ FUNC_GROUP_DECL(GPIE0, B20, C20); #define F18 34 SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); -SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2); SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC); SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE); PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN); @@ -1412,7 +1412,7 @@ FUNC_GROUP_DECL(ADC15, H4); #define R22 192 SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); -SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_DECL_SINGLE(SIOS3, ACPI); SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI); SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22); @@ -1420,7 +1420,7 @@ FUNC_GROUP_DECL(SIOS3, R22); #define R21 193 SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); -SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_DECL_SINGLE(SIOS5, ACPI); SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI); SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21); @@ -1436,7 +1436,7 @@ FUNC_GROUP_DECL(SIOPWREQ, P22); #define P21 195 SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); -SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI); SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI); SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21); @@ -2785,6 +2785,22 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +#define GPIOE1 33 +#define GPIOE3 35 +static void aspeed_g5_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + /* + * If we're freeing GPIOE1 (33) or GPIOE3 (35) then re-enable the + * pass-through mux setting; otherwise, do nothing. + */ + if (offset != GPIOE1 && offset != GPIOE3) + return; + + aspeed_gpio_disable_free(pctldev, range, offset); +} + static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = { { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, @@ -2820,6 +2836,7 @@ static const struct pinmux_ops aspeed_g5_pinmux_ops = { .get_function_groups = aspeed_pinmux_get_fn_groups, .set_mux = aspeed_pinmux_set_mux, .gpio_request_enable = aspeed_gpio_request_enable, + .gpio_disable_free = aspeed_g5_gpio_disable_free, .strict = true, }; |