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-rw-r--r--drivers/mtd/spi-nor/Kconfig8
-rw-r--r--drivers/mtd/spi-nor/Makefile1
-rw-r--r--drivers/mtd/spi-nor/aspeed-smc.c292
-rw-r--r--drivers/mtd/spi-nor/npcm-fiu.c930
-rw-r--r--drivers/mtd/spi-nor/spi-nor.c2
5 files changed, 1220 insertions, 13 deletions
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 37775fc09e09..5af9d5f77076 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -75,6 +75,14 @@ config SPI_HISI_SFC
help
This enables support for hisilicon SPI-NOR flash controller.
+config SPI_NPCM_FIU
+ tristate "NPCM FLASH Interface unit(FIU) controller "
+ depends on ARCH_NPCM || COMPILE_TEST
+ help
+ This enables support for the FLASH Interface unit(FIU) controller.
+ This driver does not support generic SPI. The implementation only
+ supports SPI NOR.
+
config SPI_NXP_SPIFI
tristate "NXP SPI Flash Interface (SPIFI)"
depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index f4c61d282abd..fe0e2bdef9cd 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
+obj-$(CONFIG_SPI_NPCM_FIU) += npcm-fiu.o
obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index 95e54468cf7d..ddf7ae78aa0a 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -10,6 +10,7 @@
*/
#include <linux/bug.h>
+#include <linux/clk.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -20,6 +21,7 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/sizes.h>
+#include <linux/slab.h>
#include <linux/sysfs.h>
#define DEVICE_NAME "aspeed-smc"
@@ -41,12 +43,16 @@ struct aspeed_smc_info {
bool hastype; /* flash type field exists in config reg */
u8 we0; /* shift for write enable bit for CE0 */
u8 ctl0; /* offset in regs of ctl for CE0 */
+ u8 timing; /* offset in regs of timing */
void (*set_4b)(struct aspeed_smc_chip *chip);
+ int (*optimize_read)(struct aspeed_smc_chip *chip, u32 max_freq);
};
static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip);
static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip);
+static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip,
+ u32 max_freq);
static const struct aspeed_smc_info fmc_2400_info = {
.maxsize = 64 * 1024 * 1024,
@@ -54,7 +60,9 @@ static const struct aspeed_smc_info fmc_2400_info = {
.hastype = true,
.we0 = 16,
.ctl0 = 0x10,
+ .timing = 0x94,
.set_4b = aspeed_smc_chip_set_4b,
+ .optimize_read = aspeed_smc_optimize_read,
};
static const struct aspeed_smc_info spi_2400_info = {
@@ -63,7 +71,9 @@ static const struct aspeed_smc_info spi_2400_info = {
.hastype = false,
.we0 = 0,
.ctl0 = 0x04,
+ .timing = 0x14,
.set_4b = aspeed_smc_chip_set_4b_spi_2400,
+ .optimize_read = aspeed_smc_optimize_read,
};
static const struct aspeed_smc_info fmc_2500_info = {
@@ -72,7 +82,9 @@ static const struct aspeed_smc_info fmc_2500_info = {
.hastype = true,
.we0 = 16,
.ctl0 = 0x10,
+ .timing = 0x94,
.set_4b = aspeed_smc_chip_set_4b,
+ .optimize_read = aspeed_smc_optimize_read,
};
static const struct aspeed_smc_info spi_2500_info = {
@@ -81,7 +93,9 @@ static const struct aspeed_smc_info spi_2500_info = {
.hastype = false,
.we0 = 16,
.ctl0 = 0x10,
+ .timing = 0x94,
.set_4b = aspeed_smc_chip_set_4b,
+ .optimize_read = aspeed_smc_optimize_read,
};
enum aspeed_smc_ctl_reg_value {
@@ -102,6 +116,7 @@ struct aspeed_smc_chip {
u32 ctl_val[smc_max]; /* control settings */
enum aspeed_smc_flash_type type; /* what type of flash */
struct spi_nor nor;
+ u32 clk_rate;
};
struct aspeed_smc_controller {
@@ -113,9 +128,13 @@ struct aspeed_smc_controller {
void __iomem *ahb_base; /* per-chip windows resource */
u32 ahb_window_size; /* full mapping window size */
+ unsigned long clk_frequency;
+
struct aspeed_smc_chip *chips[0]; /* pointers to attached chips */
};
+#define ASPEED_SPI_DEFAULT_FREQ 50000000
+
/*
* SPI Flash Configuration Register (AST2500 SPI)
* or
@@ -202,6 +221,12 @@ struct aspeed_smc_controller {
((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4)
/*
+ * Switch to turn off read optimisation if needed
+ */
+static bool optimize_read = true;
+module_param(optimize_read, bool, 0644);
+
+/*
* In user mode all data bytes read or written to the chip decode address
* range are transferred to or from the SPI bus. The range is treated as a
* fifo of arbitratry 1, 2, or 4 byte width but each write has to be aligned
@@ -373,18 +398,49 @@ static void aspeed_smc_send_cmd_addr(struct spi_nor *nor, u8 cmd, u32 addr)
}
}
+static int aspeed_smc_get_io_mode(struct aspeed_smc_chip *chip)
+{
+ switch (chip->nor.read_proto) {
+ case SNOR_PROTO_1_1_1:
+ return 0;
+ case SNOR_PROTO_1_1_2:
+ return CONTROL_IO_DUAL_DATA;
+ case SNOR_PROTO_1_2_2:
+ return CONTROL_IO_DUAL_ADDR_DATA;
+ default:
+ dev_err(chip->nor.dev, "unsupported SPI read mode\n");
+ return -EINVAL;
+ }
+}
+
+static void aspeed_smc_set_io_mode(struct aspeed_smc_chip *chip, u32 io_mode)
+{
+ u32 ctl;
+
+ if (io_mode > 0) {
+ ctl = readl(chip->ctl) & ~CONTROL_IO_MODE_MASK;
+ ctl |= io_mode;
+ writel(ctl, chip->ctl);
+ }
+}
+
static ssize_t aspeed_smc_read_user(struct spi_nor *nor, loff_t from,
size_t len, u_char *read_buf)
{
struct aspeed_smc_chip *chip = nor->priv;
int i;
u8 dummy = 0xFF;
+ int io_mode = aspeed_smc_get_io_mode(chip);
aspeed_smc_start_user(nor);
aspeed_smc_send_cmd_addr(nor, nor->read_opcode, from);
for (i = 0; i < chip->nor.read_dummy / 8; i++)
aspeed_smc_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
+ /* Set IO mode only for data */
+ if (io_mode == CONTROL_IO_DUAL_DATA)
+ aspeed_smc_set_io_mode(chip, io_mode);
+
aspeed_smc_read_from_ahb(read_buf, chip->ahb_base, len);
aspeed_smc_stop_user(nor);
return len;
@@ -402,6 +458,31 @@ static ssize_t aspeed_smc_write_user(struct spi_nor *nor, loff_t to,
return len;
}
+static ssize_t aspeed_smc_read(struct spi_nor *nor, loff_t from, size_t len,
+ u_char *read_buf)
+{
+ struct aspeed_smc_chip *chip = nor->priv;
+
+ /*
+ * The AHB window configured for the chip is too small for the
+ * read offset. Use the "User mode" of the controller to
+ * perform the read.
+ */
+ if (from >= chip->ahb_window_size) {
+ aspeed_smc_read_user(nor, from, len, read_buf);
+ goto out;
+ }
+
+ /*
+ * Use the "Command mode" to do a direct read from the AHB
+ * window configured for the chip. This should be the default.
+ */
+ memcpy_fromio(read_buf, chip->ahb_base + from, len);
+
+out:
+ return len;
+}
+
static int aspeed_smc_unregister(struct aspeed_smc_controller *controller)
{
struct aspeed_smc_chip *chip;
@@ -706,10 +787,179 @@ static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip,
return 0;
}
+
+#define CALIBRATE_BUF_SIZE 16384
+
+static bool aspeed_smc_check_reads(struct aspeed_smc_chip *chip,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ int i;
+
+ for (i = 0; i < 10; i++) {
+ aspeed_smc_read_from_ahb(test_buf, chip->ahb_base,
+ CALIBRATE_BUF_SIZE);
+ if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0)
+ return false;
+ }
+ return true;
+}
+
+static int aspeed_smc_calibrate_reads(struct aspeed_smc_chip *chip, u32 hdiv,
+ const u8 *golden_buf, u8 *test_buf)
+{
+ struct aspeed_smc_controller *controller = chip->controller;
+ const struct aspeed_smc_info *info = controller->info;
+ int i;
+ int good_pass = -1, pass_count = 0;
+ u32 shift = (hdiv - 1) << 2;
+ u32 mask = ~(0xfu << shift);
+ u32 fread_timing_val = 0;
+
+#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
+
+ /* Try HCLK delay 0..5, each one with/without delay and look for a
+ * good pair.
+ */
+ for (i = 0; i < 12; i++) {
+ bool pass;
+
+ fread_timing_val &= mask;
+ fread_timing_val |= FREAD_TPASS(i) << shift;
+
+ writel(fread_timing_val, controller->regs + info->timing);
+ pass = aspeed_smc_check_reads(chip, golden_buf, test_buf);
+ dev_dbg(chip->nor.dev,
+ " * [%08x] %d HCLK delay, %dns DI delay : %s",
+ fread_timing_val, i/2, (i & 1) ? 0 : 4,
+ pass ? "PASS" : "FAIL");
+ if (pass) {
+ pass_count++;
+ if (pass_count == 3) {
+ good_pass = i - 1;
+ break;
+ }
+ } else
+ pass_count = 0;
+ }
+
+ /* No good setting for this frequency */
+ if (good_pass < 0)
+ return -1;
+
+ /* We have at least one pass of margin, let's use first pass */
+ fread_timing_val &= mask;
+ fread_timing_val |= FREAD_TPASS(good_pass) << shift;
+ writel(fread_timing_val, controller->regs + info->timing);
+ dev_dbg(chip->nor.dev, " * -> good is pass %d [0x%08x]",
+ good_pass, fread_timing_val);
+ return 0;
+}
+
+static bool aspeed_smc_check_calib_data(const u8 *test_buf, u32 size)
+{
+ const u32 *tb32 = (const u32 *) test_buf;
+ u32 i, cnt = 0;
+
+ /* We check if we have enough words that are neither all 0
+ * nor all 1's so the calibration can be considered valid.
+ *
+ * I use an arbitrary threshold for now of 64
+ */
+ size >>= 2;
+ for (i = 0; i < size; i++) {
+ if (tb32[i] != 0 && tb32[i] != 0xffffffff)
+ cnt++;
+ }
+ return cnt >= 64;
+}
+
+static const uint32_t aspeed_smc_hclk_divs[] = {
+ 0xf, /* HCLK */
+ 0x7, /* HCLK/2 */
+ 0xe, /* HCLK/3 */
+ 0x6, /* HCLK/4 */
+ 0xd, /* HCLK/5 */
+};
+#define ASPEED_SMC_HCLK_DIV(i) (aspeed_smc_hclk_divs[(i) - 1] << 8)
+
+static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip,
+ u32 max_freq)
+{
+ u8 *golden_buf, *test_buf;
+ int i, rc, best_div = -1;
+ u32 save_read_val = chip->ctl_val[smc_read];
+ u32 ahb_freq = chip->controller->clk_frequency;
+
+ dev_dbg(chip->nor.dev, "AHB frequency: %d MHz", ahb_freq / 1000000);
+
+ test_buf = kmalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
+ golden_buf = test_buf + CALIBRATE_BUF_SIZE;
+
+ /* We start with the dumbest setting (keep 4Byte bit) and read
+ * some data
+ */
+ chip->ctl_val[smc_read] = (chip->ctl_val[smc_read] & 0x2000) |
+ (0x00 << 28) | /* Single bit */
+ (0x00 << 24) | /* CE# max */
+ (0x03 << 16) | /* use normal reads */
+ (0x00 << 8) | /* HCLK/16 */
+ (0x00 << 6) | /* no dummy cycle */
+ (0x00); /* normal read */
+
+ writel(chip->ctl_val[smc_read], chip->ctl);
+
+ aspeed_smc_read_from_ahb(golden_buf, chip->ahb_base,
+ CALIBRATE_BUF_SIZE);
+
+ /* Establish our read mode with freq field set to 0 (HCLK/16) */
+ chip->ctl_val[smc_read] = save_read_val & 0xfffff0ff;
+
+ /* Check if calibration data is suitable */
+ if (!aspeed_smc_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
+ dev_info(chip->nor.dev,
+ "Calibration area too uniform, using low speed");
+ writel(chip->ctl_val[smc_read], chip->ctl);
+ kfree(test_buf);
+ return 0;
+ }
+
+ /* Now we iterate the HCLK dividers until we find our breaking point */
+ for (i = ARRAY_SIZE(aspeed_smc_hclk_divs); i > 0; i--) {
+ u32 tv, freq;
+
+ /* Compare timing to max */
+ freq = ahb_freq / i;
+ if (freq >= max_freq)
+ continue;
+
+ /* Set the timing */
+ tv = chip->ctl_val[smc_read] | ASPEED_SMC_HCLK_DIV(i);
+ writel(tv, chip->ctl);
+ dev_dbg(chip->nor.dev, "Trying HCLK/%d...", i);
+ rc = aspeed_smc_calibrate_reads(chip, i, golden_buf, test_buf);
+ if (rc == 0)
+ best_div = i;
+ }
+ kfree(test_buf);
+
+ /* Nothing found ? */
+ if (best_div < 0)
+ dev_warn(chip->nor.dev, "No good frequency, using dumb slow");
+ else {
+ dev_dbg(chip->nor.dev, "Found good read timings at HCLK/%d",
+ best_div);
+ chip->ctl_val[smc_read] |= ASPEED_SMC_HCLK_DIV(best_div);
+ }
+
+ writel(chip->ctl_val[smc_read], chip->ctl);
+ return 0;
+}
+
static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
{
struct aspeed_smc_controller *controller = chip->controller;
const struct aspeed_smc_info *info = controller->info;
+ int io_mode;
u32 cmd;
if (chip->nor.addr_width == 4 && info->set_4b)
@@ -732,21 +982,24 @@ static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip)
* TODO: Adjust clocks if fast read is supported and interpret
* SPI-NOR flags to adjust controller settings.
*/
- if (chip->nor.read_proto == SNOR_PROTO_1_1_1) {
- if (chip->nor.read_dummy == 0)
- cmd = CONTROL_COMMAND_MODE_NORMAL;
- else
- cmd = CONTROL_COMMAND_MODE_FREAD;
- } else {
- dev_err(chip->nor.dev, "unsupported SPI read mode\n");
- return -EINVAL;
- }
+ io_mode = aspeed_smc_get_io_mode(chip);
+ if (io_mode < 0)
+ return io_mode;
- chip->ctl_val[smc_read] |= cmd |
+ if (chip->nor.read_dummy == 0)
+ cmd = CONTROL_COMMAND_MODE_NORMAL;
+ else
+ cmd = CONTROL_COMMAND_MODE_FREAD;
+
+ chip->ctl_val[smc_read] |= cmd | io_mode |
+ chip->nor.read_opcode << CONTROL_COMMAND_SHIFT |
CONTROL_IO_DUMMY_SET(chip->nor.read_dummy / 8);
- dev_dbg(controller->dev, "base control register: %08x\n",
+ dev_info(controller->dev, "read control register: %08x\n",
chip->ctl_val[smc_read]);
+
+ if (optimize_read && info->optimize_read)
+ info->optimize_read(chip, chip->clk_rate);
return 0;
}
@@ -756,6 +1009,7 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
const struct spi_nor_hwcaps hwcaps = {
.mask = SNOR_HWCAPS_READ |
SNOR_HWCAPS_READ_FAST |
+ SNOR_HWCAPS_READ_1_1_2 |
SNOR_HWCAPS_PP,
};
const struct aspeed_smc_info *info = controller->info;
@@ -799,6 +1053,13 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
break;
}
+ if (of_property_read_u32(child, "spi-max-frequency",
+ &chip->clk_rate)) {
+ chip->clk_rate = ASPEED_SPI_DEFAULT_FREQ;
+ }
+ dev_info(dev, "Using %d MHz SPI frequency\n",
+ chip->clk_rate / 1000000);
+
chip->controller = controller;
chip->ctl = controller->regs + info->ctl0 + cs * 4;
chip->cs = cs;
@@ -809,7 +1070,7 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller,
nor->dev = dev;
nor->priv = chip;
spi_nor_set_flash_node(nor, child);
- nor->read = aspeed_smc_read_user;
+ nor->read = aspeed_smc_read;
nor->write = aspeed_smc_write_user;
nor->read_reg = aspeed_smc_read_reg;
nor->write_reg = aspeed_smc_write_reg;
@@ -853,6 +1114,7 @@ static int aspeed_smc_probe(struct platform_device *pdev)
struct aspeed_smc_controller *controller;
const struct of_device_id *match;
const struct aspeed_smc_info *info;
+ struct clk *clk;
struct resource *res;
int ret;
@@ -884,6 +1146,12 @@ static int aspeed_smc_probe(struct platform_device *pdev)
controller->ahb_window_size = resource_size(res);
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+ controller->clk_frequency = clk_get_rate(clk);
+ devm_clk_put(&pdev->dev, clk);
+
ret = aspeed_smc_setup_flash(controller, np, res);
if (ret)
dev_err(dev, "Aspeed SMC probe failed %d\n", ret);
diff --git a/drivers/mtd/spi-nor/npcm-fiu.c b/drivers/mtd/spi-nor/npcm-fiu.c
new file mode 100644
index 000000000000..9b6e7747d678
--- /dev/null
+++ b/drivers/mtd/spi-nor/npcm-fiu.c
@@ -0,0 +1,930 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Nuvoton Technology corporation.
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/of_irq.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/spi-nor.h>
+#include <linux/vmalloc.h>
+#include <linux/regmap.h>
+#include <linux/log2.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of_device.h>
+
+#include <asm/sizes.h>
+#include <mtd/mtd-abi.h>
+
+/* Flash Interface Unit (FIU) Registers */
+#define NPCM_FIU_DRD_CFG 0x00
+#define NPCM_FIU_DWR_CFG 0x04
+#define NPCM_FIU_UMA_CFG 0x08
+#define NPCM_FIU_UMA_CTS 0x0C
+#define NPCM_FIU_UMA_CMD 0x10
+#define NPCM_FIU_UMA_ADDR 0x14
+#define NPCM_FIU_PRT_CFG 0x18
+#define NPCM_FIU_UMA_DW0 0x20
+#define NPCM_FIU_UMA_DW1 0x24
+#define NPCM_FIU_UMA_DW2 0x28
+#define NPCM_FIU_UMA_DW3 0x2C
+#define NPCM_FIU_UMA_DR0 0x30
+#define NPCM_FIU_UMA_DR1 0x34
+#define NPCM_FIU_UMA_DR2 0x38
+#define NPCM_FIU_UMA_DR3 0x3C
+#define NPCM_FIU_MAX_REG_LIMIT 0x80
+
+/* FIU Direct Read Configuration Register */
+#define NPCM_FIU_DRD_CFG_LCK BIT(31)
+#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24)
+#define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16)
+#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12)
+#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8)
+#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0)
+#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16
+#define NPCM_FIU_DRD_DBW_SHIFT 12
+#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8
+
+/* FIU Direct Write Configuration Register */
+#define NPCM_FIU_DWR_CFG_LCK BIT(31)
+#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24)
+#define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16)
+#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10)
+#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8)
+#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0)
+#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16
+#define NPCM_FIU_DWR_ABPCK_SHIFT 10
+#define NPCM_FIU_DWR_DBPCK_SHIFT 8
+
+/* FIU UMA Configuration Register */
+#define NPCM_FIU_UMA_CFG_LCK BIT(31)
+#define NPCM_FIU_UMA_CFG_CMMLCK BIT(30)
+#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24)
+#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21)
+#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16)
+#define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11)
+#define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10)
+#define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8)
+#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6)
+#define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4)
+#define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2)
+#define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0)
+#define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT 2
+#define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT 4
+#define NPCM_FIU_UMA_CFG_DBPCK_SHIFT 6
+#define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT 8
+#define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT 11
+#define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT 16
+#define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT 21
+#define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT 24
+
+/* FIU UMA Control and Status Register */
+#define NPCM_FIU_UMA_CTS_RDYIE BIT(25)
+#define NPCM_FIU_UMA_CTS_RDYST BIT(24)
+#define NPCM_FIU_UMA_CTS_SW_CS BIT(16)
+#define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8)
+#define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0)
+#define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT 8
+
+/* FIU UMA Command Register */
+#define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24)
+#define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16)
+#define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8)
+#define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0)
+
+/* FIU UMA Address Register */
+#define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0)
+#define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24)
+#define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16)
+#define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8)
+#define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0)
+
+/* FIU UMA Write Data Bytes 0-3 Register */
+#define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24)
+#define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16)
+#define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8)
+#define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0)
+
+/* FIU UMA Write Data Bytes 4-7 Register */
+#define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24)
+#define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16)
+#define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8)
+#define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0)
+
+/* FIU UMA Write Data Bytes 8-11 Register */
+#define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24)
+#define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16)
+#define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8)
+#define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0)
+
+/* FIU UMA Write Data Bytes 12-15 Register */
+#define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24)
+#define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16)
+#define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8)
+#define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0)
+
+/* FIU UMA Read Data Bytes 0-3 Register */
+#define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24)
+#define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16)
+#define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8)
+#define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0)
+
+/* FIU UMA Read Data Bytes 4-7 Register */
+#define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24)
+#define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16)
+#define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8)
+#define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0)
+
+/* FIU UMA Read Data Bytes 8-11 Register */
+#define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24)
+#define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16)
+#define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8)
+#define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0)
+
+/* FIU UMA Read Data Bytes 12-15 Register */
+#define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24)
+#define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16)
+#define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8)
+#define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0)
+
+/* FIU Read Mode */
+enum {
+ DRD_SINGLE_WIRE_MODE = 0,
+ DRD_DUAL_IO_MODE = 1,
+ DRD_QUAD_IO_MODE = 2,
+ DRD_SPI_X_MODE = 3,
+};
+
+enum {
+ DWR_ABPCK_BIT_PER_CLK = 0,
+ DWR_ABPCK_2_BIT_PER_CLK = 1,
+ DWR_ABPCK_4_BIT_PER_CLK = 2,
+};
+
+enum {
+ DWR_DBPCK_BIT_PER_CLK = 0,
+ DWR_DBPCK_2_BIT_PER_CLK = 1,
+ DWR_DBPCK_4_BIT_PER_CLK = 2,
+};
+
+#define NPCM_FIU_DRD_16_BYTE_BURST 0x3000000
+#define NPCM_FIU_DWR_16_BYTE_BURST 0x3000000
+
+#define MAP_SIZE_128MB 0x8000000
+#define MAP_SIZE_16MB 0x1000000
+#define MAP_SIZE_8MB 0x800000
+
+#define NUM_BITS_IN_BYTE 8
+#define FIU_DRD_MAX_DUMMY_NUMBER 3
+#define NPCM_MAX_CHIP_NUM 4
+#define CHUNK_SIZE 16
+#define UMA_MICRO_SEC_TIMEOUT 150
+
+enum {
+ FIU0 = 0,
+ FIU3,
+ FIUX,
+};
+
+struct npcm_fiu_info {
+ char *name;
+ u32 fiu_id;
+ u32 max_map_size;
+ u32 max_cs;
+};
+
+struct fiu_data {
+ const struct npcm_fiu_info *npcm_fiu_data_info;
+ int fiu_max;
+};
+
+static const struct npcm_fiu_info npxm7xx_fiu_info[] = {
+ {.name = "FIU0", .fiu_id = FIU0,
+ .max_map_size = MAP_SIZE_128MB, .max_cs = 2},
+ {.name = "FIU3", .fiu_id = FIU3,
+ .max_map_size = MAP_SIZE_128MB, .max_cs = 4},
+ {.name = "FIUX", .fiu_id = FIUX,
+ .max_map_size = MAP_SIZE_16MB, .max_cs = 2} };
+
+static const struct fiu_data npxm7xx_fiu_data = {
+ .npcm_fiu_data_info = npxm7xx_fiu_info,
+ .fiu_max = 3,
+};
+
+struct npcm_fiu_bus;
+
+struct npcm_chip {
+ void __iomem *flash_region_mapped_ptr;
+ enum spi_nor_protocol direct_rd_proto;
+ struct npcm_fiu_bus *host;
+ struct spi_nor nor;
+ bool direct_read;
+ u32 read_proto;
+ u32 chipselect;
+ u32 clkrate;
+};
+
+struct npcm_fiu_bus {
+ struct npcm_chip *chip[NPCM_MAX_CHIP_NUM];
+ enum spi_nor_protocol direct_rd_proto;
+ const struct npcm_fiu_info *info;
+ struct resource *res_mem;
+ resource_size_t iosize;
+ struct regmap *regmap;
+ void __iomem *regbase;
+ u32 direct_read_proto;
+ struct device *dev;
+ struct mutex lock; /* controller access mutex */
+ struct clk *clk;
+ bool spix_mode;
+ int id;
+};
+
+static const struct regmap_config npcm_mtd_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = NPCM_FIU_MAX_REG_LIMIT,
+};
+
+static int npcm_fiu_direct_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct spi_nor *nor = mtd->priv;
+ struct npcm_chip *chip = nor->priv;
+
+ memcpy_fromio(buf, chip->flash_region_mapped_ptr + from, len);
+
+ *retlen = len;
+ return 0;
+}
+
+static int npcm_fiu_direct_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ struct spi_nor *nor = mtd->priv;
+ struct npcm_chip *chip = nor->priv;
+
+ memcpy_toio(chip->flash_region_mapped_ptr + to, buf, len);
+
+ *retlen = len;
+ return 0;
+}
+
+static int npcm_fiu_uma_read(struct spi_nor *nor, u8 transaction_code,
+ u32 address, bool is_address_size, u8 *data,
+ u32 data_size)
+{
+ struct npcm_chip *chip = nor->priv;
+ struct npcm_fiu_bus *host = chip->host;
+ u32 uma_cfg = BIT(10);
+ u32 dummy_bytes;
+ u32 data_reg[4];
+ int ret;
+ u32 val;
+ u32 i;
+
+ regmap_update_bits(host->regmap, NPCM_FIU_UMA_CTS,
+ NPCM_FIU_UMA_CTS_DEV_NUM,
+ (chip->chipselect <<
+ NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
+ regmap_update_bits(host->regmap, NPCM_FIU_UMA_CMD,
+ NPCM_FIU_UMA_CMD_CMD, transaction_code);
+ regmap_write(host->regmap, NPCM_FIU_UMA_ADDR, address);
+
+ if (is_address_size) {
+ uma_cfg |=
+ ilog2(spi_nor_get_protocol_inst_nbits(nor->read_proto));
+ uma_cfg |=
+ ilog2(spi_nor_get_protocol_addr_nbits(nor->read_proto))
+ << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
+ uma_cfg |=
+ ilog2(spi_nor_get_protocol_addr_nbits(nor->read_proto))
+ << NPCM_FIU_UMA_CFG_DBPCK_SHIFT;
+ uma_cfg |=
+ ilog2(spi_nor_get_protocol_data_nbits(nor->read_proto))
+ << NPCM_FIU_UMA_CFG_RDBPCK_SHIFT;
+ dummy_bytes =
+ (nor->read_dummy *
+ spi_nor_get_protocol_addr_nbits(nor->read_proto)) /
+ NUM_BITS_IN_BYTE;
+ uma_cfg |= dummy_bytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT;
+ uma_cfg |= (nor->addr_width << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT);
+ }
+
+ uma_cfg |= data_size << NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT;
+ regmap_write(host->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
+
+ regmap_write_bits(host->regmap, NPCM_FIU_UMA_CTS,
+ NPCM_FIU_UMA_CTS_EXEC_DONE,
+ NPCM_FIU_UMA_CTS_EXEC_DONE);
+
+ ret = regmap_read_poll_timeout(host->regmap, NPCM_FIU_UMA_CTS, val,
+ (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,
+ UMA_MICRO_SEC_TIMEOUT);
+ if (ret)
+ return ret;
+
+ if (data_size) {
+ for (i = 0; i <= data_size / 4; i++)
+ regmap_read(host->regmap, NPCM_FIU_UMA_DR0 + (i * 4),
+ &data_reg[i]);
+ memcpy(data, data_reg, data_size);
+ }
+
+ return 0;
+}
+
+static int npcm_fiu_uma_write(struct spi_nor *nor, u8 transaction_code,
+ u32 address, bool is_address_size, u8 *data,
+ u32 data_size)
+{
+ struct npcm_chip *chip = nor->priv;
+ struct npcm_fiu_bus *host = chip->host;
+ u32 uma_cfg = BIT(10);
+ u32 data_reg[4] = {0};
+ u32 val;
+ u32 i;
+
+ regmap_update_bits(host->regmap, NPCM_FIU_UMA_CTS,
+ NPCM_FIU_UMA_CTS_DEV_NUM,
+ (chip->chipselect <<
+ NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
+
+ regmap_update_bits(host->regmap, NPCM_FIU_UMA_CMD,
+ NPCM_FIU_UMA_CMD_CMD, transaction_code);
+ regmap_write(host->regmap, NPCM_FIU_UMA_ADDR, address);
+
+ if (data_size) {
+ memcpy(data_reg, data, data_size);
+ for (i = 0; i <= data_size / 4; i++)
+ regmap_write(host->regmap, NPCM_FIU_UMA_DW0 + (i * 4),
+ data_reg[i]);
+ }
+
+ if (is_address_size) {
+ uma_cfg |=
+ ilog2(spi_nor_get_protocol_inst_nbits
+ (nor->write_proto));
+ uma_cfg |=
+ ilog2(spi_nor_get_protocol_addr_nbits(nor->write_proto))
+ << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
+ uma_cfg |=
+ ilog2(spi_nor_get_protocol_data_nbits(nor->write_proto))
+ << NPCM_FIU_UMA_CFG_WDBPCK_SHIFT;
+ uma_cfg |= (nor->addr_width << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT);
+ }
+
+ uma_cfg |= (data_size << NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT);
+ regmap_write(host->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
+
+ regmap_write_bits(host->regmap, NPCM_FIU_UMA_CTS,
+ NPCM_FIU_UMA_CTS_EXEC_DONE,
+ NPCM_FIU_UMA_CTS_EXEC_DONE);
+
+ return regmap_read_poll_timeout(host->regmap, NPCM_FIU_UMA_CTS, val,
+ (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,
+ UMA_MICRO_SEC_TIMEOUT);
+}
+
+static int npcm_fiu_manualwrite(struct spi_nor *nor, u8 transaction_code,
+ u32 address, u8 *data, u32 data_size)
+{
+ u32 num_data_chunks;
+ u32 remain_data;
+ u32 idx = 0;
+ int ret;
+
+ struct npcm_chip *chip = nor->priv;
+ struct npcm_fiu_bus *host = chip->host;
+
+ num_data_chunks = data_size / CHUNK_SIZE;
+ remain_data = data_size % CHUNK_SIZE;
+
+ regmap_update_bits(host->regmap, NPCM_FIU_UMA_CTS,
+ NPCM_FIU_UMA_CTS_DEV_NUM,
+ (chip->chipselect <<
+ NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
+ regmap_update_bits(host->regmap, NPCM_FIU_UMA_CTS,
+ NPCM_FIU_UMA_CTS_SW_CS, 0);
+
+ ret = npcm_fiu_uma_write(nor, transaction_code, address, true,
+ NULL, 0);
+ if (ret)
+ return ret;
+
+ /* Starting the data writing loop in multiples of 8 */
+ for (idx = 0; idx < num_data_chunks; ++idx) {
+ ret = npcm_fiu_uma_write(nor, data[0], (u32)NULL, false,
+ &data[1], CHUNK_SIZE - 1);
+ if (ret)
+ return ret;
+
+ data += CHUNK_SIZE;
+ }
+
+ /* Handling chunk remains */
+ if (remain_data > 0) {
+ ret = npcm_fiu_uma_write(nor, data[0], (u32)NULL, false,
+ &data[1], remain_data - 1);
+ if (ret)
+ return ret;
+ }
+
+ regmap_update_bits(host->regmap, NPCM_FIU_UMA_CTS,
+ NPCM_FIU_UMA_CTS_SW_CS, NPCM_FIU_UMA_CTS_SW_CS);
+
+ return 0;
+}
+
+static ssize_t npcm_fiu_write(struct spi_nor *nor, loff_t to,
+ size_t len, const u_char *write_buf)
+{
+ u32 local_addr = (u32)to;
+ struct mtd_info *mtd;
+ u32 actual_size = 0;
+ u32 cnt = (u32)len;
+ int ret;
+
+ mtd = &nor->mtd;
+
+ if (cnt != 0) {
+ while (cnt) {
+ actual_size = ((((local_addr) / nor->page_size) + 1)
+ * nor->page_size) - (local_addr);
+ if (actual_size > cnt)
+ actual_size = cnt;
+
+ ret = npcm_fiu_manualwrite(nor, nor->program_opcode,
+ local_addr,
+ (u_char *)write_buf,
+ actual_size);
+ if (ret)
+ return ret;
+
+ write_buf += actual_size;
+ local_addr += actual_size;
+ cnt -= actual_size;
+ }
+ }
+
+ return (len - cnt);
+}
+
+static void npcm_fiu_set_drd(struct spi_nor *nor, struct npcm_fiu_bus *host)
+{
+ regmap_update_bits(host->regmap, NPCM_FIU_DRD_CFG,
+ NPCM_FIU_DRD_CFG_ACCTYPE,
+ ilog2(spi_nor_get_protocol_addr_nbits
+ (nor->read_proto)) <<
+ NPCM_FIU_DRD_ACCTYPE_SHIFT);
+ regmap_update_bits(host->regmap, NPCM_FIU_DRD_CFG,
+ NPCM_FIU_DRD_CFG_DBW,
+ ((nor->read_dummy *
+ spi_nor_get_protocol_addr_nbits(nor->read_proto))
+ / NUM_BITS_IN_BYTE) << NPCM_FIU_DRD_DBW_SHIFT);
+ regmap_update_bits(host->regmap, NPCM_FIU_DRD_CFG,
+ NPCM_FIU_DRD_CFG_RDCMD, nor->read_opcode);
+ regmap_update_bits(host->regmap, NPCM_FIU_DRD_CFG,
+ NPCM_FIU_DRD_CFG_ADDSIZ,
+ (nor->addr_width - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT);
+}
+
+static ssize_t npcm_fiu_read(struct spi_nor *nor, loff_t from, size_t len,
+ u_char *read_buf)
+{
+ struct npcm_chip *chip = nor->priv;
+ struct npcm_fiu_bus *host = chip->host;
+ int i, readlen, currlen;
+ struct mtd_info *mtd;
+ size_t retlen = 0;
+ u8 *buf_ptr;
+ u32 addr;
+ int ret;
+
+ mtd = &nor->mtd;
+
+ if (chip->direct_read) {
+ regmap_read(host->regmap, NPCM_FIU_DRD_CFG, &addr);
+ if (host->direct_rd_proto != chip->direct_rd_proto) {
+ npcm_fiu_set_drd(nor, host);
+ host->direct_rd_proto = chip->direct_rd_proto;
+ }
+ npcm_fiu_direct_read(mtd, from, len, &retlen, read_buf);
+ } else {
+ i = 0;
+ currlen = (int)len;
+
+ do {
+ addr = ((u32)from + i);
+ if (currlen < 4)
+ readlen = currlen;
+ else
+ readlen = 4;
+
+ buf_ptr = read_buf + i;
+ ret = npcm_fiu_uma_read(nor, nor->read_opcode, addr,
+ true, buf_ptr, readlen);
+ if (ret)
+ return ret;
+
+ i += readlen;
+ currlen -= 4;
+ } while (currlen > 0);
+
+ retlen = i;
+ }
+
+ return retlen;
+}
+
+static int npcm_fiu_erase(struct spi_nor *nor, loff_t offs)
+{
+ return npcm_fiu_uma_write(nor, nor->erase_opcode, (u32)offs, true,
+ NULL, 0);
+}
+
+static int npcm_fiu_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ int len)
+{
+ return npcm_fiu_uma_read(nor, opcode, 0, false, buf, len);
+}
+
+static int npcm_fiu_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
+ int len)
+{
+ return npcm_fiu_uma_write(nor, opcode, 0, false, buf, len);
+}
+
+static int npcm_fiu_nor_prep(struct spi_nor *nor, enum spi_nor_ops ops)
+{
+ struct npcm_chip *chip = nor->priv;
+ struct npcm_fiu_bus *host = chip->host;
+
+ mutex_lock(&host->lock);
+
+ return 0;
+}
+
+static void npcm_fiu_nor_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
+{
+ struct npcm_chip *chip = nor->priv;
+ struct npcm_fiu_bus *host = chip->host;
+
+ mutex_unlock(&host->lock);
+}
+
+/* Expansion bus registers as mtd_ram device */
+static int npcm_mtd_ram_register(struct device_node *np,
+ struct npcm_fiu_bus *host)
+{
+ struct device *dev = host->dev;
+ struct npcm_chip *chip;
+ struct mtd_info *mtd;
+ struct spi_nor *nor;
+ u32 chipselect;
+ u32 rx_dummy = 0;
+ int ret;
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ ret = of_property_read_u32(np, "reg", &chipselect);
+ if (ret) {
+ dev_err(dev, "There's no reg property for %s\n",
+ dev->of_node->full_name);
+ return ret;
+ }
+
+ of_property_read_u32(np, "npcm,fiu-spix-rx-dummy-num", &rx_dummy);
+ if (rx_dummy > FIU_DRD_MAX_DUMMY_NUMBER) {
+ dev_warn(dev, "npcm,fiu-spix-rx-dummy-num %d not supported\n",
+ rx_dummy);
+ rx_dummy = 0;
+ }
+
+ chip->host = host;
+ chip->chipselect = chipselect;
+ nor = &chip->nor;
+ nor->dev = dev;
+ nor->priv = chip;
+ mtd = &nor->mtd;
+
+ chip->flash_region_mapped_ptr =
+ devm_ioremap(dev, (host->res_mem->start +
+ (host->info->max_map_size *
+ chip->chipselect)), MAP_SIZE_8MB);
+ if (!chip->flash_region_mapped_ptr) {
+ dev_err(dev, "Error mapping memory region!\n");
+ return -ENOMEM;
+ }
+
+ /* Populate mtd_info data structure */
+ *mtd = (struct mtd_info) {
+ .dev = { .parent = dev },
+ .name = "exp-bus",
+ .type = MTD_RAM,
+ .priv = nor,
+ .size = MAP_SIZE_8MB,
+ .writesize = 1,
+ .writebufsize = 1,
+ .flags = MTD_CAP_RAM,
+ ._read = npcm_fiu_direct_read,
+ ._write = npcm_fiu_direct_write,
+ };
+
+ /* set read and write direct to configuration to SPI-X mode */
+ regmap_write(host->regmap, NPCM_FIU_DRD_CFG,
+ NPCM_FIU_DRD_16_BYTE_BURST);
+ regmap_update_bits(host->regmap, NPCM_FIU_DRD_CFG,
+ NPCM_FIU_DRD_CFG_ACCTYPE,
+ DRD_SPI_X_MODE << NPCM_FIU_DRD_ACCTYPE_SHIFT);
+ regmap_update_bits(host->regmap, NPCM_FIU_DRD_CFG,
+ NPCM_FIU_DRD_CFG_DBW,
+ rx_dummy << NPCM_FIU_DRD_DBW_SHIFT);
+ regmap_write(host->regmap, NPCM_FIU_DWR_CFG,
+ NPCM_FIU_DWR_16_BYTE_BURST);
+ regmap_update_bits(host->regmap, NPCM_FIU_DWR_CFG,
+ NPCM_FIU_DWR_CFG_ABPCK,
+ DWR_ABPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_ABPCK_SHIFT);
+ regmap_update_bits(host->regmap, NPCM_FIU_DWR_CFG,
+ NPCM_FIU_DWR_CFG_DBPCK,
+ DWR_DBPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_DBPCK_SHIFT);
+
+ ret = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0);
+ if (ret)
+ return ret;
+
+ host->chip[chip->chipselect] = chip;
+
+ return 0;
+}
+
+static void npcm_fiu_enable_direct_rd(struct spi_nor *nor,
+ struct npcm_fiu_bus *host,
+ struct npcm_chip *chip)
+{
+ struct device *dev = host->dev;
+ u32 flashsize;
+
+ if (!host->res_mem) {
+ dev_warn(dev, "Reserved memory not defined, direct read disabled\n");
+ return;
+ }
+
+ /* direct read supports only I/O read mode */
+ if (nor->read_proto != SNOR_PROTO_1_1_1 &&
+ nor->read_proto != SNOR_PROTO_1_2_2 &&
+ nor->read_proto != SNOR_PROTO_1_4_4) {
+ dev_warn(dev, "Only Read I/O commands supported, direct read disabled\n");
+ return;
+ }
+
+ flashsize = (u32)(nor->mtd.size >> 10) * 1024;
+ if (flashsize == 0 || flashsize > host->info->max_map_size) {
+ dev_warn(dev, "Flash size ecxeed(0x%x) map size(0x%x), direct read disabled\n"
+ , flashsize, host->info->max_map_size);
+ return;
+ }
+
+ chip->flash_region_mapped_ptr =
+ devm_ioremap(dev, (host->res_mem->start +
+ (host->info->max_map_size *
+ chip->chipselect)), flashsize);
+ if (!chip->flash_region_mapped_ptr) {
+ dev_warn(dev, "Error mapping memory region, direct read disabled\n");
+ return;
+ }
+
+ npcm_fiu_set_drd(nor, host);
+
+ host->direct_rd_proto = nor->read_proto;
+ chip->direct_rd_proto = nor->read_proto;
+ chip->direct_read = true;
+}
+
+/* Get spi flash device information and register it as a mtd device. */
+static int npcm_fiu_nor_register(struct device_node *np,
+ struct npcm_fiu_bus *host)
+{
+ struct device *dev = host->dev;
+ struct npcm_chip *chip;
+ struct mtd_info *mtd;
+ struct spi_nor *nor;
+ u32 chipselect;
+ int ret;
+ u32 val;
+ struct spi_nor_hwcaps hwcaps = {
+ .mask = SNOR_HWCAPS_READ |
+ SNOR_HWCAPS_READ_FAST |
+ SNOR_HWCAPS_PP |
+ SNOR_HWCAPS_PP_1_1_4 |
+ SNOR_HWCAPS_PP_1_4_4 |
+ SNOR_HWCAPS_PP_4_4_4,
+ };
+
+ /* This driver mode supports only NOR flash devices. */
+ if (!of_device_is_compatible(np, "jedec,spi-nor")) {
+ dev_err(dev, "The device is no compatible to jedec,spi-nor\n");
+ return -ENOMEM;
+ }
+
+ ret = of_property_read_u32(np, "reg", &chipselect);
+ if (ret) {
+ dev_err(dev, "There's no reg property for %s\n", np->full_name);
+ return ret;
+ }
+
+ if (chipselect >= host->info->max_cs) {
+ dev_err(dev, "Flash device number exceeds the maximum chipselect number\n");
+ return -ENOMEM;
+ }
+
+ if (!of_property_read_u32(np, "spi-rx-bus-width", &val)) {
+ switch (val) {
+ case 1:
+ break;
+ case 2:
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2
+ | SNOR_HWCAPS_READ_1_2_2
+ | SNOR_HWCAPS_READ_2_2_2;
+ break;
+ case 4:
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4
+ | SNOR_HWCAPS_READ_1_4_4
+ | SNOR_HWCAPS_READ_4_4_4;
+ break;
+ default:
+ dev_warn(dev, "spi-rx-bus-width %d not supported\n", val);
+ break;
+ }
+ }
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->host = host;
+ chip->chipselect = chipselect;
+
+ nor = &chip->nor;
+ mtd = &nor->mtd;
+
+ nor->dev = dev;
+ nor->priv = chip;
+
+ spi_nor_set_flash_node(nor, np);
+
+ nor->prepare = npcm_fiu_nor_prep;
+ nor->unprepare = npcm_fiu_nor_unprep;
+ nor->read_reg = npcm_fiu_read_reg;
+ nor->write_reg = npcm_fiu_write_reg;
+ nor->read = npcm_fiu_read;
+ nor->write = npcm_fiu_write;
+ nor->erase = npcm_fiu_erase;
+
+ ret = spi_nor_scan(nor, NULL, &hwcaps);
+ if (ret)
+ return ret;
+
+ npcm_fiu_enable_direct_rd(nor, host, chip);
+ ret = mtd_device_register(mtd, NULL, 0);
+ if (ret) {
+ dev_err(dev, "MTD NOR device register failed\n");
+ return ret;
+ }
+
+ host->chip[chip->chipselect] = chip;
+ return 0;
+}
+
+static void npcm_fiu_unregister_all(struct npcm_fiu_bus *host)
+{
+ struct npcm_chip *chip;
+ int n;
+
+ for (n = 0; n < host->info->max_cs; n++) {
+ chip = host->chip[n];
+ if (chip)
+ mtd_device_unregister(&chip->nor.mtd);
+ }
+}
+
+static void npcm_fiu_register_all(struct npcm_fiu_bus *host)
+{
+ struct device *dev = host->dev;
+ struct device_node *np;
+ int ret;
+
+ for_each_available_child_of_node(dev->of_node, np) {
+ if (host->spix_mode)
+ ret = npcm_mtd_ram_register(np, host);
+ else
+ ret = npcm_fiu_nor_register(np, host);
+ if (ret)
+ dev_warn(dev, "npcm fiu %s registration failed\n", np->full_name);
+ }
+}
+
+static const struct of_device_id npcm_fiu_dt_ids[] = {
+ { .compatible = "nuvoton,npcm750-fiu", .data = &npxm7xx_fiu_data },
+ { /* sentinel */ }
+};
+
+static int npcm_fiu_probe(struct platform_device *pdev)
+{
+ const struct fiu_data *fiu_data_match;
+ const struct of_device_id *match;
+ struct device *dev = &pdev->dev;
+ struct npcm_fiu_bus *host;
+ struct resource *res;
+
+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
+ if (!host)
+ return -ENOMEM;
+
+ match = of_match_device(npcm_fiu_dt_ids, dev);
+ if (!match || !match->data) {
+ dev_err(dev, "No compatible OF match\n");
+ return -ENODEV;
+ }
+
+ fiu_data_match = match->data;
+
+ host->id = of_alias_get_id(dev->of_node, "fiu");
+ if (host->id < 0 || host->id >= fiu_data_match->fiu_max) {
+ dev_err(dev, "Invalid platform device id: %d\n", host->id);
+ return -EINVAL;
+ }
+
+ host->info = &fiu_data_match->npcm_fiu_data_info[host->id];
+
+ platform_set_drvdata(pdev, host);
+ host->dev = dev;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control");
+ host->regbase = devm_ioremap_resource(dev, res);
+ if (IS_ERR(host->regbase))
+ return PTR_ERR(host->regbase);
+
+ host->regmap = devm_regmap_init_mmio(dev, host->regbase,
+ &npcm_mtd_regmap_config);
+ if (IS_ERR(host->regmap)) {
+ dev_err(dev, "Failed to create regmap\n");
+ return PTR_ERR(host->regmap);
+ }
+
+ host->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "memory");
+ host->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(host->clk))
+ return PTR_ERR(host->clk);
+
+ host->spix_mode = of_property_read_bool(dev->of_node, "spix-mode");
+
+ mutex_init(&host->lock);
+ clk_prepare_enable(host->clk);
+
+ npcm_fiu_register_all(host);
+
+ dev_info(dev, "NPCM %s probe succeed\n", host->info->name);
+
+ return 0;
+}
+
+static int npcm_fiu_remove(struct platform_device *pdev)
+{
+ struct npcm_fiu_bus *host = platform_get_drvdata(pdev);
+
+ npcm_fiu_unregister_all(host);
+ mutex_destroy(&host->lock);
+ clk_disable_unprepare(host->clk);
+ return 0;
+}
+
+MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids);
+
+static struct platform_driver npcm_fiu_driver = {
+ .driver = {
+ .name = "NPCM-FIU",
+ .bus = &platform_bus_type,
+ .of_match_table = npcm_fiu_dt_ids,
+ },
+ .probe = npcm_fiu_probe,
+ .remove = npcm_fiu_remove,
+};
+module_platform_driver(npcm_fiu_driver);
+
+MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller Driver");
+MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index f028277fb1ce..c5ef85e74667 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1091,7 +1091,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
- { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { "mx66l51235f", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-14 20:11:06 +0300