diff options
Diffstat (limited to 'drivers/media/i2c/smiapp-pll.h')
| -rw-r--r-- | drivers/media/i2c/smiapp-pll.h | 61 |
1 files changed, 36 insertions, 25 deletions
diff --git a/drivers/media/i2c/smiapp-pll.h b/drivers/media/i2c/smiapp-pll.h index cb2d2db5d02d..a4a649834a18 100644 --- a/drivers/media/i2c/smiapp-pll.h +++ b/drivers/media/i2c/smiapp-pll.h @@ -4,7 +4,7 @@ * Generic driver for SMIA/SMIA++ compliant camera modules * * Copyright (C) 2012 Nokia Corporation - * Contact: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com> + * Contact: Sakari Ailus <sakari.ailus@iki.fi> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -27,16 +27,34 @@ #include <linux/device.h> +/* CSI-2 or CCP-2 */ +#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00 +#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01 + +/* op pix clock is for all lanes in total normally */ +#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) +#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1) + struct smiapp_pll { - uint8_t lanes; + /* input values */ + uint8_t bus_type; + union { + struct { + uint8_t lanes; + } csi2; + struct { + uint8_t bus_width; + } parallel; + }; + uint8_t flags; uint8_t binning_horizontal; uint8_t binning_vertical; uint8_t scale_m; uint8_t scale_n; uint8_t bits_per_pixel; - uint16_t flags; uint32_t link_freq; + /* output values */ uint16_t pre_pll_clk_div; uint16_t pll_multiplier; uint16_t op_sys_clk_div; @@ -55,6 +73,17 @@ struct smiapp_pll { uint32_t pixel_rate_csi; }; +struct smiapp_pll_branch_limits { + uint16_t min_sys_clk_div; + uint16_t max_sys_clk_div; + uint32_t min_sys_clk_freq_hz; + uint32_t max_sys_clk_freq_hz; + uint16_t min_pix_clk_div; + uint16_t max_pix_clk_div; + uint32_t min_pix_clk_freq_hz; + uint32_t max_pix_clk_freq_hz; +}; + struct smiapp_pll_limits { /* Strict PLL limits */ uint32_t min_ext_clk_freq_hz; @@ -68,36 +97,18 @@ struct smiapp_pll_limits { uint32_t min_pll_op_freq_hz; uint32_t max_pll_op_freq_hz; - uint16_t min_vt_sys_clk_div; - uint16_t max_vt_sys_clk_div; - uint32_t min_vt_sys_clk_freq_hz; - uint32_t max_vt_sys_clk_freq_hz; - uint16_t min_vt_pix_clk_div; - uint16_t max_vt_pix_clk_div; - uint32_t min_vt_pix_clk_freq_hz; - uint32_t max_vt_pix_clk_freq_hz; - - uint16_t min_op_sys_clk_div; - uint16_t max_op_sys_clk_div; - uint32_t min_op_sys_clk_freq_hz; - uint32_t max_op_sys_clk_freq_hz; - uint16_t min_op_pix_clk_div; - uint16_t max_op_pix_clk_div; - uint32_t min_op_pix_clk_freq_hz; - uint32_t max_op_pix_clk_freq_hz; + struct smiapp_pll_branch_limits vt; + struct smiapp_pll_branch_limits op; /* Other relevant limits */ uint32_t min_line_length_pck_bin; uint32_t min_line_length_pck; }; -/* op pix clock is for all lanes in total normally */ -#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) -#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1) - struct device; -int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits, +int smiapp_pll_calculate(struct device *dev, + const struct smiapp_pll_limits *limits, struct smiapp_pll *pll); #endif /* SMIAPP_PLL_H */ |