diff options
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/Kconfig | 23 | ||||
| -rw-r--r-- | drivers/i2c/Makefile | 1 | ||||
| -rw-r--r-- | drivers/i2c/busses/i2c-aspeed.c | 754 | ||||
| -rw-r--r-- | drivers/i2c/i2c-core-base.c | 88 | ||||
| -rw-r--r-- | drivers/i2c/i2c-core-smbus.c | 22 | ||||
| -rw-r--r-- | drivers/i2c/i2c-mux.c | 112 | ||||
| -rw-r--r-- | drivers/i2c/i2c-slave-mqueue.c | 243 |
7 files changed, 1174 insertions, 69 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 438905e2a1d0..339464db1df6 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -133,6 +133,29 @@ config I2C_SLAVE_TESTUNIT multi-master, SMBus Host Notify, etc. Please read Documentation/i2c/slave-testunit-backend.rst for further details. +config I2C_SLAVE_MQUEUE_MESSAGE_SIZE + int "The message size of I2C mqueue slave" + default 120 + +config I2C_SLAVE_MQUEUE_QUEUE_SIZE + int "The queue size of I2C mqueue slave" + default 32 + help + This number MUST be power of 2. + +config I2C_SLAVE_MQUEUE + tristate "I2C mqueue (message queue) slave driver" + help + Some protocols over I2C are designed for bi-directional transferring + messages by using I2C Master Write protocol. This driver is used to + receive and queue messages from the remote I2C device. + + Userspace can get the messages by reading sysfs file that this driver + exposes. + + This support is also available as a module. If so, the module will be + called i2c-slave-mqueue. + endif config I2C_DEBUG_CORE diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c1d493dc9bac..0442e5cf8587 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -17,5 +17,6 @@ obj-y += algos/ busses/ muxes/ obj-$(CONFIG_I2C_STUB) += i2c-stub.o obj-$(CONFIG_I2C_SLAVE_EEPROM) += i2c-slave-eeprom.o obj-$(CONFIG_I2C_SLAVE_TESTUNIT) += i2c-slave-testunit.o +obj-$(CONFIG_I2C_SLAVE_MQUEUE) += i2c-slave-mqueue.o ccflags-$(CONFIG_I2C_DEBUG_CORE) := -DDEBUG diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c index 724bf30600d6..70dacc1bf4e7 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -7,8 +7,11 @@ * Copyright 2017 Google, Inc. */ +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/completion.h> +#include <linux/dma-mapping.h> +#include <linux/dmapool.h> #include <linux/err.h> #include <linux/errno.h> #include <linux/i2c.h> @@ -19,15 +22,24 @@ #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/kernel.h> +#include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/regmap.h> #include <linux/reset.h> #include <linux/slab.h> -/* I2C Register */ +/* I2C Global Registers */ +/* 0x00 : I2CG Interrupt Status Register */ +/* 0x08 : I2CG Interrupt Target Assignment */ +/* 0x0c : I2CG Global Control Register (AST2500) */ +#define ASPEED_I2CG_GLOBAL_CTRL_REG 0x0c +#define ASPEED_I2CG_SRAM_BUFFER_EN BIT(0) + +/* I2C Bus Registers */ #define ASPEED_I2C_FUN_CTRL_REG 0x00 #define ASPEED_I2C_AC_TIMING_REG1 0x04 #define ASPEED_I2C_AC_TIMING_REG2 0x08 @@ -35,18 +47,20 @@ #define ASPEED_I2C_INTR_STS_REG 0x10 #define ASPEED_I2C_CMD_REG 0x14 #define ASPEED_I2C_DEV_ADDR_REG 0x18 +#define ASPEED_I2C_BUF_CTRL_REG 0x1c #define ASPEED_I2C_BYTE_BUF_REG 0x20 - -/* Global Register Definition */ -/* 0x00 : I2C Interrupt Status Register */ -/* 0x08 : I2C Interrupt Target Assignment */ +#define ASPEED_I2C_DMA_ADDR_REG 0x24 +#define ASPEED_I2C_DMA_LEN_REG 0x28 /* Device Register Definition */ /* 0x00 : I2CD Function Control Register */ +#define ASPEED_I2CD_BUFFER_PAGE_SEL_MASK GENMASK(22, 20) +#define ASPEED_I2CD_BUS_AUTO_RECOVERY_EN BIT(17) #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15) #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8) #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7) #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6) +#define ASPEED_I2CD_GCALL_EN BIT(2) #define ASPEED_I2CD_SLAVE_EN BIT(1) #define ASPEED_I2CD_MASTER_EN BIT(0) @@ -58,10 +72,14 @@ #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16) #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12) +#define ASPEED_I2CD_TIME_TIMEOUT_BASE_DIVISOR_SHIFT 8 +#define ASPEED_I2CD_TIME_TIMEOUT_BASE_DIVISOR_MASK GENMASK(9, 8) #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0) #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0) + /* 0x08 : I2CD Clock and AC Timing Control Register #2 */ -#define ASPEED_NO_TIMEOUT_CTRL 0 +#define ASPEED_I2CD_TIMEOUT_CYCLES_SHIFT 0 +#define ASPEED_I2CD_TIMEOUT_CYCLES_MASK GENMASK(4, 0) /* 0x0c : I2CD Interrupt Control Register & * 0x10 : I2CD Interrupt Status Register @@ -70,8 +88,15 @@ * status bits. */ #define ASPEED_I2CD_INTR_RECV_MASK 0xf000ffff +#if defined(CONFIG_MACH_ASPEED_G6) +#define ASPEED_I2CD_INTR_SLAVE_ADDR_RECEIVED_PENDING BIT(29) +#else +#define ASPEED_I2CD_INTR_SLAVE_ADDR_RECEIVED_PENDING BIT(30) +#endif +#define ASPEED_I2CD_INTR_SLAVE_INACTIVE_TIMEOUT BIT(15) #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14) #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13) +#define ASPEED_I2CD_INTR_GCALL_ADDR BIT(8) #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7) #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6) #define ASPEED_I2CD_INTR_ABNORMAL BIT(5) @@ -85,8 +110,11 @@ ASPEED_I2CD_INTR_SCL_TIMEOUT | \ ASPEED_I2CD_INTR_ABNORMAL | \ ASPEED_I2CD_INTR_ARBIT_LOSS) +#define ASPEED_I2CD_INTR_SLAVE_ERRORS \ + ASPEED_I2CD_INTR_SLAVE_INACTIVE_TIMEOUT #define ASPEED_I2CD_INTR_ALL \ - (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \ + (ASPEED_I2CD_INTR_SLAVE_INACTIVE_TIMEOUT | \ + ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \ ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \ ASPEED_I2CD_INTR_SCL_TIMEOUT | \ ASPEED_I2CD_INTR_ABNORMAL | \ @@ -95,6 +123,11 @@ ASPEED_I2CD_INTR_RX_DONE | \ ASPEED_I2CD_INTR_TX_NAK | \ ASPEED_I2CD_INTR_TX_ACK) +#define ASPEED_I2CD_INTR_STATUS_MASK \ + (ASPEED_I2CD_INTR_SLAVE_ADDR_RECEIVED_PENDING | \ + ASPEED_I2CD_INTR_GCALL_ADDR | \ + ASPEED_I2CD_INTR_SLAVE_MATCH | \ + ASPEED_I2CD_INTR_ALL) /* 0x14 : I2CD Command/Status Register */ #define ASPEED_I2CD_SCL_LINE_STS BIT(18) @@ -103,6 +136,10 @@ #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11) /* Command Bit */ +#define ASPEED_I2CD_RX_DMA_ENABLE BIT(9) +#define ASPEED_I2CD_TX_DMA_ENABLE BIT(8) +#define ASPEED_I2CD_RX_BUFF_ENABLE BIT(7) +#define ASPEED_I2CD_TX_BUFF_ENABLE BIT(6) #define ASPEED_I2CD_M_STOP_CMD BIT(5) #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4) #define ASPEED_I2CD_M_RX_CMD BIT(3) @@ -119,6 +156,21 @@ /* 0x18 : I2CD Slave Device Address Register */ #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0) +/* 0x1c : I2CD Buffer Control Register */ +/* Use 8-bits or 6-bits wide bit fileds to support both AST2400 and AST2500 */ +#define ASPEED_I2CD_BUF_RX_COUNT_MASK GENMASK(31, 24) +#define ASPEED_I2CD_BUF_RX_SIZE_MASK GENMASK(23, 16) +#define ASPEED_I2CD_BUF_TX_COUNT_MASK GENMASK(15, 8) +#define ASPEED_I2CD_BUF_OFFSET_MASK GENMASK(5, 0) + +/* 0x24 : I2CD DMA Mode Buffer Address Register */ +#define ASPEED_I2CD_DMA_ADDR_MASK GENMASK(31, 2) +#define ASPEED_I2CD_DMA_ALIGN 4 + +/* 0x28 : I2CD DMA Transfer Length Register */ +#define ASPEED_I2CD_DMA_LEN_SHIFT 0 +#define ASPEED_I2CD_DMA_LEN_MASK GENMASK(11, 0) + enum aspeed_i2c_master_state { ASPEED_I2C_MASTER_INACTIVE, ASPEED_I2C_MASTER_PENDING, @@ -137,6 +189,8 @@ enum aspeed_i2c_slave_state { ASPEED_I2C_SLAVE_READ_PROCESSED, ASPEED_I2C_SLAVE_WRITE_REQUESTED, ASPEED_I2C_SLAVE_WRITE_RECEIVED, + ASPEED_I2C_SLAVE_GCALL_START, + ASPEED_I2C_SLAVE_GCALL_REQUESTED, ASPEED_I2C_SLAVE_STOP, }; @@ -152,6 +206,7 @@ struct aspeed_i2c_bus { u32 divisor); unsigned long parent_clk_frequency; u32 bus_frequency; + u32 hw_timeout_ms; /* Transaction state. */ enum aspeed_i2c_master_state master_state; struct i2c_msg *msgs; @@ -164,12 +219,43 @@ struct aspeed_i2c_bus { int master_xfer_result; /* Multi-master */ bool multi_master; + /* Buffer mode */ + void __iomem *buf_base; + u8 buf_offset; + u8 buf_page; + /* DMA mode */ + struct dma_pool *dma_pool; + dma_addr_t dma_handle; + u8 *dma_buf; + size_t dma_len; + /* Buffer/DMA mode */ + size_t buf_size; #if IS_ENABLED(CONFIG_I2C_SLAVE) struct i2c_client *slave; enum aspeed_i2c_slave_state slave_state; + /* General call */ + bool general_call; #endif /* CONFIG_I2C_SLAVE */ }; +static bool dump_debug __read_mostly; +static int dump_debug_bus_id __read_mostly; + +#define I2C_HEX_DUMP(bus, addr, flags, buf, len) \ + do { \ + if (dump_debug && (bus)->adap.nr == dump_debug_bus_id) { \ + char dump_info[100] = {0,}; \ + char task_info[TASK_COMM_LEN]; \ + get_task_comm(task_info, current); \ + snprintf(dump_info, sizeof(dump_info), \ + "bus_id:%d, addr:0x%02x, flags:0x%02x, task:%s(%d): ", \ + (bus)->adap.nr, addr, flags, task_info, \ + task_pid_nr(current)); \ + print_hex_dump(KERN_ERR, dump_info, DUMP_PREFIX_NONE, \ + 16, 1, buf, len, true); \ + } \ + } while (0) + static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus); static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus) @@ -241,6 +327,123 @@ reset_out: } #if IS_ENABLED(CONFIG_I2C_SLAVE) +static int aspeed_i2c_check_slave_error(u32 irq_status) +{ + if (irq_status & ASPEED_I2CD_INTR_SLAVE_INACTIVE_TIMEOUT) + return -EIO; + + return 0; +} + +static inline void +aspeed_i2c_slave_handle_rx_done(struct aspeed_i2c_bus *bus, u32 irq_status, + u8 *value) +{ + if (bus->dma_buf && + bus->slave_state == ASPEED_I2C_SLAVE_WRITE_RECEIVED && + !(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP)) + *value = bus->dma_buf[0]; + else if (bus->buf_base && + bus->slave_state == ASPEED_I2C_SLAVE_WRITE_RECEIVED && + !(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP)) + *value = readb(bus->buf_base); + else + *value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; +} + +static inline void +aspeed_i2c_slave_handle_normal_stop(struct aspeed_i2c_bus *bus, u32 irq_status, + u8 *value) +{ + int i, len; + + if (bus->slave_state == ASPEED_I2C_SLAVE_WRITE_RECEIVED && + irq_status & ASPEED_I2CD_INTR_RX_DONE) { + if (bus->dma_buf) { + len = bus->buf_size - + FIELD_GET(ASPEED_I2CD_DMA_LEN_MASK, + readl(bus->base + + ASPEED_I2C_DMA_LEN_REG)); + for (i = 0; i < len; i++) { + *value = bus->dma_buf[i]; + i2c_slave_event(bus->slave, + I2C_SLAVE_WRITE_RECEIVED, + value); + } + } else if (bus->buf_base) { + len = FIELD_GET(ASPEED_I2CD_BUF_RX_COUNT_MASK, + readl(bus->base + + ASPEED_I2C_BUF_CTRL_REG)); + for (i = 0; i < len; i++) { + *value = readb(bus->buf_base + i); + i2c_slave_event(bus->slave, + I2C_SLAVE_WRITE_RECEIVED, + value); + } + } + } +} + +static inline void +aspeed_i2c_slave_handle_write_requested(struct aspeed_i2c_bus *bus, u8 *value) +{ + if (bus->dma_buf) { + writel(bus->dma_handle & ASPEED_I2CD_DMA_ADDR_MASK, + bus->base + ASPEED_I2C_DMA_ADDR_REG); + writel(FIELD_PREP(ASPEED_I2CD_DMA_LEN_MASK, bus->buf_size), + bus->base + ASPEED_I2C_DMA_LEN_REG); + writel(ASPEED_I2CD_RX_DMA_ENABLE, + bus->base + ASPEED_I2C_CMD_REG); + } else if (bus->buf_base) { + writel(FIELD_PREP(ASPEED_I2CD_BUF_RX_SIZE_MASK, + bus->buf_size - 1) | + FIELD_PREP(ASPEED_I2CD_BUF_OFFSET_MASK, + bus->buf_offset), + bus->base + ASPEED_I2C_BUF_CTRL_REG); + writel(ASPEED_I2CD_RX_BUFF_ENABLE, + bus->base + ASPEED_I2C_CMD_REG); + } +} + +static inline void +aspeed_i2c_slave_handle_write_received(struct aspeed_i2c_bus *bus, u8 *value) +{ + int i, len; + + if (bus->dma_buf) { + len = bus->buf_size - + FIELD_GET(ASPEED_I2CD_DMA_LEN_MASK, + readl(bus->base + + ASPEED_I2C_DMA_LEN_REG)); + for (i = 1; i < len; i++) { + *value = bus->dma_buf[i]; + i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED, + value); + } + writel(bus->dma_handle & ASPEED_I2CD_DMA_ADDR_MASK, + bus->base + ASPEED_I2C_DMA_ADDR_REG); + writel(FIELD_PREP(ASPEED_I2CD_DMA_LEN_MASK, bus->buf_size), + bus->base + ASPEED_I2C_DMA_LEN_REG); + writel(ASPEED_I2CD_RX_DMA_ENABLE, + bus->base + ASPEED_I2C_CMD_REG); + } else if (bus->buf_base) { + len = FIELD_GET(ASPEED_I2CD_BUF_RX_COUNT_MASK, + readl(bus->base + + ASPEED_I2C_BUF_CTRL_REG)); + for (i = 1; i < len; i++) { + *value = readb(bus->buf_base + i); + i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED, + value); + } + writel(FIELD_PREP(ASPEED_I2CD_BUF_RX_SIZE_MASK, + bus->buf_size - 1) | + FIELD_PREP(ASPEED_I2CD_BUF_OFFSET_MASK, bus->buf_offset), + bus->base + ASPEED_I2C_BUF_CTRL_REG); + writel(ASPEED_I2CD_RX_BUFF_ENABLE, + bus->base + ASPEED_I2C_CMD_REG); + } +} + static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status) { u32 command, irq_handled = 0; @@ -250,6 +453,14 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status) if (!slave) return 0; + if (aspeed_i2c_check_slave_error(irq_status)) { + dev_dbg(bus->dev, "received slave error interrupt: 0x%08x\n", + irq_status); + irq_handled |= (irq_status & ASPEED_I2CD_INTR_SLAVE_ERRORS); + bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE; + return irq_handled; + } + command = readl(bus->base + ASPEED_I2C_CMD_REG); /* Slave was requested, restart state machine. */ @@ -258,6 +469,12 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status) bus->slave_state = ASPEED_I2C_SLAVE_START; } + /* General call was requested, restart state machine. */ + if (irq_status & ASPEED_I2CD_INTR_GCALL_ADDR) { + irq_handled |= ASPEED_I2CD_INTR_GCALL_ADDR; + bus->slave_state = ASPEED_I2C_SLAVE_GCALL_START; + } + /* Slave is not currently active, irq was for someone else. */ if (bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE) return irq_handled; @@ -265,9 +482,21 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status) dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n", irq_status, command); + /* + * If a peer master sends messages too quickly before it processes + * previous slave DMA data handling, this indicator will be set. It's + * just a indicator and driver can't recover this case so just ignore + * it. + */ + if (unlikely(irq_status & + ASPEED_I2CD_INTR_SLAVE_ADDR_RECEIVED_PENDING)) { + dev_dbg(bus->dev, "A slave addr match interrupt is pending.\n"); + irq_handled |= ASPEED_I2CD_INTR_SLAVE_ADDR_RECEIVED_PENDING; + } + /* Slave was sent something. */ if (irq_status & ASPEED_I2CD_INTR_RX_DONE) { - value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; + aspeed_i2c_slave_handle_rx_done(bus, irq_status, &value); /* Handle address frame. */ if (bus->slave_state == ASPEED_I2C_SLAVE_START) { if (value & 0x1) @@ -276,15 +505,32 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status) else bus->slave_state = ASPEED_I2C_SLAVE_WRITE_REQUESTED; + } else if (bus->slave_state == ASPEED_I2C_SLAVE_GCALL_START) { + /* + * I2C spec defines the second byte meaning like below. + * 0x06 : Reset and write programmable part of slave + * address by hardware. + * 0x04 : Write programmable part of slave address by + * hardware. + * 0x00 : No allowed. + * + * But in OpenBMC, we are going to use this + * 'General call' feature for IPMB message broadcasting + * so it delivers all data as is without any specific + * handling of the second byte. + */ + bus->slave_state = ASPEED_I2C_SLAVE_GCALL_REQUESTED; } irq_handled |= ASPEED_I2CD_INTR_RX_DONE; } /* Slave was asked to stop. */ if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) { + aspeed_i2c_slave_handle_normal_stop(bus, irq_status, &value); irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP; bus->slave_state = ASPEED_I2C_SLAVE_STOP; } + if (irq_status & ASPEED_I2CD_INTR_TX_NAK && bus->slave_state == ASPEED_I2C_SLAVE_READ_PROCESSED) { irq_handled |= ASPEED_I2CD_INTR_TX_NAK; @@ -314,15 +560,22 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status) case ASPEED_I2C_SLAVE_WRITE_REQUESTED: bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED; i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); + aspeed_i2c_slave_handle_write_requested(bus, &value); break; case ASPEED_I2C_SLAVE_WRITE_RECEIVED: i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value); + aspeed_i2c_slave_handle_write_received(bus, &value); + break; + case ASPEED_I2C_SLAVE_GCALL_REQUESTED: + bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED; + i2c_slave_event(slave, I2C_SLAVE_GCALL_REQUESTED, &value); break; case ASPEED_I2C_SLAVE_STOP: i2c_slave_event(slave, I2C_SLAVE_STOP, &value); bus->slave_state = ASPEED_I2C_SLAVE_INACTIVE; break; case ASPEED_I2C_SLAVE_START: + case ASPEED_I2C_SLAVE_GCALL_START: /* Slave was just started. Waiting for the next event. */; break; default: @@ -336,12 +589,95 @@ static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status) } #endif /* CONFIG_I2C_SLAVE */ +static inline u32 +aspeed_i2c_prepare_rx_buf(struct aspeed_i2c_bus *bus, struct i2c_msg *msg) +{ + u32 command = 0; + int len; + + if (msg->len > bus->buf_size) { + len = bus->buf_size; + } else { + len = msg->len; + command |= ASPEED_I2CD_M_S_RX_CMD_LAST; + } + + if (bus->dma_buf) { + command |= ASPEED_I2CD_RX_DMA_ENABLE; + + writel(bus->dma_handle & ASPEED_I2CD_DMA_ADDR_MASK, + bus->base + ASPEED_I2C_DMA_ADDR_REG); + writel(FIELD_PREP(ASPEED_I2CD_DMA_LEN_MASK, len), + bus->base + ASPEED_I2C_DMA_LEN_REG); + bus->dma_len = len; + } else { + command |= ASPEED_I2CD_RX_BUFF_ENABLE; + + writel(FIELD_PREP(ASPEED_I2CD_BUF_RX_SIZE_MASK, len - 1) | + FIELD_PREP(ASPEED_I2CD_BUF_OFFSET_MASK, bus->buf_offset), + bus->base + ASPEED_I2C_BUF_CTRL_REG); + } + + return command; +} + +static inline u32 +aspeed_i2c_prepare_tx_buf(struct aspeed_i2c_bus *bus, struct i2c_msg *msg) +{ + u8 slave_addr = i2c_8bit_addr_from_msg(msg); + u32 command = 0; + int len; + + if (msg->len + 1 > bus->buf_size) + len = bus->buf_size; + else + len = msg->len + 1; + + if (bus->dma_buf) { + command |= ASPEED_I2CD_TX_DMA_ENABLE; + + bus->dma_buf[0] = slave_addr; + memcpy(bus->dma_buf + 1, msg->buf, len); + + writel(bus->dma_handle & ASPEED_I2CD_DMA_ADDR_MASK, + bus->base + ASPEED_I2C_DMA_ADDR_REG); + writel(FIELD_PREP(ASPEED_I2CD_DMA_LEN_MASK, len), + bus->base + ASPEED_I2C_DMA_LEN_REG); + bus->dma_len = len; + } else { + u8 wbuf[4]; + int i; + + command |= ASPEED_I2CD_TX_BUFF_ENABLE; + + /* + * Yeah, it looks bad but byte writing on remapped I2C SRAM + * causes corruption so use this way to make dword writings. + */ + wbuf[0] = slave_addr; + for (i = 1; i < len; i++) { + wbuf[i % 4] = msg->buf[i - 1]; + if (i % 4 == 3) + writel(*(u32 *)wbuf, bus->buf_base + i - 3); + } + if (--i % 4 != 3) + writel(*(u32 *)wbuf, bus->buf_base + i - (i % 4)); + + writel(FIELD_PREP(ASPEED_I2CD_BUF_TX_COUNT_MASK, len - 1) | + FIELD_PREP(ASPEED_I2CD_BUF_OFFSET_MASK, bus->buf_offset), + bus->base + ASPEED_I2C_BUF_CTRL_REG); + } + + bus->buf_index = len - 1; + + return command; +} + /* precondition: bus.lock has been acquired. */ static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus) { u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD; struct i2c_msg *msg = &bus->msgs[bus->msgs_index]; - u8 slave_addr = i2c_8bit_addr_from_msg(msg); #if IS_ENABLED(CONFIG_I2C_SLAVE) /* @@ -360,12 +696,22 @@ static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus) if (msg->flags & I2C_M_RD) { command |= ASPEED_I2CD_M_RX_CMD; - /* Need to let the hardware know to NACK after RX. */ - if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN)) - command |= ASPEED_I2CD_M_S_RX_CMD_LAST; + if (!(msg->flags & I2C_M_RECV_LEN)) { + if (msg->len && (bus->dma_buf || bus->buf_base)) + command |= aspeed_i2c_prepare_rx_buf(bus, msg); + + /* Need to let the hardware know to NACK after RX. */ + if (msg->len <= 1) + command |= ASPEED_I2CD_M_S_RX_CMD_LAST; + } + } else if (msg->len && (bus->dma_buf || bus->buf_base)) { + command |= aspeed_i2c_prepare_tx_buf(bus, msg); } - writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG); + if (!(command & (ASPEED_I2CD_TX_BUFF_ENABLE | + ASPEED_I2CD_TX_DMA_ENABLE))) + writel(i2c_8bit_addr_from_msg(msg), + bus->base + ASPEED_I2C_BYTE_BUF_REG); writel(command, bus->base + ASPEED_I2C_CMD_REG); } @@ -387,7 +733,7 @@ static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus) } } -static int aspeed_i2c_is_irq_error(u32 irq_status) +static int aspeed_i2c_check_master_error(u32 irq_status) { if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS) return -EAGAIN; @@ -400,6 +746,134 @@ static int aspeed_i2c_is_irq_error(u32 irq_status) return 0; } +static inline u32 +aspeed_i2c_master_handle_tx_first(struct aspeed_i2c_bus *bus, + struct i2c_msg *msg) +{ + u32 command = 0; + + if (bus->dma_buf || bus->buf_base) { + int len; + + if (msg->len - bus->buf_index > bus->buf_size) + len = bus->buf_size; + else + len = msg->len - bus->buf_index; + + if (bus->dma_buf) { + command |= ASPEED_I2CD_TX_DMA_ENABLE; + + memcpy(bus->dma_buf, msg->buf + bus->buf_index, len); + + + writel(bus->dma_handle & ASPEED_I2CD_DMA_ADDR_MASK, + bus->base + ASPEED_I2C_DMA_ADDR_REG); + writel(FIELD_PREP(ASPEED_I2CD_DMA_LEN_MASK, len), + bus->base + ASPEED_I2C_DMA_LEN_REG); + bus->dma_len = len; + } else { + u8 wbuf[4]; + int i; + + command |= ASPEED_I2CD_TX_BUFF_ENABLE; + + if (msg->len - bus->buf_index > bus->buf_size) + len = bus->buf_size; + else + len = msg->len - bus->buf_index; + + for (i = 0; i < len; i++) { + wbuf[i % 4] = msg->buf[bus->buf_index + i]; + if (i % 4 == 3) + writel(*(u32 *)wbuf, + bus->buf_base + i - 3); + } + if (--i % 4 != 3) + writel(*(u32 *)wbuf, + bus->buf_base + i - (i % 4)); + + writel(FIELD_PREP(ASPEED_I2CD_BUF_TX_COUNT_MASK, + len - 1) | + FIELD_PREP(ASPEED_I2CD_BUF_OFFSET_MASK, + bus->buf_offset), + bus->base + ASPEED_I2C_BUF_CTRL_REG); + } + + bus->buf_index += len; + } else { + writel(msg->buf[bus->buf_index++], + bus->base + ASPEED_I2C_BYTE_BUF_REG); + } + + return command; +} + +static inline void +aspeed_i2c_master_handle_rx(struct aspeed_i2c_bus *bus, struct i2c_msg *msg) +{ + u8 recv_byte; + int len; + + if (bus->dma_buf) { + len = bus->dma_len - + FIELD_GET(ASPEED_I2CD_DMA_LEN_MASK, + readl(bus->base + ASPEED_I2C_DMA_LEN_REG)); + + memcpy(msg->buf + bus->buf_index, bus->dma_buf, len); + bus->buf_index += len; + } else if (bus->buf_base) { + len = FIELD_GET(ASPEED_I2CD_BUF_RX_COUNT_MASK, + readl(bus->base + ASPEED_I2C_BUF_CTRL_REG)); + memcpy_fromio(msg->buf + bus->buf_index, bus->buf_base, len); + bus->buf_index += len; + } else { + recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; + msg->buf[bus->buf_index++] = recv_byte; + } +} + +static inline u32 +aspeed_i2c_master_handle_rx_next(struct aspeed_i2c_bus *bus, + struct i2c_msg *msg) +{ + u32 command = 0; + + if (bus->dma_buf || bus->buf_base) { + int len; + + if (msg->len - bus->buf_index > bus->buf_size) { + len = bus->buf_size; + } else { + len = msg->len - bus->buf_index; + command |= ASPEED_I2CD_M_S_RX_CMD_LAST; + } + + if (bus->dma_buf) { + command |= ASPEED_I2CD_RX_DMA_ENABLE; + + writel(bus->dma_handle & ASPEED_I2CD_DMA_ADDR_MASK, + bus->base + ASPEED_I2C_DMA_ADDR_REG); + writel(FIELD_PREP(ASPEED_I2CD_DMA_LEN_MASK, len), + bus->base + ASPEED_I2C_DMA_LEN_REG); + bus->dma_len = len; + } else { + command |= ASPEED_I2CD_RX_BUFF_ENABLE; + + writel(FIELD_PREP(ASPEED_I2CD_BUF_RX_SIZE_MASK, + len - 1) | + FIELD_PREP(ASPEED_I2CD_BUF_TX_COUNT_MASK, 0) | + FIELD_PREP(ASPEED_I2CD_BUF_OFFSET_MASK, + bus->buf_offset), + bus->base + ASPEED_I2C_BUF_CTRL_REG); + } + } else { + if (bus->buf_index + 1 == msg->len) + command |= ASPEED_I2CD_M_S_RX_CMD_LAST; + } + + return command; +} + static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status) { u32 irq_handled = 0, command = 0; @@ -418,13 +892,19 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status) * should clear the command queue effectively taking us back to the * INACTIVE state. */ - ret = aspeed_i2c_is_irq_error(irq_status); + ret = aspeed_i2c_check_master_error(irq_status); if (ret) { - dev_dbg(bus->dev, "received error interrupt: 0x%08x\n", + dev_dbg(bus->dev, "received master error interrupt: 0x%08x\n", irq_status); irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS); if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) { bus->cmd_err = ret; + if (bus->master_state == ASPEED_I2C_MASTER_STOP) + irq_handled |= (irq_status & + ASPEED_I2CD_INTR_NORMAL_STOP); + if (ret == -EAGAIN) + irq_handled |= (irq_status & + ASPEED_I2CD_INTR_TX_ACK); bus->master_state = ASPEED_I2C_MASTER_INACTIVE; goto out_complete; } @@ -508,11 +988,10 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status) fallthrough; case ASPEED_I2C_MASTER_TX_FIRST: if (bus->buf_index < msg->len) { + command = ASPEED_I2CD_M_TX_CMD; + command |= aspeed_i2c_master_handle_tx_first(bus, msg); + writel(command, bus->base + ASPEED_I2C_CMD_REG); bus->master_state = ASPEED_I2C_MASTER_TX; - writel(msg->buf[bus->buf_index++], - bus->base + ASPEED_I2C_BYTE_BUF_REG); - writel(ASPEED_I2CD_M_TX_CMD, - bus->base + ASPEED_I2C_CMD_REG); } else { aspeed_i2c_next_msg_or_stop(bus); } @@ -529,26 +1008,26 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status) } irq_handled |= ASPEED_I2CD_INTR_RX_DONE; - recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; - msg->buf[bus->buf_index++] = recv_byte; - if (msg->flags & I2C_M_RECV_LEN) { + recv_byte = readl(bus->base + + ASPEED_I2C_BYTE_BUF_REG) >> 8; if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) { bus->cmd_err = -EPROTO; aspeed_i2c_do_stop(bus); goto out_no_complete; } - msg->len = recv_byte + - ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1); + msg->len = recv_byte + ((msg->flags & I2C_CLIENT_PEC) ? + 2 : 1); msg->flags &= ~I2C_M_RECV_LEN; + } else if (msg->len) { + aspeed_i2c_master_handle_rx(bus, msg); } if (bus->buf_index < msg->len) { - bus->master_state = ASPEED_I2C_MASTER_RX; command = ASPEED_I2CD_M_RX_CMD; - if (bus->buf_index + 1 == msg->len) - command |= ASPEED_I2CD_M_S_RX_CMD_LAST; + command |= aspeed_i2c_master_handle_rx_next(bus, msg); writel(command, bus->base + ASPEED_I2C_CMD_REG); + bus->master_state = ASPEED_I2C_MASTER_RX; } else { aspeed_i2c_next_msg_or_stop(bus); } @@ -625,9 +1104,14 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) } else { irq_handled = aspeed_i2c_slave_irq(bus, irq_remaining); irq_remaining &= ~irq_handled; - if (irq_remaining) + if (irq_remaining) { irq_handled |= aspeed_i2c_master_irq(bus, irq_remaining); + if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE && + bus->slave_state == ASPEED_I2C_SLAVE_INACTIVE) + irq_handled |= (irq_remaining & + ASPEED_I2CD_INTR_NORMAL_STOP); + } } /* @@ -662,6 +1146,7 @@ static int aspeed_i2c_master_xfer(struct i2c_adapter *adap, { struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap); unsigned long time_left, flags; + int i; spin_lock_irqsave(&bus->lock, flags); bus->cmd_err = 0; @@ -713,6 +1198,11 @@ static int aspeed_i2c_master_xfer(struct i2c_adapter *adap, return -ETIMEDOUT; } + for (i = 0; i < num; i++) { + I2C_HEX_DUMP(bus, msgs[i].addr, msgs[i].flags, + msgs[i].buf, msgs[i].len); + } + return bus->master_xfer_result; } @@ -736,6 +1226,8 @@ static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr) /* Turn on slave mode. */ func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN; + if (bus->general_call) + func_ctrl_reg_val |= ASPEED_I2CD_GCALL_EN; writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); } @@ -774,6 +1266,8 @@ static int aspeed_i2c_unreg_slave(struct i2c_client *client) /* Turn off slave mode. */ func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN; + if (bus->general_call) + func_ctrl_reg_val &= ~ASPEED_I2CD_GCALL_EN; writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); bus->slave = NULL; @@ -880,6 +1374,7 @@ static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor) /* precondition: bus.lock has been acquired. */ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) { + u32 timeout_base_divisor, timeout_tick_us, timeout_cycles; u32 divisor, clk_reg_val; divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency); @@ -888,8 +1383,46 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) ASPEED_I2CD_TIME_THDSTA_MASK | ASPEED_I2CD_TIME_TACST_MASK); clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor); + + if (bus->hw_timeout_ms) { + u8 div_max = ASPEED_I2CD_TIME_TIMEOUT_BASE_DIVISOR_MASK >> + ASPEED_I2CD_TIME_TIMEOUT_BASE_DIVISOR_SHIFT; + u8 cycles_max = ASPEED_I2CD_TIMEOUT_CYCLES_MASK >> + ASPEED_I2CD_TIMEOUT_CYCLES_SHIFT; + + timeout_base_divisor = 0; + + do { + timeout_tick_us = 1000 * (16384 << + (timeout_base_divisor << 1)) / + (bus->parent_clk_frequency / 1000); + + if (timeout_base_divisor == div_max || + timeout_tick_us * ASPEED_I2CD_TIMEOUT_CYCLES_MASK >= + bus->hw_timeout_ms * 1000) + break; + } while (timeout_base_divisor++ < div_max); + + if (timeout_tick_us) { + timeout_cycles = DIV_ROUND_UP(bus->hw_timeout_ms * 1000, + timeout_tick_us); + if (timeout_cycles == 0) + timeout_cycles = 1; + else if (timeout_cycles > cycles_max) + timeout_cycles = cycles_max; + } else { + timeout_cycles = 0; + } + } else { + timeout_base_divisor = 0; + timeout_cycles = 0; + } + + clk_reg_val |= FIELD_PREP(ASPEED_I2CD_TIME_TIMEOUT_BASE_DIVISOR_MASK, + timeout_base_divisor); + writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); - writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); + writel(timeout_cycles, bus->base + ASPEED_I2C_AC_TIMING_REG2); return 0; } @@ -904,10 +1437,18 @@ static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, /* Disable everything. */ writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); + device_property_read_u32(&pdev->dev, "aspeed,hw-timeout-ms", + &bus->hw_timeout_ms); + if (bus->hw_timeout_ms) + fun_ctrl_reg |= ASPEED_I2CD_BUS_AUTO_RECOVERY_EN; + ret = aspeed_i2c_init_clk(bus); if (ret < 0) return ret; + fun_ctrl_reg |= FIELD_PREP(ASPEED_I2CD_BUFFER_PAGE_SEL_MASK, + bus->buf_page); + if (of_property_read_bool(pdev->dev.of_node, "multi-master")) bus->multi_master = true; else @@ -918,6 +1459,9 @@ static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, bus->base + ASPEED_I2C_FUN_CTRL_REG); #if IS_ENABLED(CONFIG_I2C_SLAVE) + if (of_property_read_bool(pdev->dev.of_node, "general-call")) + bus->general_call = true; + /* If slave has already been registered, re-enable it. */ if (bus->slave) __aspeed_i2c_reg_slave(bus, bus->slave->addr); @@ -948,6 +1492,96 @@ static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus) return ret; } +static void aspeed_i2c_set_xfer_mode(struct aspeed_i2c_bus *bus) +{ + struct platform_device *pdev = to_platform_device(bus->dev); + bool sram_enabled = true; + int ret; + + /* + * Enable I2C SRAM in case of AST2500. + * SRAM is enabled by default in AST2400 and AST2600. + */ + if (of_device_is_compatible(pdev->dev.of_node, + "aspeed,ast2500-i2c-bus")) { + struct regmap *gr_regmap = syscon_regmap_lookup_by_compatible("aspeed,ast2500-i2c-gr"); + + if (IS_ERR(gr_regmap)) + ret = PTR_ERR(gr_regmap); + else + ret = regmap_update_bits(gr_regmap, + ASPEED_I2CG_GLOBAL_CTRL_REG, + ASPEED_I2CG_SRAM_BUFFER_EN, + ASPEED_I2CG_SRAM_BUFFER_EN); + + if (ret) + sram_enabled = false; + } + + /* + * Only AST2500 and AST2600 support DMA mode under some limitations: + * I2C is sharing the DMA H/W with UHCI host controller and MCTP + * controller. Since those controllers operate with DMA mode only, I2C + * has to use buffer mode or byte mode instead if one of those + * controllers is enabled. Also make sure that if SD/eMMC or Port80 + * snoop uses DMA mode instead of PIO or FIFO respectively, I2C can't + * use DMA mode. + */ + if (sram_enabled && !IS_ENABLED(CONFIG_USB_UHCI_ASPEED) && + !of_device_is_compatible(pdev->dev.of_node, + "aspeed,ast2400-i2c-bus")) { + u32 dma_len_max = ASPEED_I2CD_DMA_LEN_MASK >> + ASPEED_I2CD_DMA_LEN_SHIFT; + + ret = device_property_read_u32(&pdev->dev, + "aspeed,dma-buf-size", + &bus->buf_size); + if (!ret && bus->buf_size > dma_len_max) + bus->buf_size = dma_len_max; + } + + if (bus->buf_size) { + if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { + dev_warn(&pdev->dev, "No suitable DMA available\n"); + } else { + bus->dma_pool = dma_pool_create("i2c-aspeed", + &pdev->dev, + bus->buf_size, + ASPEED_I2CD_DMA_ALIGN, + 0); + if (bus->dma_pool) + bus->dma_buf = dma_pool_alloc(bus->dma_pool, + GFP_KERNEL, + &bus->dma_handle); + + if (!bus->dma_buf) { + dev_warn(&pdev->dev, + "Cannot allocate DMA buffer\n"); + dma_pool_destroy(bus->dma_pool); + } + } + } + + if (!bus->dma_buf && sram_enabled) { + struct resource *res = platform_get_resource(pdev, + IORESOURCE_MEM, 1); + + if (res && resource_size(res) >= 2) + bus->buf_base = devm_ioremap_resource(&pdev->dev, res); + + if (!IS_ERR_OR_NULL(bus->buf_base)) { + bus->buf_size = resource_size(res); + if (of_device_is_compatible(pdev->dev.of_node, + "aspeed,ast2400-i2c-bus")) { + bus->buf_page = ((res->start >> 8) & + GENMASK(3, 0)) - 8; + bus->buf_offset = (res->start >> 2) & + ASPEED_I2CD_BUF_OFFSET_MASK; + } + } + } +} + static const struct of_device_id aspeed_i2c_bus_of_table[] = { { .compatible = "aspeed,ast2400-i2c-bus", @@ -970,18 +1604,26 @@ static int aspeed_i2c_probe_bus(struct platform_device *pdev) const struct of_device_id *match; struct aspeed_i2c_bus *bus; struct clk *parent_clk; - struct resource *res; int irq, ret; bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); if (!bus) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - bus->base = devm_ioremap_resource(&pdev->dev, res); + bus->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(bus->base)) return PTR_ERR(bus->base); + bus->dev = &pdev->dev; + + /* Disable bus and clean up any left over interrupt state. */ + writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); + writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); + writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); + + /* Clear slave addresses. */ + writel(0, bus->base + ASPEED_I2C_DEV_ADDR_REG); + parent_clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(parent_clk)) return PTR_ERR(parent_clk); @@ -1012,46 +1654,47 @@ static int aspeed_i2c_probe_bus(struct platform_device *pdev) bus->get_clk_reg_val = (u32 (*)(struct device *, u32)) match->data; + aspeed_i2c_set_xfer_mode(bus); + /* Initialize the I2C adapter */ spin_lock_init(&bus->lock); init_completion(&bus->cmd_complete); bus->adap.owner = THIS_MODULE; - bus->adap.retries = 0; bus->adap.algo = &aspeed_i2c_algo; bus->adap.dev.parent = &pdev->dev; bus->adap.dev.of_node = pdev->dev.of_node; strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); i2c_set_adapdata(&bus->adap, bus); - bus->dev = &pdev->dev; - - /* Clean up any left over interrupt state. */ - writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); - writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); - /* - * bus.lock does not need to be held because the interrupt handler has - * not been enabled yet. - */ - ret = aspeed_i2c_init(bus, pdev); - if (ret < 0) - return ret; - irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq, 0, dev_name(&pdev->dev), bus); if (ret < 0) - return ret; + goto out_free_dma_buf; + + ret = aspeed_i2c_init(bus, pdev); + if (ret < 0) + goto out_free_dma_buf; ret = i2c_add_adapter(&bus->adap); if (ret < 0) - return ret; + goto out_free_dma_buf; platform_set_drvdata(pdev, bus); - dev_info(bus->dev, "i2c bus %d registered, irq %d\n", - bus->adap.nr, irq); + dev_info(bus->dev, "i2c bus %d registered (%s mode), irq %d\n", + bus->adap.nr, bus->dma_buf ? "dma" : + bus->buf_base ? "buffer" : "byte", + irq); return 0; + +out_free_dma_buf: + if (bus->dma_buf) + dma_pool_free(bus->dma_pool, bus->dma_buf, bus->dma_handle); + dma_pool_destroy(bus->dma_pool); + + return ret; } static int aspeed_i2c_remove_bus(struct platform_device *pdev) @@ -1069,6 +1712,10 @@ static int aspeed_i2c_remove_bus(struct platform_device *pdev) reset_control_assert(bus->rst); + if (bus->dma_buf) + dma_pool_free(bus->dma_pool, bus->dma_buf, bus->dma_handle); + dma_pool_destroy(bus->dma_pool); + i2c_del_adapter(&bus->adap); return 0; @@ -1084,6 +1731,11 @@ static struct platform_driver aspeed_i2c_bus_driver = { }; module_platform_driver(aspeed_i2c_bus_driver); +module_param_named(dump_debug, dump_debug, bool, 0644); +MODULE_PARM_DESC(dump_debug, "debug flag for dump printing"); +module_param_named(dump_debug_bus_id, dump_debug_bus_id, int, 0644); +MODULE_PARM_DESC(dump_debug_bus_id, "bus id for dump debug printing"); + MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>"); MODULE_DESCRIPTION("Aspeed I2C Bus Driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/i2c/i2c-core-base.c b/drivers/i2c/i2c-core-base.c index bdce6d3e5327..7d9c685af49c 100644 --- a/drivers/i2c/i2c-core-base.c +++ b/drivers/i2c/i2c-core-base.c @@ -1395,8 +1395,30 @@ int i2c_handle_smbus_host_notify(struct i2c_adapter *adap, unsigned short addr) } EXPORT_SYMBOL_GPL(i2c_handle_smbus_host_notify); +static void i2c_adapter_hold(struct i2c_adapter *adapter, unsigned long timeout) +{ + mutex_lock(&adapter->hold_lock); + schedule_delayed_work(&adapter->unhold_work, timeout); +} + +static void i2c_adapter_unhold(struct i2c_adapter *adapter) +{ + cancel_delayed_work_sync(&adapter->unhold_work); + mutex_unlock(&adapter->hold_lock); +} + +static void i2c_adapter_unhold_work(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct i2c_adapter *adapter = container_of(dwork, struct i2c_adapter, + unhold_work); + + mutex_unlock(&adapter->hold_lock); +} + static int i2c_register_adapter(struct i2c_adapter *adap) { + u32 bus_timeout_ms = 0; int res = -EINVAL; /* Can't register until after driver model init */ @@ -1424,8 +1446,15 @@ static int i2c_register_adapter(struct i2c_adapter *adap) INIT_LIST_HEAD(&adap->userspace_clients); /* Set default timeout to 1 second if not already set */ - if (adap->timeout == 0) - adap->timeout = HZ; + if (adap->timeout == 0) { + device_property_read_u32(&adap->dev, "bus-timeout-ms", + &bus_timeout_ms); + adap->timeout = bus_timeout_ms ? + msecs_to_jiffies(bus_timeout_ms) : HZ; + } + + /* Set retries count if it has the property setting */ + device_property_read_u32(&adap->dev, "#retries", &adap->retries); /* register soft irqs for Host Notify */ res = i2c_setup_host_notify_irq_domain(adap); @@ -1479,6 +1508,9 @@ static int i2c_register_adapter(struct i2c_adapter *adap) bus_for_each_drv(&i2c_bus_type, NULL, adap, __process_new_adapter); mutex_unlock(&core_lock); + mutex_init(&adap->hold_lock); + INIT_DELAYED_WORK(&adap->unhold_work, i2c_adapter_unhold_work); + return 0; out_reg: @@ -1699,6 +1731,8 @@ void i2c_del_adapter(struct i2c_adapter *adap) idr_remove(&i2c_adapter_idr, adap->nr); mutex_unlock(&core_lock); + i2c_adapter_unhold(adap); + /* Clear the device structure in case this adapter is ever going to be added again */ memset(&adap->dev, 0, sizeof(adap->dev)); @@ -2017,7 +2051,9 @@ static int i2c_check_for_quirks(struct i2c_adapter *adap, struct i2c_msg *msgs, */ int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { + enum i2c_hold_msg_type hold_msg = I2C_HOLD_MSG_NONE; unsigned long orig_jiffies; + unsigned long timeout; int ret, try; if (WARN_ON(!msgs || num < 1)) @@ -2030,6 +2066,25 @@ int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) if (adap->quirks && i2c_check_for_quirks(adap, msgs, num)) return -EOPNOTSUPP; + /* Do not deliver a mux hold msg to root bus adapter */ + if (!i2c_parent_is_i2c_adapter(adap)) { + hold_msg = i2c_check_hold_msg(msgs[num - 1].flags, + msgs[num - 1].len, + (u16 *)msgs[num - 1].buf); + if (hold_msg == I2C_HOLD_MSG_SET) { + timeout = msecs_to_jiffies(*(u16 *)msgs[num - 1].buf); + i2c_adapter_hold(adap, timeout); + + if (--num == 0) + return 0; + } else if (hold_msg == I2C_HOLD_MSG_RESET) { + i2c_adapter_unhold(adap); + return 0; + } else if (hold_msg == I2C_HOLD_MSG_NONE) { + mutex_lock(&adap->hold_lock); + } + } + /* * i2c_trace_msg_key gets enabled when tracepoint i2c_transfer gets * enabled. This is an efficient way of keeping the for-loop from @@ -2066,6 +2121,13 @@ int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) trace_i2c_result(adap, num, ret); } + if (!i2c_parent_is_i2c_adapter(adap)) { + if (hold_msg == I2C_HOLD_MSG_SET && ret < 0) + i2c_adapter_unhold(adap); + else if (hold_msg == I2C_HOLD_MSG_NONE) + mutex_unlock(&adap->hold_lock); + } + return ret; } EXPORT_SYMBOL(__i2c_transfer); @@ -2084,6 +2146,7 @@ EXPORT_SYMBOL(__i2c_transfer); */ int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { + bool do_bus_lock = true; int ret; if (!adap->algo->master_xfer) { @@ -2107,12 +2170,25 @@ int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) * one (discarding status on the second message) or errno * (discarding status on the first one). */ - ret = __i2c_lock_bus_helper(adap); - if (ret) - return ret; + /* + * Do not lock a bus for delivering an unhold msg to a mux + * adpater. This is just for a single length unhold msg case. + */ + if (num == 1 && i2c_parent_is_i2c_adapter(adap) && + i2c_check_hold_msg(msgs[0].flags, msgs[0].len, + (u16 *)msgs[0].buf) == + I2C_HOLD_MSG_RESET) + do_bus_lock = false; + + if (do_bus_lock) { + ret = __i2c_lock_bus_helper(adap); + if (ret) + return ret; + } ret = __i2c_transfer(adap, msgs, num); - i2c_unlock_bus(adap, I2C_LOCK_SEGMENT); + if (do_bus_lock) + i2c_unlock_bus(adap, I2C_LOCK_SEGMENT); return ret; } diff --git a/drivers/i2c/i2c-core-smbus.c b/drivers/i2c/i2c-core-smbus.c index f5c9787992e9..ea95d0482883 100644 --- a/drivers/i2c/i2c-core-smbus.c +++ b/drivers/i2c/i2c-core-smbus.c @@ -533,15 +533,29 @@ s32 i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, unsigned short flags, char read_write, u8 command, int protocol, union i2c_smbus_data *data) { + bool do_bus_lock = true; s32 res; - res = __i2c_lock_bus_helper(adapter); - if (res) - return res; + /* + * Do not lock a bus for delivering an unhold msg to a mux adpater. + * This is just for a single length unhold msg case. + */ + if (i2c_parent_is_i2c_adapter(adapter) && + i2c_check_hold_msg(flags, + protocol == I2C_SMBUS_WORD_DATA ? 2 : 0, + &data->word) == I2C_HOLD_MSG_RESET) + do_bus_lock = false; + + if (do_bus_lock) { + res = __i2c_lock_bus_helper(adapter); + if (res) + return res; + } res = __i2c_smbus_xfer(adapter, addr, flags, read_write, command, protocol, data); - i2c_unlock_bus(adapter, I2C_LOCK_SEGMENT); + if (do_bus_lock) + i2c_unlock_bus(adapter, I2C_LOCK_SEGMENT); return res; } diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index 774507b54b57..ce3c3ad3f129 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -36,21 +36,61 @@ struct i2c_mux_priv { u32 chan_id; }; +static void i2c_mux_hold(struct i2c_mux_core *muxc, unsigned long timeout) +{ + mutex_lock(&muxc->hold_lock); + schedule_delayed_work(&muxc->unhold_work, timeout); +} + +static void i2c_mux_unhold(struct i2c_mux_core *muxc) +{ + cancel_delayed_work_sync(&muxc->unhold_work); + mutex_unlock(&muxc->hold_lock); +} + +static void i2c_mux_unhold_work(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct i2c_mux_core *muxc = container_of(dwork, struct i2c_mux_core, + unhold_work); + + mutex_unlock(&muxc->hold_lock); +} + static int __i2c_mux_master_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct i2c_mux_priv *priv = adap->algo_data; struct i2c_mux_core *muxc = priv->muxc; struct i2c_adapter *parent = muxc->parent; + enum i2c_hold_msg_type hold_msg; + unsigned long timeout; int ret; /* Switch to the right mux port and perform the transfer. */ + hold_msg = i2c_check_hold_msg(msgs[num - 1].flags, + msgs[num - 1].len, + (u16 *)msgs[num - 1].buf); + if (hold_msg == I2C_HOLD_MSG_SET) { + timeout = msecs_to_jiffies(*(u16 *)msgs[num - 1].buf); + i2c_mux_hold(muxc, timeout); + } else if (hold_msg == I2C_HOLD_MSG_NONE) { + mutex_lock(&muxc->hold_lock); + } ret = muxc->select(muxc, priv->chan_id); if (ret >= 0) ret = __i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + if (hold_msg != I2C_HOLD_MSG_SET) { + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); + if (hold_msg == I2C_HOLD_MSG_RESET) + i2c_mux_unhold(muxc); + else + mutex_unlock(&muxc->hold_lock); + } else if (hold_msg == I2C_HOLD_MSG_SET && ret < 0) { + i2c_mux_unhold(muxc); + } return ret; } @@ -61,15 +101,32 @@ static int i2c_mux_master_xfer(struct i2c_adapter *adap, struct i2c_mux_priv *priv = adap->algo_data; struct i2c_mux_core *muxc = priv->muxc; struct i2c_adapter *parent = muxc->parent; + enum i2c_hold_msg_type hold_msg; + unsigned long timeout; int ret; /* Switch to the right mux port and perform the transfer. */ + hold_msg = i2c_check_hold_msg(msgs[num - 1].flags, + msgs[num - 1].len, + (u16 *)msgs[num - 1].buf); + if (hold_msg == I2C_HOLD_MSG_SET) { + timeout = msecs_to_jiffies(*(u16 *)msgs[num - 1].buf); + i2c_mux_hold(muxc, timeout); + } else if (hold_msg == I2C_HOLD_MSG_NONE) { + mutex_lock(&muxc->hold_lock); + } ret = muxc->select(muxc, priv->chan_id); if (ret >= 0) ret = i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + if (hold_msg != I2C_HOLD_MSG_SET) { + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); + if (hold_msg == I2C_HOLD_MSG_RESET) + i2c_mux_unhold(muxc); + else + mutex_unlock(&muxc->hold_lock); + } return ret; } @@ -82,16 +139,33 @@ static int __i2c_mux_smbus_xfer(struct i2c_adapter *adap, struct i2c_mux_priv *priv = adap->algo_data; struct i2c_mux_core *muxc = priv->muxc; struct i2c_adapter *parent = muxc->parent; + enum i2c_hold_msg_type hold_msg; + unsigned long timeout; int ret; /* Select the right mux port and perform the transfer. */ + hold_msg = i2c_check_hold_msg(flags, + size == I2C_SMBUS_WORD_DATA ? 2 : 0, + &data->word); + if (hold_msg == I2C_HOLD_MSG_SET) { + timeout = msecs_to_jiffies(data->word); + i2c_mux_hold(muxc, timeout); + } else if (hold_msg == I2C_HOLD_MSG_NONE) { + mutex_lock(&muxc->hold_lock); + } ret = muxc->select(muxc, priv->chan_id); if (ret >= 0) ret = __i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + if (hold_msg != I2C_HOLD_MSG_SET) { + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); + if (hold_msg == I2C_HOLD_MSG_RESET) + i2c_mux_unhold(muxc); + else + mutex_unlock(&muxc->hold_lock); + } return ret; } @@ -104,16 +178,33 @@ static int i2c_mux_smbus_xfer(struct i2c_adapter *adap, struct i2c_mux_priv *priv = adap->algo_data; struct i2c_mux_core *muxc = priv->muxc; struct i2c_adapter *parent = muxc->parent; + enum i2c_hold_msg_type hold_msg; + unsigned long timeout; int ret; /* Select the right mux port and perform the transfer. */ + hold_msg = i2c_check_hold_msg(flags, + size == I2C_SMBUS_WORD_DATA ? 2 : 0, + &data->word); + if (hold_msg == I2C_HOLD_MSG_SET) { + timeout = msecs_to_jiffies(data->word); + i2c_mux_hold(muxc, timeout); + } else if (hold_msg == I2C_HOLD_MSG_NONE) { + mutex_lock(&muxc->hold_lock); + } ret = muxc->select(muxc, priv->chan_id); if (ret >= 0) ret = i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + if (hold_msg != I2C_HOLD_MSG_SET) { + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); + if (hold_msg == I2C_HOLD_MSG_RESET) + i2c_mux_unhold(muxc); + else + mutex_unlock(&muxc->hold_lock); + } return ret; } @@ -263,6 +354,9 @@ struct i2c_mux_core *i2c_mux_alloc(struct i2c_adapter *parent, muxc->deselect = deselect; muxc->max_adapters = max_adapters; + mutex_init(&muxc->hold_lock); + INIT_DELAYED_WORK(&muxc->unhold_work, i2c_mux_unhold_work); + return muxc; } EXPORT_SYMBOL_GPL(i2c_mux_alloc); @@ -441,6 +535,8 @@ void i2c_mux_del_adapters(struct i2c_mux_core *muxc) { char symlink_name[20]; + i2c_mux_unhold(muxc); + while (muxc->num_adapters) { struct i2c_adapter *adap = muxc->adapter[--muxc->num_adapters]; struct i2c_mux_priv *priv = adap->algo_data; diff --git a/drivers/i2c/i2c-slave-mqueue.c b/drivers/i2c/i2c-slave-mqueue.c new file mode 100644 index 000000000000..1d4db584b393 --- /dev/null +++ b/drivers/i2c/i2c-slave-mqueue.c @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 - 2018, Intel Corporation. + +#include <linux/i2c.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/sysfs.h> + +#define MQ_MSGBUF_SIZE CONFIG_I2C_SLAVE_MQUEUE_MESSAGE_SIZE +#define MQ_QUEUE_SIZE CONFIG_I2C_SLAVE_MQUEUE_QUEUE_SIZE +#define MQ_QUEUE_NEXT(x) (((x) + 1) & (MQ_QUEUE_SIZE - 1)) + +struct mq_msg { + int len; + u8 *buf; +}; + +struct mq_queue { + struct bin_attribute bin; + struct kernfs_node *kn; + struct i2c_client *client; + + spinlock_t lock; /* spinlock for queue index handling */ + int in; + int out; + + struct mq_msg *curr; + int truncated; /* drop current if truncated */ + struct mq_msg *queue; +}; + +static bool dump_debug __read_mostly; +static int dump_debug_bus_id __read_mostly; + +#define I2C_HEX_DUMP(client, buf, len) \ + do { \ + if (dump_debug && \ + (client)->adapter->nr == dump_debug_bus_id) { \ + char dump_info[100] = {0,}; \ + snprintf(dump_info, sizeof(dump_info), \ + "bus_id:%d: ", (client)->adapter->nr); \ + print_hex_dump(KERN_ERR, dump_info, DUMP_PREFIX_NONE, \ + 16, 1, buf, len, true); \ + } \ + } while (0) + +static int i2c_slave_mqueue_callback(struct i2c_client *client, + enum i2c_slave_event event, u8 *val) +{ + struct mq_queue *mq = i2c_get_clientdata(client); + struct mq_msg *msg = mq->curr; + int ret = 0; + + switch (event) { + case I2C_SLAVE_WRITE_REQUESTED: + case I2C_SLAVE_GCALL_REQUESTED: + mq->truncated = 0; + + msg->len = 1; + msg->buf[0] = event == I2C_SLAVE_GCALL_REQUESTED ? + 0 : client->addr << 1; + break; + + case I2C_SLAVE_WRITE_RECEIVED: + if (msg->len < MQ_MSGBUF_SIZE) { + msg->buf[msg->len++] = *val; + } else { + dev_err(&client->dev, "message is truncated!\n"); + mq->truncated = 1; + ret = -EINVAL; + } + break; + + case I2C_SLAVE_STOP: + if (unlikely(mq->truncated || msg->len < 2)) + break; + + spin_lock(&mq->lock); + mq->in = MQ_QUEUE_NEXT(mq->in); + mq->curr = &mq->queue[mq->in]; + mq->curr->len = 0; + + /* Flush the oldest message */ + if (mq->out == mq->in) + mq->out = MQ_QUEUE_NEXT(mq->out); + spin_unlock(&mq->lock); + + kernfs_notify(mq->kn); + break; + + default: + *val = 0xFF; + break; + } + + return ret; +} + +static ssize_t i2c_slave_mqueue_bin_read(struct file *filp, + struct kobject *kobj, + struct bin_attribute *attr, + char *buf, loff_t pos, size_t count) +{ + struct mq_queue *mq; + struct mq_msg *msg; + unsigned long flags; + bool more = false; + ssize_t ret = 0; + + mq = dev_get_drvdata(container_of(kobj, struct device, kobj)); + + spin_lock_irqsave(&mq->lock, flags); + if (mq->out != mq->in) { + msg = &mq->queue[mq->out]; + + if (msg->len <= count) { + ret = msg->len; + memcpy(buf, msg->buf, ret); + I2C_HEX_DUMP(mq->client, buf, ret); + } else { + ret = -EOVERFLOW; /* Drop this HUGE one. */ + } + + mq->out = MQ_QUEUE_NEXT(mq->out); + if (mq->out != mq->in) + more = true; + } + spin_unlock_irqrestore(&mq->lock, flags); + + if (more) + kernfs_notify(mq->kn); + + return ret; +} + +static int i2c_slave_mqueue_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct mq_queue *mq; + int ret, i; + void *buf; + + mq = devm_kzalloc(dev, sizeof(*mq), GFP_KERNEL); + if (!mq) + return -ENOMEM; + + BUILD_BUG_ON(!is_power_of_2(MQ_QUEUE_SIZE)); + + mq->client = client; + + buf = devm_kmalloc_array(dev, MQ_QUEUE_SIZE, MQ_MSGBUF_SIZE, + GFP_KERNEL); + if (!buf) + return -ENOMEM; + + mq->queue = devm_kzalloc(dev, sizeof(*mq->queue) * MQ_QUEUE_SIZE, + GFP_KERNEL); + if (!buf) + return -ENOMEM; + + for (i = 0; i < MQ_QUEUE_SIZE; i++) + mq->queue[i].buf = buf + i * MQ_MSGBUF_SIZE; + + i2c_set_clientdata(client, mq); + + spin_lock_init(&mq->lock); + mq->curr = &mq->queue[0]; + + sysfs_bin_attr_init(&mq->bin); + mq->bin.attr.name = "slave-mqueue"; + mq->bin.attr.mode = 0400; + mq->bin.read = i2c_slave_mqueue_bin_read; + mq->bin.size = MQ_MSGBUF_SIZE * MQ_QUEUE_SIZE; + + ret = sysfs_create_bin_file(&dev->kobj, &mq->bin); + if (ret) + return ret; + + mq->kn = kernfs_find_and_get(dev->kobj.sd, mq->bin.attr.name); + if (!mq->kn) { + sysfs_remove_bin_file(&dev->kobj, &mq->bin); + return -EFAULT; + } + + ret = i2c_slave_register(client, i2c_slave_mqueue_callback); + if (ret) { + kernfs_put(mq->kn); + sysfs_remove_bin_file(&dev->kobj, &mq->bin); + return ret; + } + + return 0; +} + +static int i2c_slave_mqueue_remove(struct i2c_client *client) +{ + struct mq_queue *mq = i2c_get_clientdata(client); + + i2c_slave_unregister(client); + + kernfs_put(mq->kn); + sysfs_remove_bin_file(&client->dev.kobj, &mq->bin); + + return 0; +} + +static const struct i2c_device_id i2c_slave_mqueue_id[] = { + { "slave-mqueue", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, i2c_slave_mqueue_id); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id i2c_slave_mqueue_of_match[] = { + { .compatible = "slave-mqueue", .data = (void *)0 }, + { }, +}; +MODULE_DEVICE_TABLE(of, i2c_slave_mqueue_of_match); +#endif + +static struct i2c_driver i2c_slave_mqueue_driver = { + .driver = { + .name = "i2c-slave-mqueue", + .of_match_table = of_match_ptr(i2c_slave_mqueue_of_match), + }, + .probe = i2c_slave_mqueue_probe, + .remove = i2c_slave_mqueue_remove, + .id_table = i2c_slave_mqueue_id, +}; +module_i2c_driver(i2c_slave_mqueue_driver); + +module_param_named(dump_debug, dump_debug, bool, 0644); +MODULE_PARM_DESC(dump_debug, "debug flag for dump printing"); +module_param_named(dump_debug_bus_id, dump_debug_bus_id, int, 0644); +MODULE_PARM_DESC(dump_debug_bus_id, "bus id for dump debug printing"); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Haiyue Wang <haiyue.wang@linux.intel.com>"); +MODULE_DESCRIPTION("I2C slave mode for receiving and queuing messages"); |