summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/aspeed-g5.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g5.dtsi')
-rw-r--r--arch/arm/boot/dts/aspeed-g5.dtsi244
1 files changed, 240 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8..674746513031 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -29,6 +29,7 @@
serial3 = &uart4;
serial4 = &uart5;
serial5 = &vuart;
+ peci0 = &peci0;
};
cpus {
@@ -53,7 +54,7 @@
#size-cells = <1>;
ranges;
- fmc: flash-controller@1e620000 {
+ fmc: spi@1e620000 {
reg = < 0x1e620000 0xc4
0x20000000 0x10000000 >;
#address-cells = <1>;
@@ -65,21 +66,24 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
- spi1: flash-controller@1e630000 {
+ spi1: spi@1e630000 {
reg = < 0x1e630000 0xc4
0x30000000 0x08000000 >;
#address-cells = <1>;
@@ -90,16 +94,18 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
- spi2: flash-controller@1e631000 {
+ spi2: spi@1e631000 {
reg = < 0x1e631000 0xc4
0x38000000 0x08000000 >;
#address-cells = <1>;
@@ -110,11 +116,13 @@
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
status = "disabled";
};
};
@@ -212,6 +220,15 @@
aspeed,external-nodes = <&gfx &lhc>;
};
+
+ vga_scratch: scratch {
+ compatible = "aspeed,bmc-misc";
+ };
+
+ p2a: p2a-control {
+ compatible = "aspeed,ast2500-p2a-ctrl";
+ status = "disabled";
+ };
};
rng: hwrng@1e6e2078 {
@@ -225,6 +242,10 @@
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
reg-io-width = <4>;
+ clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
+ resets = <&syscon ASPEED_RESET_CRT1>;
+ status = "disabled";
+ interrupts = <0x19>;
};
adc: adc@1e6e9000 {
@@ -236,6 +257,16 @@
status = "disabled";
};
+ video: video@1e700000 {
+ compatible = "aspeed,ast2500-video-engine";
+ reg = <0x1e700000 0x1000>;
+ clocks = <&syscon ASPEED_CLK_GATE_VCLK>,
+ <&syscon ASPEED_CLK_GATE_ECLK>;
+ clock-names = "vclk", "eclk";
+ interrupts = <7>;
+ status = "disabled";
+ };
+
sram: sram@1e720000 {
compatible = "mmio-sram";
reg = <0x1e720000 0x9000>; // 36K
@@ -250,6 +281,13 @@
gpio-ranges = <&pinctrl 0 0 220>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ rtc: rtc@1e781000 {
+ compatible = "aspeed,ast2500-rtc";
+ reg = <0x1e781000 0x18>;
+ status = "disabled";
};
timer: timer@1e782000 {
@@ -330,8 +368,32 @@
ranges = <0x0 0x1e789000 0x1000>;
lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc";
+ compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
reg = <0x0 0x80>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x80>;
+
+ kcs1: kcs1@0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ interrupts = <8>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
+ kcs2: kcs2@0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ interrupts = <8>;
+ kcs_chan = <2>;
+ status = "disabled";
+ };
+ kcs3: kcs3@0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ interrupts = <8>;
+ kcs_chan = <3>;
+ status = "disabled";
+ };
};
lpc_host: lpc-host@80 {
@@ -343,6 +405,13 @@
#size-cells = <1>;
ranges = <0x0 0x80 0x1e0>;
+ kcs4: kcs4@0 {
+ compatible = "aspeed,ast2500-kcs-bmc";
+ interrupts = <8>;
+ kcs_chan = <4>;
+ status = "disabled";
+ };
+
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
@@ -372,11 +441,29 @@
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0xc0 0x18>;
interrupts = <8>;
+ };
+
+ sio_regs: regs {
+ compatible = "aspeed,bmc-misc";
+ };
+
+ mbox: mbox@180 {
+ compatible = "aspeed,ast2500-mbox";
+ reg = <0x180 0x5c>;
+ interrupts = <46>;
+ #mbox-cells = <1>;
status = "disabled";
};
};
};
+ peci: bus@1e78b000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e78b000 0x60>;
+ };
+
uart2: serial@1e78d000 {
compatible = "ns16550a";
reg = <0x1e78d000 0x20>;
@@ -420,6 +507,24 @@
};
};
+&peci {
+ peci0: peci-bus@0 {
+ compatible = "aspeed,ast2500-peci";
+ reg = <0x0 0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <15>;
+ clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
+ resets = <&syscon ASPEED_RESET_PECI>;
+ clock-frequency = <24000000>;
+ msg-timing = <1>;
+ addr-timing = <1>;
+ rd-sampling-point = <8>;
+ cmd-timeout-ms = <1000>;
+ status = "disabled";
+ };
+};
+
&i2c {
i2c_ic: interrupt-controller@0 {
#interrupt-cells = <1>;
@@ -1492,3 +1597,134 @@
groups = "WDTRST2";
};
};
+
+&vga_scratch {
+ dac_mux {
+ offset = <0x2c>;
+ bit-mask = <0x3>;
+ bit-shift = <16>;
+ };
+ vga0 {
+ offset = <0x50>;
+ bit-mask = <0xffffffff>;
+ bit-shift = <0>;
+ };
+ vga1 {
+ offset = <0x54>;
+ bit-mask = <0xffffffff>;
+ bit-shift = <0>;
+ };
+ vga2 {
+ offset = <0x58>;
+ bit-mask = <0xffffffff>;
+ bit-shift = <0>;
+ };
+ vga3 {
+ offset = <0x5c>;
+ bit-mask = <0xffffffff>;
+ bit-shift = <0>;
+ };
+ vga4 {
+ offset = <0x60>;
+ bit-mask = <0xffffffff>;
+ bit-shift = <0>;
+ };
+ vga5 {
+ offset = <0x64>;
+ bit-mask = <0xffffffff>;
+ bit-shift = <0>;
+ };
+ vga6 {
+ offset = <0x68>;
+ bit-mask = <0xffffffff>;
+ bit-shift = <0>;
+ };
+ vga7 {
+ offset = <0x6c>;
+ bit-mask = <0xffffffff>;
+ bit-shift = <0>;
+ };
+};
+
+&sio_regs {
+ sio_2b {
+ offset = <0xf0>;
+ bit-mask = <0xff>;
+ bit-shift = <24>;
+ };
+ sio_2a {
+ offset = <0xf0>;
+ bit-mask = <0xff>;
+ bit-shift = <16>;
+ };
+ sio_29 {
+ offset = <0xf0>;
+ bit-mask = <0xff>;
+ bit-shift = <8>;
+ };
+ sio_28 {
+ offset = <0xf0>;
+ bit-mask = <0xff>;
+ bit-shift = <0>;
+ };
+ sio_2f {
+ offset = <0xf4>;
+ bit-mask = <0xff>;
+ bit-shift = <24>;
+ };
+ sio_2e {
+ offset = <0xf4>;
+ bit-mask = <0xff>;
+ bit-shift = <16>;
+ };
+ sio_2d {
+ offset = <0xf4>;
+ bit-mask = <0xff>;
+ bit-shift = <8>;
+ };
+ sio_2c {
+ offset = <0xf4>;
+ bit-mask = <0xff>;
+ bit-shift = <0>;
+ };
+ sio_23 {
+ offset = <0xf8>;
+ bit-mask = <0xff>;
+ bit-shift = <24>;
+ };
+ sio_22 {
+ offset = <0xf8>;
+ bit-mask = <0xff>;
+ bit-shift = <16>;
+ };
+ sio_21 {
+ offset = <0xf8>;
+ bit-mask = <0xff>;
+ bit-shift = <8>;
+ };
+ sio_20 {
+ offset = <0xf8>;
+ bit-mask = <0xff>;
+ bit-shift = <0>;
+ };
+ sio_27 {
+ offset = <0xfc>;
+ bit-mask = <0xff>;
+ bit-shift = <24>;
+ };
+ sio_26 {
+ offset = <0xfc>;
+ bit-mask = <0xff>;
+ bit-shift = <16>;
+ };
+ sio_25 {
+ offset = <0xfc>;
+ bit-mask = <0xff>;
+ bit-shift = <8>;
+ };
+ sio_24 {
+ offset = <0xfc>;
+ bit-mask = <0xff>;
+ bit-shift = <0>;
+ };
+};
generated by cgit v1.2.3 (git 2.39.0) at 2025-08-08 15:52:04 +0300