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-rw-r--r--Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt2
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt2
2 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
index 8dbe47013c2b..14968b048cd3 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
@@ -12,6 +12,8 @@ Required properties:
- clock-names: Must include the following entries:
- mc: the module's clock input
- interrupts: The interrupt outputs from the controller.
+
+Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
the SWGROUP of the master.
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
index 9592717f483f..190437a0c146 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
@@ -138,7 +138,7 @@ from the corresponding HW reg.
Example for aemif, davinci nand and nor flash chip select shown below.
-memory-controller@21000A00 {
+memory-controller@21000a00 {
compatible = "ti,davinci-aemif";
#address-cells = <2>;
#size-cells = <1>;