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authorChakravarty, Souvik K <souvik.k.chakravarty@intel.com>2017-11-24 16:34:41 +0300
committerAndy Shevchenko <andriy.shevchenko@linux.intel.com>2017-11-27 14:39:11 +0300
commit9c916549c0345a054431abdc4f2d9ba48e856f80 (patch)
tree53d646306fe50b63ef3a543593156d373dcb321f /drivers
parent2448f44f31625610ddeafc9c7642da8a78d93c7b (diff)
downloadlinux-9c916549c0345a054431abdc4f2d9ba48e856f80.tar.xz
platform/x86: intel_pmc_ipc: Add read64 API
Add intel_pmc_gcr_read64() API for reading from 64-bit GCR registers. This API will be called from intel_telemetry. Update description of intel_pmc_gcr_read(). Signed-off-by: Souvik Kumar Chakravarty <souvik.k.chakravarty@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/platform/x86/intel_pmc_ipc.c33
1 files changed, 31 insertions, 2 deletions
diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c
index e03fa31446ca..e7edc8c63936 100644
--- a/drivers/platform/x86/intel_pmc_ipc.c
+++ b/drivers/platform/x86/intel_pmc_ipc.c
@@ -215,11 +215,11 @@ static inline int is_gcr_valid(u32 offset)
}
/**
- * intel_pmc_gcr_read() - Read PMC GCR register
+ * intel_pmc_gcr_read() - Read a 32-bit PMC GCR register
* @offset: offset of GCR register from GCR address base
* @data: data pointer for storing the register output
*
- * Reads the PMC GCR register of given offset.
+ * Reads the 32-bit PMC GCR register at given offset.
*
* Return: negative value on error or 0 on success.
*/
@@ -244,6 +244,35 @@ int intel_pmc_gcr_read(u32 offset, u32 *data)
EXPORT_SYMBOL_GPL(intel_pmc_gcr_read);
/**
+ * intel_pmc_gcr_read64() - Read a 64-bit PMC GCR register
+ * @offset: offset of GCR register from GCR address base
+ * @data: data pointer for storing the register output
+ *
+ * Reads the 64-bit PMC GCR register at given offset.
+ *
+ * Return: negative value on error or 0 on success.
+ */
+int intel_pmc_gcr_read64(u32 offset, u64 *data)
+{
+ int ret;
+
+ spin_lock(&ipcdev.gcr_lock);
+
+ ret = is_gcr_valid(offset);
+ if (ret < 0) {
+ spin_unlock(&ipcdev.gcr_lock);
+ return ret;
+ }
+
+ *data = readq(ipcdev.gcr_mem_base + offset);
+
+ spin_unlock(&ipcdev.gcr_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(intel_pmc_gcr_read64);
+
+/**
* intel_pmc_gcr_write() - Write PMC GCR register
* @offset: offset of GCR register from GCR address base
* @data: register update value