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authorJames Morris <jmorris@namei.org>2011-01-10 01:46:24 +0300
committerJames Morris <jmorris@namei.org>2011-01-10 01:46:24 +0300
commitd2e7ad19229f982fc1eb731827d82ceac90abfb3 (patch)
tree98a3741b4d4b27a48b3c7ea9babe331e539416a8 /drivers/spi/dw_spi_pci.c
parentd03a5d888fb688c832d470b749acc5ed38e0bc1d (diff)
parent0c21e3aaf6ae85bee804a325aa29c325209180fd (diff)
downloadlinux-d2e7ad19229f982fc1eb731827d82ceac90abfb3.tar.xz
Merge branch 'master' into next
Conflicts: security/smack/smack_lsm.c Verified and added fix by Stephen Rothwell <sfr@canb.auug.org.au> Ok'd by Casey Schaufler <casey@schaufler-ca.com> Signed-off-by: James Morris <jmorris@namei.org>
Diffstat (limited to 'drivers/spi/dw_spi_pci.c')
-rw-r--r--drivers/spi/dw_spi_pci.c20
1 files changed, 14 insertions, 6 deletions
diff --git a/drivers/spi/dw_spi_pci.c b/drivers/spi/dw_spi_pci.c
index 1f52755dc878..49ec3aa1219f 100644
--- a/drivers/spi/dw_spi_pci.c
+++ b/drivers/spi/dw_spi_pci.c
@@ -1,5 +1,5 @@
/*
- * mrst_spi_pci.c - PCI interface driver for DW SPI Core
+ * dw_spi_pci.c - PCI interface driver for DW SPI Core
*
* Copyright (c) 2009, Intel Corporation.
*
@@ -26,8 +26,8 @@
#define DRIVER_NAME "dw_spi_pci"
struct dw_spi_pci {
- struct pci_dev *pdev;
- struct dw_spi dws;
+ struct pci_dev *pdev;
+ struct dw_spi dws;
};
static int __devinit spi_pci_probe(struct pci_dev *pdev,
@@ -72,9 +72,17 @@ static int __devinit spi_pci_probe(struct pci_dev *pdev,
dws->parent_dev = &pdev->dev;
dws->bus_num = 0;
dws->num_cs = 4;
- dws->max_freq = 25000000; /* for Moorestwon */
dws->irq = pdev->irq;
- dws->fifo_len = 40; /* FIFO has 40 words buffer */
+
+ /*
+ * Specific handling for Intel MID paltforms, like dma setup,
+ * clock rate, FIFO depth.
+ */
+ if (pdev->device == 0x0800) {
+ ret = dw_spi_mid_init(dws);
+ if (ret)
+ goto err_unmap;
+ }
ret = dw_spi_add_host(dws);
if (ret)
@@ -140,7 +148,7 @@ static int spi_resume(struct pci_dev *pdev)
#endif
static const struct pci_device_id pci_ids[] __devinitdata = {
- /* Intel Moorestown platform SPI controller 0 */
+ /* Intel MID platform SPI controller 0 */
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0800) },
{},
};