diff options
| author | Adrian Hunter <adrian.hunter@intel.com> | 2014-11-04 13:42:46 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2014-11-10 14:40:53 +0300 |
| commit | e57a5f61eae7e145aeeda18ccb22576822f534bf (patch) | |
| tree | 3ac10196b0713885f85d8fae054f3e867c19c77c /drivers/mmc/host/sdhci.h | |
| parent | 0545230f1764bc639e14eea3fe944d9d16e91a92 (diff) | |
| download | linux-e57a5f61eae7e145aeeda18ccb22576822f534bf.tar.xz | |
mmc: sdhci: Add 64-bit ADMA support
Add 64-bit ADMA support including:
- add 64-bit ADMA descriptor
- add SDHCI_USE_64_BIT_DMA flag
- set upper 32-bits of DMA addresses
- ability to select 64-bit ADMA
- ability to use 64-bit ADMA sizes and alignment
- display "ADMA 64-bit" when host is added
It is assumed that a 64-bit capable device has set a 64-bit DMA mask
and *must* do 64-bit DMA. A driver has the opportunity to change
that during the first call to ->enable_dma(). Similarly
SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
implement.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci.h')
| -rw-r--r-- | drivers/mmc/host/sdhci.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 14c8b6773dbb..c2ec7fcd8a1f 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -227,6 +227,7 @@ /* 55-57 reserved */ #define SDHCI_ADMA_ADDRESS 0x58 +#define SDHCI_ADMA_ADDRESS_HI 0x5C /* 60-FB reserved */ @@ -279,6 +280,23 @@ struct sdhci_adma2_32_desc { __le32 addr; } __packed __aligned(SDHCI_ADMA2_32_ALIGN); +/* ADMA2 64-bit DMA descriptor size */ +#define SDHCI_ADMA2_64_DESC_SZ 12 + +/* ADMA2 64-bit DMA alignment */ +#define SDHCI_ADMA2_64_ALIGN 8 + +/* + * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte + * aligned. + */ +struct sdhci_adma2_64_desc { + __le16 cmd; + __le16 len; + __le32 addr_lo; + __le32 addr_hi; +} __packed __aligned(4); + #define ADMA2_TRAN_VALID 0x21 #define ADMA2_NOP_END_VALID 0x3 #define ADMA2_END 0x2 |