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authorOlof Johansson <olof@lixom.net>2021-06-17 03:36:17 +0300
committerOlof Johansson <olof@lixom.net>2021-06-17 03:36:30 +0300
commit1eb5f83ee936de6a69b2bcee95088a6e0ab7c202 (patch)
tree878a5c3dd5bd6179c86807b49aadd0c8b93d2ab3 /drivers/memory
parente73153ba0c7f6f392d6306ffeed733f9b39851ce (diff)
parent2c1bc371268862a991a6498e1dddc8971b9076b8 (diff)
downloadlinux-1eb5f83ee936de6a69b2bcee95088a6e0ab7c202.tar.xz
Merge tag 'memory-controller-drv-tegra-5.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers
Memory controller drivers for v5.14 - Tegra SoC, part two Second set of changes for Tegra SoC memory controller drivers, containing patchset from Thierry Reding: "The goal here is to avoid early identity mappings altogether and instead postpone the need for the identity mappings to when devices are attached to the SMMU. This works by making the SMMU driver coordinate with the memory controller driver on when to start enforcing SMMU translations. This makes Tegra behave in a more standard way and pushes the code to deal with the Tegra-specific programming into the NVIDIA SMMU implementation." This pulls a dependency from Will Deacon (ARM SMMU driver) and contains further ARM SMMU driver patches to resolve complex dependencies between different patchsets. The pull from Will contains only one patch ("Implement ->probe_finalize()"). Further work in Will's tree might depend on this patch, therefore patch was applied there. On the other hand, this ("Implement ->probe_finalize()") patch is also a dependency for ARM SMMU driver changes for Tegra. These changes, bringing seamless transition from the firmware framebuffer to the OS framebuffer, depend on earlier Tegra memory controller driver patches. * tag 'memory-controller-drv-tegra-5.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: (37 commits) iommu/arm-smmu: Use Tegra implementation on Tegra186 iommu/arm-smmu: tegra: Implement SID override programming iommu/arm-smmu: tegra: Detect number of instances at runtime dt-bindings: arm-smmu: Add Tegra186 compatible string memory: tegra: Delete dead debugfs checking code iommu/arm-smmu: Implement ->probe_finalize() memory: tegra: Implement SID override programming memory: tegra: Split Tegra194 data into separate file memory: tegra: Add memory client IDs to tables memory: tegra: Unify drivers memory: tegra: Only initialize reset controller if available memory: tegra: Make IRQ support opitonal memory: tegra: Parameterize interrupt handler memory: tegra: Extract setup code into callback memory: tegra: Make per-SoC setup more generic memory: tegra: Push suspend/resume into SoC drivers memory: tegra: Introduce struct tegra_mc_ops memory: tegra: Unify struct tegra_mc across SoC generations memory: tegra: Consolidate register fields memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table() ... Link: https://lore.kernel.org/r/20210614195200.21657-1-krzysztof.kozlowski@canonical.com Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/tegra/Kconfig18
-rw-r--r--drivers/memory/tegra/Makefile6
-rw-r--r--drivers/memory/tegra/mc.c321
-rw-r--r--drivers/memory/tegra/mc.h25
-rw-r--r--drivers/memory/tegra/tegra114.c1245
-rw-r--r--drivers/memory/tegra/tegra124-emc.c8
-rw-r--r--drivers/memory/tegra/tegra124.c1306
-rw-r--r--drivers/memory/tegra/tegra186.c1679
-rw-r--r--drivers/memory/tegra/tegra194.c1351
-rw-r--r--drivers/memory/tegra/tegra20-emc.c52
-rw-r--r--drivers/memory/tegra/tegra20.c110
-rw-r--r--drivers/memory/tegra/tegra210-emc-core.c4
-rw-r--r--drivers/memory/tegra/tegra210.c1433
-rw-r--r--drivers/memory/tegra/tegra30-emc.c56
-rw-r--r--drivers/memory/tegra/tegra30.c1292
15 files changed, 5027 insertions, 3879 deletions
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index a70967a56e52..f9bae36c03a3 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -2,16 +2,18 @@
config TEGRA_MC
bool "NVIDIA Tegra Memory Controller support"
default y
- depends on ARCH_TEGRA
+ depends on ARCH_TEGRA || (COMPILE_TEST && COMMON_CLK)
select INTERCONNECT
help
This driver supports the Memory Controller (MC) hardware found on
NVIDIA Tegra SoCs.
+if TEGRA_MC
+
config TEGRA20_EMC
tristate "NVIDIA Tegra20 External Memory Controller driver"
default y
- depends on TEGRA_MC && ARCH_TEGRA_2x_SOC
+ depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
select DEVFREQ_GOV_SIMPLE_ONDEMAND
select PM_DEVFREQ
help
@@ -23,7 +25,7 @@ config TEGRA20_EMC
config TEGRA30_EMC
tristate "NVIDIA Tegra30 External Memory Controller driver"
default y
- depends on TEGRA_MC && ARCH_TEGRA_3x_SOC
+ depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
select PM_OPP
help
This driver is for the External Memory Controller (EMC) found on
@@ -34,8 +36,8 @@ config TEGRA30_EMC
config TEGRA124_EMC
tristate "NVIDIA Tegra124 External Memory Controller driver"
default y
- depends on TEGRA_MC && ARCH_TEGRA_124_SOC
- select TEGRA124_CLK_EMC
+ depends on ARCH_TEGRA_124_SOC || COMPILE_TEST
+ select TEGRA124_CLK_EMC if ARCH_TEGRA
select PM_OPP
help
This driver is for the External Memory Controller (EMC) found on
@@ -45,14 +47,16 @@ config TEGRA124_EMC
config TEGRA210_EMC_TABLE
bool
- depends on ARCH_TEGRA_210_SOC
+ depends on ARCH_TEGRA_210_SOC || COMPILE_TEST
config TEGRA210_EMC
tristate "NVIDIA Tegra210 External Memory Controller driver"
- depends on TEGRA_MC && ARCH_TEGRA_210_SOC
+ depends on ARCH_TEGRA_210_SOC || COMPILE_TEST
select TEGRA210_EMC_TABLE
help
This driver is for the External Memory Controller (EMC) found on
Tegra210 chips. The EMC controls the external DRAM on the board.
This driver is required to change memory timings / clock rate for
external memory.
+
+endif
diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile
index 6c1a2ecc6628..c992e87782d2 100644
--- a/drivers/memory/tegra/Makefile
+++ b/drivers/memory/tegra/Makefile
@@ -7,6 +7,8 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
+tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
+tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
@@ -15,7 +17,7 @@ obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o
obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
-obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o tegra186-emc.o
-obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra186-emc.o
+obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o
+obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o
tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index e58c3e5baea0..3c5aae7abf35 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -39,7 +39,13 @@ static const struct of_device_id tegra_mc_of_match[] = {
#ifdef CONFIG_ARCH_TEGRA_210_SOC
{ .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
#endif
- { }
+#ifdef CONFIG_ARCH_TEGRA_186_SOC
+ { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
+#endif
+#ifdef CONFIG_ARCH_TEGRA_194_SOC
+ { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
+#endif
+ { /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
@@ -91,6 +97,15 @@ struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get);
+int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
+{
+ if (mc->soc->ops && mc->soc->ops->probe_device)
+ return mc->soc->ops->probe_device(mc, dev);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_mc_probe_device);
+
static int tegra_mc_block_dma_common(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
@@ -299,38 +314,6 @@ static int tegra_mc_reset_setup(struct tegra_mc *mc)
return 0;
}
-static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
-{
- unsigned long long tick;
- unsigned int i;
- u32 value;
-
- /* compute the number of MC clock cycles per tick */
- tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
- do_div(tick, NSEC_PER_SEC);
-
- value = mc_readl(mc, MC_EMEM_ARB_CFG);
- value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
- value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
- mc_writel(mc, value, MC_EMEM_ARB_CFG);
-
- /* write latency allowance defaults */
- for (i = 0; i < mc->soc->num_clients; i++) {
- const struct tegra_mc_la *la = &mc->soc->clients[i].la;
- u32 value;
-
- value = mc_readl(mc, la->reg);
- value &= ~(la->mask << la->shift);
- value |= (la->def & la->mask) << la->shift;
- mc_writel(mc, value, la->reg);
- }
-
- /* latch new values */
- mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
-
- return 0;
-}
-
int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
{
unsigned int i;
@@ -368,6 +351,43 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
}
EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count);
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_114_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_124_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_132_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_210_SOC)
+static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
+{
+ unsigned long long tick;
+ unsigned int i;
+ u32 value;
+
+ /* compute the number of MC clock cycles per tick */
+ tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
+ do_div(tick, NSEC_PER_SEC);
+
+ value = mc_readl(mc, MC_EMEM_ARB_CFG);
+ value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
+ value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
+ mc_writel(mc, value, MC_EMEM_ARB_CFG);
+
+ /* write latency allowance defaults */
+ for (i = 0; i < mc->soc->num_clients; i++) {
+ const struct tegra_mc_client *client = &mc->soc->clients[i];
+ u32 value;
+
+ value = mc_readl(mc, client->regs.la.reg);
+ value &= ~(client->regs.la.mask << client->regs.la.shift);
+ value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift;
+ mc_writel(mc, value, client->regs.la.reg);
+ }
+
+ /* latch new values */
+ mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
+
+ return 0;
+}
+
static int load_one_timing(struct tegra_mc *mc,
struct tegra_mc_timing *timing,
struct device_node *node)
@@ -459,27 +479,35 @@ static int tegra_mc_setup_timings(struct tegra_mc *mc)
return 0;
}
-static const char *const status_names[32] = {
- [ 1] = "External interrupt",
- [ 6] = "EMEM address decode error",
- [ 7] = "GART page fault",
- [ 8] = "Security violation",
- [ 9] = "EMEM arbitration error",
- [10] = "Page fault",
- [11] = "Invalid APB ASID update",
- [12] = "VPR violation",
- [13] = "Secure carveout violation",
- [16] = "MTS carveout violation",
-};
+int tegra30_mc_probe(struct tegra_mc *mc)
+{
+ int err;
-static const char *const error_names[8] = {
- [2] = "EMEM decode error",
- [3] = "TrustZone violation",
- [4] = "Carveout violation",
- [6] = "SMMU translation error",
-};
+ mc->clk = devm_clk_get_optional(mc->dev, "mc");
+ if (IS_ERR(mc->clk)) {
+ dev_err(mc->dev, "failed to get MC clock: %ld\n", PTR_ERR(mc->clk));
+ return PTR_ERR(mc->clk);
+ }
+
+ /* ensure that debug features are disabled */
+ mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
+
+ err = tegra_mc_setup_latency_allowance(mc);
+ if (err < 0) {
+ dev_err(mc->dev, "failed to setup latency allowance: %d\n", err);
+ return err;
+ }
-static irqreturn_t tegra_mc_irq(int irq, void *data)
+ err = tegra_mc_setup_timings(mc);
+ if (err < 0) {
+ dev_err(mc->dev, "failed to setup timings: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
{
struct tegra_mc *mc = data;
unsigned long status;
@@ -491,7 +519,7 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
return IRQ_NONE;
for_each_set_bit(bit, &status, 32) {
- const char *error = status_names[bit] ?: "unknown";
+ const char *error = tegra_mc_status_names[bit] ?: "unknown";
const char *client = "unknown", *desc;
const char *direction, *secure;
phys_addr_t addr = 0;
@@ -531,7 +559,7 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
type = (value & MC_ERR_STATUS_TYPE_MASK) >>
MC_ERR_STATUS_TYPE_SHIFT;
- desc = error_names[type];
+ desc = tegra_mc_error_names[type];
switch (value & MC_ERR_STATUS_TYPE_MASK) {
case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
@@ -576,78 +604,31 @@ static irqreturn_t tegra_mc_irq(int irq, void *data)
return IRQ_HANDLED;
}
-static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
-{
- struct tegra_mc *mc = data;
- unsigned long status;
- unsigned int bit;
-
- /* mask all interrupts to avoid flooding */
- status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
- if (!status)
- return IRQ_NONE;
-
- for_each_set_bit(bit, &status, 32) {
- const char *direction = "read", *secure = "";
- const char *error = status_names[bit];
- const char *client, *desc;
- phys_addr_t addr;
- u32 value, reg;
- u8 id, type;
-
- switch (BIT(bit)) {
- case MC_INT_DECERR_EMEM:
- reg = MC_DECERR_EMEM_OTHERS_STATUS;
- value = mc_readl(mc, reg);
-
- id = value & mc->soc->client_id_mask;
- desc = error_names[2];
-
- if (value & BIT(31))
- direction = "write";
- break;
-
- case MC_INT_INVALID_GART_PAGE:
- reg = MC_GART_ERROR_REQ;
- value = mc_readl(mc, reg);
-
- id = (value >> 1) & mc->soc->client_id_mask;
- desc = error_names[2];
-
- if (value & BIT(0))
- direction = "write";
- break;
-
- case MC_INT_SECURITY_VIOLATION:
- reg = MC_SECURITY_VIOLATION_STATUS;
- value = mc_readl(mc, reg);
-
- id = value & mc->soc->client_id_mask;
- type = (value & BIT(30)) ? 4 : 3;
- desc = error_names[type];
- secure = "secure ";
-
- if (value & BIT(31))
- direction = "write";
- break;
-
- default:
- continue;
- }
-
- client = mc->soc->clients[id].name;
- addr = mc_readl(mc, reg + sizeof(u32));
-
- dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
- client, secure, direction, &addr, error,
- desc);
- }
+const struct tegra_mc_ops tegra30_mc_ops = {
+ .probe = tegra30_mc_probe,
+ .handle_irq = tegra30_mc_handle_irq,
+};
+#endif
- /* clear interrupts */
- mc_writel(mc, status, MC_INTSTATUS);
+const char *const tegra_mc_status_names[32] = {
+ [ 1] = "External interrupt",
+ [ 6] = "EMEM address decode error",
+ [ 7] = "GART page fault",
+ [ 8] = "Security violation",
+ [ 9] = "EMEM arbitration error",
+ [10] = "Page fault",
+ [11] = "Invalid APB ASID update",
+ [12] = "VPR violation",
+ [13] = "Secure carveout violation",
+ [16] = "MTS carveout violation",
+};
- return IRQ_HANDLED;
-}
+const char *const tegra_mc_error_names[8] = {
+ [2] = "EMEM decode error",
+ [3] = "TrustZone violation",
+ [4] = "Carveout violation",
+ [6] = "SMMU translation error",
+};
/*
* Memory Controller (MC) has few Memory Clients that are issuing memory
@@ -748,7 +729,6 @@ static int tegra_mc_probe(struct platform_device *pdev)
{
struct resource *res;
struct tegra_mc *mc;
- void *isr;
u64 mask;
int err;
@@ -777,70 +757,38 @@ static int tegra_mc_probe(struct platform_device *pdev)
if (IS_ERR(mc->regs))
return PTR_ERR(mc->regs);
- mc->clk = devm_clk_get(&pdev->dev, "mc");
- if (IS_ERR(mc->clk)) {
- dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
- PTR_ERR(mc->clk));
- return PTR_ERR(mc->clk);
+ mc->debugfs.root = debugfs_create_dir("mc", NULL);
+
+ if (mc->soc->ops && mc->soc->ops->probe) {
+ err = mc->soc->ops->probe(mc);
+ if (err < 0)
+ return err;
}
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- if (mc->soc == &tegra20_mc_soc) {
- isr = tegra20_mc_irq;
- } else
-#endif
- {
- /* ensure that debug features are disabled */
- mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
+ if (mc->soc->ops && mc->soc->ops->handle_irq) {
+ mc->irq = platform_get_irq(pdev, 0);
+ if (mc->irq < 0)
+ return mc->irq;
- err = tegra_mc_setup_latency_allowance(mc);
- if (err < 0) {
- dev_err(&pdev->dev,
- "failed to setup latency allowance: %d\n",
- err);
- return err;
- }
+ WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
- isr = tegra_mc_irq;
+ mc_writel(mc, mc->soc->intmask, MC_INTMASK);
- err = tegra_mc_setup_timings(mc);
+ err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0,
+ dev_name(&pdev->dev), mc);
if (err < 0) {
- dev_err(&pdev->dev, "failed to setup timings: %d\n",
+ dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
err);
return err;
}
}
- mc->irq = platform_get_irq(pdev, 0);
- if (mc->irq < 0)
- return mc->irq;
-
- WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
-
- mc_writel(mc, mc->soc->intmask, MC_INTMASK);
-
- err = devm_request_irq(&pdev->dev, mc->irq, isr, 0,
- dev_name(&pdev->dev), mc);
- if (err < 0) {
- dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
- err);
- return err;
- }
-
- mc->debugfs.root = debugfs_create_dir("mc", NULL);
-
- if (mc->soc->init) {
- err = mc->soc->init(mc);
+ if (mc->soc->reset_ops) {
+ err = tegra_mc_reset_setup(mc);
if (err < 0)
- dev_err(&pdev->dev, "failed to initialize SoC driver: %d\n",
- err);
+ dev_err(&pdev->dev, "failed to register reset controller: %d\n", err);
}
- err = tegra_mc_reset_setup(mc);
- if (err < 0)
- dev_err(&pdev->dev, "failed to register reset controller: %d\n",
- err);
-
err = tegra_mc_interconnect_setup(mc);
if (err < 0)
dev_err(&pdev->dev, "failed to initialize interconnect: %d\n",
@@ -867,37 +815,28 @@ static int tegra_mc_probe(struct platform_device *pdev)
return 0;
}
-static int tegra_mc_suspend(struct device *dev)
+static int __maybe_unused tegra_mc_suspend(struct device *dev)
{
struct tegra_mc *mc = dev_get_drvdata(dev);
- int err;
- if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
- err = tegra_gart_suspend(mc->gart);
- if (err)
- return err;
- }
+ if (mc->soc->ops && mc->soc->ops->suspend)
+ return mc->soc->ops->suspend(mc);
return 0;
}
-static int tegra_mc_resume(struct device *dev)
+static int __maybe_unused tegra_mc_resume(struct device *dev)
{
struct tegra_mc *mc = dev_get_drvdata(dev);
- int err;
- if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
- err = tegra_gart_resume(mc->gart);
- if (err)
- return err;
- }
+ if (mc->soc->ops && mc->soc->ops->resume)
+ return mc->soc->ops->resume(mc);
return 0;
}
static const struct dev_pm_ops tegra_mc_pm_ops = {
- .suspend = tegra_mc_suspend,
- .resume = tegra_mc_resume,
+ SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume)
};
static struct platform_driver tegra_mc_driver = {
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index 1ee34f0da4f7..1e492989c363 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -129,6 +129,31 @@ extern const struct tegra_mc_soc tegra132_mc_soc;
extern const struct tegra_mc_soc tegra210_mc_soc;
#endif
+#ifdef CONFIG_ARCH_TEGRA_186_SOC
+extern const struct tegra_mc_soc tegra186_mc_soc;
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_194_SOC
+extern const struct tegra_mc_soc tegra194_mc_soc;
+#endif
+
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_114_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_124_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_132_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_210_SOC)
+int tegra30_mc_probe(struct tegra_mc *mc);
+extern const struct tegra_mc_ops tegra30_mc_ops;
+#endif
+
+#if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
+ defined(CONFIG_ARCH_TEGRA_194_SOC)
+extern const struct tegra_mc_ops tegra186_mc_ops;
+#endif
+
+extern const char * const tegra_mc_status_names[32];
+extern const char * const tegra_mc_error_names[8];
+
/*
* These IDs are for internal use of Tegra ICC drivers. The ID numbers are
* chosen such that they don't conflict with the device-tree ICC node IDs.
diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c
index ed376ba2d2fe..41350570c815 100644
--- a/drivers/memory/tegra/tegra114.c
+++ b/drivers/memory/tegra/tegra114.c
@@ -15,883 +15,1013 @@ static const struct tegra_mc_client tegra114_mc_clients[] = {
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
- .la = {
- .reg = 0x34c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0,
+ .regs = {
+ .la = {
+ .reg = 0x34c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0,
+ },
},
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 1,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 2,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 3,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 4,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 5,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 6,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x09,
.name = "eppup",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x228,
- .bit = 9,
- },
- .la = {
- .reg = 0x300,
- .shift = 0,
- .mask = 0xff,
- .def = 0x33,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x300,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x33,
+ },
},
}, {
.id = 0x0a,
.name = "g2pr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 10,
- },
- .la = {
- .reg = 0x308,
- .shift = 0,
- .mask = 0xff,
- .def = 0x09,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x308,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x09,
+ },
},
}, {
.id = 0x0b,
.name = "g2sr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 11,
- },
- .la = {
- .reg = 0x308,
- .shift = 16,
- .mask = 0xff,
- .def = 0x09,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x308,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x09,
+ },
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x228,
- .bit = 15,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 16,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x68,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x68,
+ },
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 17,
- },
- .la = {
- .reg = 0x2fc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x68,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2fc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x68,
+ },
},
}, {
.id = 0x12,
.name = "fdcdrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 18,
- },
- .la = {
- .reg = 0x334,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x334,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x13,
.name = "fdcdrd2",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 19,
- },
- .la = {
- .reg = 0x33c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x33c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x14,
.name = "g2dr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 20,
- },
- .la = {
- .reg = 0x30c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x30c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x228,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 22,
- },
- .la = {
- .reg = 0x310,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 23,
- },
- .la = {
- .reg = 0x310,
- .shift = 16,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x18,
.name = "idxsrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 24,
- },
- .la = {
- .reg = 0x334,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0b,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x334,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0b,
+ },
},
}, {
.id = 0x1c,
.name = "msencsrd",
.swgroup = TEGRA_SWGROUP_MSENC,
- .smmu = {
- .reg = 0x228,
- .bit = 28,
- },
- .la = {
- .reg = 0x328,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 29,
- },
- .la = {
- .reg = 0x344,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 30,
- },
- .la = {
- .reg = 0x344,
- .shift = 16,
- .mask = 0xff,
- .def = 0xe8,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xe8,
+ },
},
}, {
.id = 0x20,
.name = "texl2srd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 0,
- },
- .la = {
- .reg = 0x338,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x338,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 2,
- },
- .la = {
- .reg = 0x354,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 3,
- },
- .la = {
- .reg = 0x354,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 4,
- },
- .la = {
- .reg = 0x358,
- .shift = 0,
- .mask = 0xff,
- .def = 0xb8,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xb8,
+ },
},
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 5,
- },
- .la = {
- .reg = 0x358,
- .shift = 16,
- .mask = 0xff,
- .def = 0xee,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xee,
+ },
},
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x28,
.name = "eppu",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 8,
- },
- .la = {
- .reg = 0x300,
- .shift = 16,
- .mask = 0xff,
- .def = 0x33,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 8,
+ },
+ .la = {
+ .reg = 0x300,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x33,
+ },
},
}, {
.id = 0x29,
.name = "eppv",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 9,
- },
- .la = {
- .reg = 0x304,
- .shift = 0,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x304,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
}, {
.id = 0x2a,
.name = "eppy",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 10,
- },
- .la = {
- .reg = 0x304,
- .shift = 16,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x304,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
}, {
.id = 0x2b,
.name = "msencswr",
.swgroup = TEGRA_SWGROUP_MSENC,
- .smmu = {
- .reg = 0x22c,
- .bit = 11,
- },
- .la = {
- .reg = 0x328,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x2c,
.name = "viwsb",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 12,
- },
- .la = {
- .reg = 0x364,
- .shift = 0,
- .mask = 0xff,
- .def = 0x47,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x364,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x47,
+ },
},
}, {
.id = 0x2d,
.name = "viwu",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 13,
- },
- .la = {
- .reg = 0x368,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x368,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x2e,
.name = "viwv",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 14,
- },
- .la = {
- .reg = 0x368,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x368,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x2f,
.name = "viwy",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 15,
- },
- .la = {
- .reg = 0x36c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x47,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x36c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x47,
+ },
},
}, {
.id = 0x30,
.name = "g2dw",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x22c,
- .bit = 16,
- },
- .la = {
- .reg = 0x30c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x9,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x30c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x9,
+ },
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x22c,
- .bit = 18,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
}, {
.id = 0x33,
.name = "fdcdwr",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 19,
- },
- .la = {
- .reg = 0x338,
- .shift = 16,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x338,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x34,
.name = "fdcdwr2",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 20,
- },
- .la = {
- .reg = 0x340,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x340,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x22c,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x22c,
- .bit = 22,
- },
- .la = {
- .reg = 0x314,
- .shift = 0,
- .mask = 0xff,
- .def = 0x25,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x314,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x25,
+ },
},
}, {
.id = 0x37,
.name = "ispw",
.swgroup = TEGRA_SWGROUP_ISP,
- .smmu = {
- .reg = 0x22c,
- .bit = 23,
- },
- .la = {
- .reg = 0x31c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x31c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 27,
- },
- .la = {
- .reg = 0x348,
- .shift = 0,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 28,
- },
- .la = {
- .reg = 0x348,
- .shift = 16,
- .mask = 0xff,
- .def = 0xe8,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xe8,
+ },
},
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 30,
- },
- .la = {
- .reg = 0x35c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 31,
- },
- .la = {
- .reg = 0x35c,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 0,
- },
- .la = {
- .reg = 0x360,
- .shift = 0,
- .mask = 0xff,
- .def = 0x89,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x89,
+ },
},
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 1,
- },
- .la = {
- .reg = 0x360,
- .shift = 16,
- .mask = 0xff,
- .def = 0x59,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x59,
+ },
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 10,
- },
- .la = {
- .reg = 0x37c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 11,
- },
- .la = {
- .reg = 0x37c,
- .shift = 16,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 12,
- },
- .la = {
- .reg = 0x380,
- .shift = 0,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 13,
- },
- .la = {
- .reg = 0x380,
- .shift = 16,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x4e,
.name = "fdcdwr3",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x230,
- .bit = 14,
- },
- .la = {
- .reg = 0x388,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x4f,
.name = "fdcdrd3",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x230,
- .bit = 15,
- },
- .la = {
- .reg = 0x384,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x384,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x50,
.name = "fdcwr4",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x230,
- .bit = 16,
- },
- .la = {
- .reg = 0x388,
- .shift = 16,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x51,
.name = "fdcrd4",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x230,
- .bit = 17,
- },
- .la = {
- .reg = 0x384,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x384,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x52,
.name = "emucifr",
.swgroup = TEGRA_SWGROUP_EMUCIF,
- .la = {
- .reg = 0x38c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x38c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x53,
.name = "emucifw",
.swgroup = TEGRA_SWGROUP_EMUCIF,
- .la = {
- .reg = 0x38c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .la = {
+ .reg = 0x38c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 20,
- },
- .la = {
- .reg = 0x390,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 21,
- },
- .la = {
- .reg = 0x390,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
},
};
@@ -983,4 +1113,5 @@ const struct tegra_mc_soc tegra114_mc_soc = {
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra114_mc_resets,
.num_resets = ARRAY_SIZE(tegra114_mc_resets),
+ .ops = &tegra30_mc_ops,
};
diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c
index 5699d909abc2..908f8d5392b2 100644
--- a/drivers/memory/tegra/tegra124-emc.c
+++ b/drivers/memory/tegra/tegra124-emc.c
@@ -272,8 +272,8 @@
#define EMC_PUTERM_ADJ 0x574
#define DRAM_DEV_SEL_ALL 0
-#define DRAM_DEV_SEL_0 (2 << 30)
-#define DRAM_DEV_SEL_1 (1 << 30)
+#define DRAM_DEV_SEL_0 BIT(31)
+#define DRAM_DEV_SEL_1 BIT(30)
#define EMC_CFG_POWER_FEATURES_MASK \
(EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
@@ -1269,10 +1269,6 @@ static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
- if (!emc->debugfs.root) {
- dev_err(dev, "failed to create debugfs directory\n");
- return;
- }
debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
&tegra_emc_debug_available_rates_fops);
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 459211f50c08..d780a84241fe 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -16,921 +16,1055 @@ static const struct tegra_mc_client tegra124_mc_clients[] = {
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
- .la = {
- .reg = 0x34c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0,
+ .regs = {
+ .la = {
+ .reg = 0x34c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0,
+ },
},
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 1,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0xc2,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xc2,
+ },
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 2,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 0,
- .mask = 0xff,
- .def = 0xc6,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xc6,
+ },
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 3,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 4,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 5,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 6,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x228,
- .bit = 14,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x228,
- .bit = 15,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 16,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 17,
- },
- .la = {
- .reg = 0x2fc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2fc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x228,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 0,
- .mask = 0xff,
- .def = 0x24,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x24,
+ },
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 22,
- },
- .la = {
- .reg = 0x310,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 23,
- },
- .la = {
- .reg = 0x310,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x1c,
.name = "msencsrd",
.swgroup = TEGRA_SWGROUP_MSENC,
- .smmu = {
- .reg = 0x228,
- .bit = 28,
- },
- .la = {
- .reg = 0x328,
- .shift = 0,
- .mask = 0xff,
- .def = 0x23,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x23,
+ },
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 29,
- },
- .la = {
- .reg = 0x344,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 30,
- },
- .la = {
- .reg = 0x344,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x228,
- .bit = 31,
- },
- .la = {
- .reg = 0x350,
- .shift = 0,
- .mask = 0xff,
- .def = 0x65,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x65,
+ },
},
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 2,
- },
- .la = {
- .reg = 0x354,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4f,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4f,
+ },
},
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 3,
- },
- .la = {
- .reg = 0x354,
- .shift = 16,
- .mask = 0xff,
- .def = 0x3d,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x3d,
+ },
},
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 4,
- },
- .la = {
- .reg = 0x358,
- .shift = 0,
- .mask = 0xff,
- .def = 0x66,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x66,
+ },
},
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 5,
- },
- .la = {
- .reg = 0x358,
- .shift = 16,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x2b,
.name = "msencswr",
.swgroup = TEGRA_SWGROUP_MSENC,
- .smmu = {
- .reg = 0x22c,
- .bit = 11,
- },
- .la = {
- .reg = 0x328,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x22c,
- .bit = 17,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x22c,
- .bit = 18,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x22c,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x22c,
- .bit = 22,
- },
- .la = {
- .reg = 0x314,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x314,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 27,
- },
- .la = {
- .reg = 0x348,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 28,
- },
- .la = {
- .reg = 0x348,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x22c,
- .bit = 29,
- },
- .la = {
- .reg = 0x350,
- .shift = 16,
- .mask = 0xff,
- .def = 0x65,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x65,
+ },
},
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 30,
- },
- .la = {
- .reg = 0x35c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 31,
- },
- .la = {
- .reg = 0x35c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 0,
- },
- .la = {
- .reg = 0x360,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 1,
- },
- .la = {
- .reg = 0x360,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x44,
.name = "ispra",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 4,
- },
- .la = {
- .reg = 0x370,
- .shift = 0,
- .mask = 0xff,
- .def = 0x18,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x370,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x18,
+ },
},
}, {
.id = 0x46,
.name = "ispwa",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 6,
- },
- .la = {
- .reg = 0x374,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x374,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x47,
.name = "ispwb",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 7,
- },
- .la = {
- .reg = 0x374,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x374,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 10,
- },
- .la = {
- .reg = 0x37c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x39,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x39,
+ },
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 11,
- },
- .la = {
- .reg = 0x37c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 12,
- },
- .la = {
- .reg = 0x380,
- .shift = 0,
- .mask = 0xff,
- .def = 0x39,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x39,
+ },
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 13,
- },
- .la = {
- .reg = 0x380,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4e,
.name = "isprab",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 14,
- },
- .la = {
- .reg = 0x384,
- .shift = 0,
- .mask = 0xff,
- .def = 0x18,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x384,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x18,
+ },
},
}, {
.id = 0x50,
.name = "ispwab",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 16,
- },
- .la = {
- .reg = 0x388,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x51,
.name = "ispwbb",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 17,
- },
- .la = {
- .reg = 0x388,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 20,
- },
- .la = {
- .reg = 0x390,
- .shift = 0,
- .mask = 0xff,
- .def = 0x9b,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x9b,
+ },
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 21,
- },
- .la = {
- .reg = 0x390,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x56,
.name = "a9avpscr",
.swgroup = TEGRA_SWGROUP_A9AVP,
- .smmu = {
- .reg = 0x230,
- .bit = 22,
- },
- .la = {
- .reg = 0x3a4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x3a4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x57,
.name = "a9avpscw",
.swgroup = TEGRA_SWGROUP_A9AVP,
- .smmu = {
- .reg = 0x230,
- .bit = 23,
- },
- .la = {
- .reg = 0x3a4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x3a4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x58,
.name = "gpusrd",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0x230,
- .bit = 24,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0x230,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x59,
.name = "gpuswr",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0x230,
- .bit = 25,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0x230,
+ .bit = 25,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x5a,
.name = "displayt",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x230,
- .bit = 26,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x60,
.name = "sdmmcra",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
- .smmu = {
- .reg = 0x234,
- .bit = 0,
- },
- .la = {
- .reg = 0x3b8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x3b8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x61,
.name = "sdmmcraa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
- .smmu = {
- .reg = 0x234,
- .bit = 1,
- },
- .la = {
- .reg = 0x3bc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x3bc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x62,
.name = "sdmmcr",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
- .smmu = {
- .reg = 0x234,
- .bit = 2,
- },
- .la = {
- .reg = 0x3c0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x3c0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x63,
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.name = "sdmmcrab",
- .smmu = {
- .reg = 0x234,
- .bit = 3,
- },
- .la = {
- .reg = 0x3c4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x3c4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x64,
.name = "sdmmcwa",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
- .smmu = {
- .reg = 0x234,
- .bit = 4,
- },
- .la = {
- .reg = 0x3b8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x3b8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x65,
.name = "sdmmcwaa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
- .smmu = {
- .reg = 0x234,
- .bit = 5,
- },
- .la = {
- .reg = 0x3bc,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x3bc,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x66,
.name = "sdmmcw",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
- .smmu = {
- .reg = 0x234,
- .bit = 6,
- },
- .la = {
- .reg = 0x3c0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x3c0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x67,
.name = "sdmmcwab",
.swgroup = TEGRA_SWGROUP_SDMMC4A,
- .smmu = {
- .reg = 0x234,
- .bit = 7,
- },
- .la = {
- .reg = 0x3c4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x3c4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x6c,
.name = "vicsrd",
.swgroup = TEGRA_SWGROUP_VIC,
- .smmu = {
- .reg = 0x234,
- .bit = 12,
- },
- .la = {
- .reg = 0x394,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x394,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x6d,
.name = "vicswr",
.swgroup = TEGRA_SWGROUP_VIC,
- .smmu = {
- .reg = 0x234,
- .bit = 13,
- },
- .la = {
- .reg = 0x394,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x394,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x72,
.name = "viw",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x234,
- .bit = 18,
- },
- .la = {
- .reg = 0x398,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x398,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x73,
.name = "displayd",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x234,
- .bit = 19,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
},
};
@@ -1140,6 +1274,7 @@ const struct tegra_mc_soc tegra124_mc_soc = {
.resets = tegra124_mc_resets,
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
.icc_ops = &tegra124_mc_icc_ops,
+ .ops = &tegra30_mc_ops,
};
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
@@ -1171,5 +1306,6 @@ const struct tegra_mc_soc tegra132_mc_soc = {
.resets = tegra124_mc_resets,
.num_resets = ARRAY_SIZE(tegra124_mc_resets),
.icc_ops = &tegra124_mc_icc_ops,
+ .ops = &tegra30_mc_ops,
};
#endif /* CONFIG_ARCH_TEGRA_132_SOC */
diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index e25c954dde2e..e65eac5764d4 100644
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -1,1605 +1,878 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/io.h>
+#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <soc/tegra/mc.h>
+
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
#include <dt-bindings/memory/tegra186-mc.h>
#endif
-#if defined(CONFIG_ARCH_TEGRA_194_SOC)
-#include <dt-bindings/memory/tegra194-mc.h>
-#endif
-
-struct tegra186_mc_client {
- const char *name;
- unsigned int sid;
- struct {
- unsigned int override;
- unsigned int security;
- } regs;
-};
-
-struct tegra186_mc_soc {
- const struct tegra186_mc_client *clients;
- unsigned int num_clients;
-};
-
-struct tegra186_mc {
- struct device *dev;
- void __iomem *regs;
-
- const struct tegra186_mc_soc *soc;
-};
+#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
+#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
+#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
-static void tegra186_mc_program_sid(struct tegra186_mc *mc)
+static void tegra186_mc_program_sid(struct tegra_mc *mc)
{
unsigned int i;
for (i = 0; i < mc->soc->num_clients; i++) {
- const struct tegra186_mc_client *client = &mc->soc->clients[i];
+ const struct tegra_mc_client *client = &mc->soc->clients[i];
u32 override, security;
- override = readl(mc->regs + client->regs.override);
- security = readl(mc->regs + client->regs.security);
+ override = readl(mc->regs + client->regs.sid.override);
+ security = readl(mc->regs + client->regs.sid.security);
dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
client->name, override, security);
dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid,
client->name);
- writel(client->sid, mc->regs + client->regs.override);
+ writel(client->sid, mc->regs + client->regs.sid.override);
- override = readl(mc->regs + client->regs.override);
- security = readl(mc->regs + client->regs.security);
+ override = readl(mc->regs + client->regs.sid.override);
+ security = readl(mc->regs + client->regs.sid.security);
dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
client->name, override, security);
}
}
+static int tegra186_mc_probe(struct tegra_mc *mc)
+{
+ int err;
+
+ err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
+ if (err < 0)
+ return err;
+
+ tegra186_mc_program_sid(mc);
+
+ return 0;
+}
+
+static void tegra186_mc_remove(struct tegra_mc *mc)
+{
+ of_platform_depopulate(mc->dev);
+}
+
+static int tegra186_mc_resume(struct tegra_mc *mc)
+{
+ tegra186_mc_program_sid(mc);
+
+ return 0;
+}
+
+static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
+ const struct tegra_mc_client *client,
+ unsigned int sid)
+{
+ u32 value, old;
+
+ value = readl(mc->regs + client->regs.sid.security);
+ if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
+ /*
+ * If the secure firmware has locked this down the override
+ * for this memory client, there's nothing we can do here.
+ */
+ if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
+ return;
+
+ /*
+ * Otherwise, try to set the override itself. Typically the
+ * secure firmware will never have set this configuration.
+ * Instead, it will either have disabled write access to
+ * this field, or it will already have set an explicit
+ * override itself.
+ */
+ WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
+
+ value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
+ writel(value, mc->regs + client->regs.sid.security);
+ }
+
+ value = readl(mc->regs + client->regs.sid.override);
+ old = value & MC_SID_STREAMID_OVERRIDE_MASK;
+
+ if (old != sid) {
+ dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
+ client->name, sid);
+ writel(sid, mc->regs + client->regs.sid.override);
+ }
+}
+
+static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
+{
+#if IS_ENABLED(CONFIG_IOMMU_API)
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+ struct of_phandle_args args;
+ unsigned int i, index = 0;
+
+ while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
+ index, &args)) {
+ if (args.np == mc->dev->of_node && args.args_count != 0) {
+ for (i = 0; i < mc->soc->num_clients; i++) {
+ const struct tegra_mc_client *client = &mc->soc->clients[i];
+
+ if (client->id == args.args[0]) {
+ u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
+
+ tegra186_mc_client_sid_override(mc, client, sid);
+ }
+ }
+ }
+
+ index++;
+ }
+#endif
+
+ return 0;
+}
+
+const struct tegra_mc_ops tegra186_mc_ops = {
+ .probe = tegra186_mc_probe,
+ .remove = tegra186_mc_remove,
+ .resume = tegra186_mc_resume,
+ .probe_device = tegra186_mc_probe_device,
+};
+
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
-static const struct tegra186_mc_client tegra186_mc_clients[] = {
+static const struct tegra_mc_client tegra186_mc_clients[] = {
{
+ .id = TEGRA186_MEMORY_CLIENT_PTCR,
.name = "ptcr",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
- .override = 0x000,
- .security = 0x004,
+ .sid = {
+ .override = 0x000,
+ .security = 0x004,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_AFIR,
.name = "afir",
.sid = TEGRA186_SID_AFI,
.regs = {
- .override = 0x070,
- .security = 0x074,
+ .sid = {
+ .override = 0x070,
+ .security = 0x074,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_HDAR,
.name = "hdar",
.sid = TEGRA186_SID_HDA,
.regs = {
- .override = 0x0a8,
- .security = 0x0ac,
+ .sid = {
+ .override = 0x0a8,
+ .security = 0x0ac,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
.name = "host1xdmar",
.sid = TEGRA186_SID_HOST1X,
.regs = {
- .override = 0x0b0,
- .security = 0x0b4,
+ .sid = {
+ .override = 0x0b0,
+ .security = 0x0b4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
.name = "nvencsrd",
.sid = TEGRA186_SID_NVENC,
.regs = {
- .override = 0x0e0,
- .security = 0x0e4,
+ .sid = {
+ .override = 0x0e0,
+ .security = 0x0e4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SATAR,
.name = "satar",
.sid = TEGRA186_SID_SATA,
.regs = {
- .override = 0x0f8,
- .security = 0x0fc,
+ .sid = {
+ .override = 0x0f8,
+ .security = 0x0fc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_MPCORER,
.name = "mpcorer",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
- .override = 0x138,
- .security = 0x13c,
+ .sid = {
+ .override = 0x138,
+ .security = 0x13c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
.name = "nvencswr",
.sid = TEGRA186_SID_NVENC,
.regs = {
- .override = 0x158,
- .security = 0x15c,
+ .sid = {
+ .override = 0x158,
+ .security = 0x15c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_AFIW,
.name = "afiw",
.sid = TEGRA186_SID_AFI,
.regs = {
- .override = 0x188,
- .security = 0x18c,
+ .sid = {
+ .override = 0x188,
+ .security = 0x18c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_HDAW,
.name = "hdaw",
.sid = TEGRA186_SID_HDA,
.regs = {
- .override = 0x1a8,
- .security = 0x1ac,
+ .sid = {
+ .override = 0x1a8,
+ .security = 0x1ac,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
.name = "mpcorew",
.sid = TEGRA186_SID_PASSTHROUGH,
.regs = {
- .override = 0x1c8,
- .security = 0x1cc,
+ .sid = {
+ .override = 0x1c8,
+ .security = 0x1cc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SATAW,
.name = "sataw",
.sid = TEGRA186_SID_SATA,
.regs = {
- .override = 0x1e8,
- .security = 0x1ec,
+ .sid = {
+ .override = 0x1e8,
+ .security = 0x1ec,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_ISPRA,
.name = "ispra",
.sid = TEGRA186_SID_ISP,
.regs = {
- .override = 0x220,
- .security = 0x224,
+ .sid = {
+ .override = 0x220,
+ .security = 0x224,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_ISPWA,
.name = "ispwa",
.sid = TEGRA186_SID_ISP,
.regs = {
- .override = 0x230,
- .security = 0x234,
+ .sid = {
+ .override = 0x230,
+ .security = 0x234,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_ISPWB,
.name = "ispwb",
.sid = TEGRA186_SID_ISP,
.regs = {
- .override = 0x238,
- .security = 0x23c,
+ .sid = {
+ .override = 0x238,
+ .security = 0x23c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
.name = "xusb_hostr",
.sid = TEGRA186_SID_XUSB_HOST,
.regs = {
- .override = 0x250,
- .security = 0x254,
+ .sid = {
+ .override = 0x250,
+ .security = 0x254,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
.name = "xusb_hostw",
.sid = TEGRA186_SID_XUSB_HOST,
.regs = {
- .override = 0x258,
- .security = 0x25c,
+ .sid = {
+ .override = 0x258,
+ .security = 0x25c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
.name = "xusb_devr",
.sid = TEGRA186_SID_XUSB_DEV,
.regs = {
- .override = 0x260,
- .security = 0x264,
+ .sid = {
+ .override = 0x260,
+ .security = 0x264,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
.name = "xusb_devw",
.sid = TEGRA186_SID_XUSB_DEV,
.regs = {
- .override = 0x268,
- .security = 0x26c,
+ .sid = {
+ .override = 0x268,
+ .security = 0x26c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
.name = "tsecsrd",
.sid = TEGRA186_SID_TSEC,
.regs = {
- .override = 0x2a0,
- .security = 0x2a4,
+ .sid = {
+ .override = 0x2a0,
+ .security = 0x2a4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
.name = "tsecswr",
.sid = TEGRA186_SID_TSEC,
.regs = {
- .override = 0x2a8,
- .security = 0x2ac,
+ .sid = {
+ .override = 0x2a8,
+ .security = 0x2ac,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
.name = "gpusrd",
.sid = TEGRA186_SID_GPU,
.regs = {
- .override = 0x2c0,
- .security = 0x2c4,
+ .sid = {
+ .override = 0x2c0,
+ .security = 0x2c4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
.name = "gpuswr",
.sid = TEGRA186_SID_GPU,
.regs = {
- .override = 0x2c8,
- .security = 0x2cc,
+ .sid = {
+ .override = 0x2c8,
+ .security = 0x2cc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
.name = "sdmmcra",
.sid = TEGRA186_SID_SDMMC1,
.regs = {
- .override = 0x300,
- .security = 0x304,
+ .sid = {
+ .override = 0x300,
+ .security = 0x304,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
.name = "sdmmcraa",
.sid = TEGRA186_SID_SDMMC2,
.regs = {
- .override = 0x308,
- .security = 0x30c,
+ .sid = {
+ .override = 0x308,
+ .security = 0x30c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
.name = "sdmmcr",
.sid = TEGRA186_SID_SDMMC3,
.regs = {
- .override = 0x310,
- .security = 0x314,
+ .sid = {
+ .override = 0x310,
+ .security = 0x314,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
.name = "sdmmcrab",
.sid = TEGRA186_SID_SDMMC4,
.regs = {
- .override = 0x318,
- .security = 0x31c,
+ .sid = {
+ .override = 0x318,
+ .security = 0x31c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
.name = "sdmmcwa",
.sid = TEGRA186_SID_SDMMC1,
.regs = {
- .override = 0x320,
- .security = 0x324,
+ .sid = {
+ .override = 0x320,
+ .security = 0x324,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
.name = "sdmmcwaa",
.sid = TEGRA186_SID_SDMMC2,
.regs = {
- .override = 0x328,
- .security = 0x32c,
+ .sid = {
+ .override = 0x328,
+ .security = 0x32c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
.name = "sdmmcw",
.sid = TEGRA186_SID_SDMMC3,
.regs = {
- .override = 0x330,
- .security = 0x334,
+ .sid = {
+ .override = 0x330,
+ .security = 0x334,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
.name = "sdmmcwab",
.sid = TEGRA186_SID_SDMMC4,
.regs = {
- .override = 0x338,
- .security = 0x33c,
+ .sid = {
+ .override = 0x338,
+ .security = 0x33c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_VICSRD,
.name = "vicsrd",
.sid = TEGRA186_SID_VIC,
.regs = {
- .override = 0x360,
- .security = 0x364,
+ .sid = {
+ .override = 0x360,
+ .security = 0x364,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_VICSWR,
.name = "vicswr",
.sid = TEGRA186_SID_VIC,
.regs = {
- .override = 0x368,
- .security = 0x36c,
+ .sid = {
+ .override = 0x368,
+ .security = 0x36c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_VIW,
.name = "viw",
.sid = TEGRA186_SID_VI,
.regs = {
- .override = 0x390,
- .security = 0x394,
+ .sid = {
+ .override = 0x390,
+ .security = 0x394,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
.name = "nvdecsrd",
.sid = TEGRA186_SID_NVDEC,
.regs = {
- .override = 0x3c0,
- .security = 0x3c4,
+ .sid = {
+ .override = 0x3c0,
+ .security = 0x3c4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
.name = "nvdecswr",
.sid = TEGRA186_SID_NVDEC,
.regs = {
- .override = 0x3c8,
- .security = 0x3cc,
+ .sid = {
+ .override = 0x3c8,
+ .security = 0x3cc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_APER,
.name = "aper",
.sid = TEGRA186_SID_APE,
.regs = {
- .override = 0x3d0,
- .security = 0x3d4,
+ .sid = {
+ .override = 0x3d0,
+ .security = 0x3d4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_APEW,
.name = "apew",
.sid = TEGRA186_SID_APE,
.regs = {
- .override = 0x3d8,
- .security = 0x3dc,
+ .sid = {
+ .override = 0x3d8,
+ .security = 0x3dc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
.name = "nvjpgsrd",
.sid = TEGRA186_SID_NVJPG,
.regs = {
- .override = 0x3f0,
- .security = 0x3f4,
+ .sid = {
+ .override = 0x3f0,
+ .security = 0x3f4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
.name = "nvjpgswr",
.sid = TEGRA186_SID_NVJPG,
.regs = {
- .override = 0x3f8,
- .security = 0x3fc,
+ .sid = {
+ .override = 0x3f8,
+ .security = 0x3fc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SESRD,
.name = "sesrd",
.sid = TEGRA186_SID_SE,
.regs = {
- .override = 0x400,
- .security = 0x404,
+ .sid = {
+ .override = 0x400,
+ .security = 0x404,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SESWR,
.name = "seswr",
.sid = TEGRA186_SID_SE,
.regs = {
- .override = 0x408,
- .security = 0x40c,
+ .sid = {
+ .override = 0x408,
+ .security = 0x40c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_ETRR,
.name = "etrr",
.sid = TEGRA186_SID_ETR,
.regs = {
- .override = 0x420,
- .security = 0x424,
+ .sid = {
+ .override = 0x420,
+ .security = 0x424,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_ETRW,
.name = "etrw",
.sid = TEGRA186_SID_ETR,
.regs = {
- .override = 0x428,
- .security = 0x42c,
+ .sid = {
+ .override = 0x428,
+ .security = 0x42c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
.name = "tsecsrdb",
.sid = TEGRA186_SID_TSECB,
.regs = {
- .override = 0x430,
- .security = 0x434,
+ .sid = {
+ .override = 0x430,
+ .security = 0x434,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
.name = "tsecswrb",
.sid = TEGRA186_SID_TSECB,
.regs = {
- .override = 0x438,
- .security = 0x43c,
+ .sid = {
+ .override = 0x438,
+ .security = 0x43c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
.name = "gpusrd2",
.sid = TEGRA186_SID_GPU,
.regs = {
- .override = 0x440,
- .security = 0x444,
+ .sid = {
+ .override = 0x440,
+ .security = 0x444,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
.name = "gpuswr2",
.sid = TEGRA186_SID_GPU,
.regs = {
- .override = 0x448,
- .security = 0x44c,
+ .sid = {
+ .override = 0x448,
+ .security = 0x44c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_AXISR,
.name = "axisr",
.sid = TEGRA186_SID_GPCDMA_0,
.regs = {
- .override = 0x460,
- .security = 0x464,
+ .sid = {
+ .override = 0x460,
+ .security = 0x464,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_AXISW,
.name = "axisw",
.sid = TEGRA186_SID_GPCDMA_0,
.regs = {
- .override = 0x468,
- .security = 0x46c,
+ .sid = {
+ .override = 0x468,
+ .security = 0x46c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_EQOSR,
.name = "eqosr",
.sid = TEGRA186_SID_EQOS,
.regs = {
- .override = 0x470,
- .security = 0x474,
+ .sid = {
+ .override = 0x470,
+ .security = 0x474,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_EQOSW,
.name = "eqosw",
.sid = TEGRA186_SID_EQOS,
.regs = {
- .override = 0x478,
- .security = 0x47c,
+ .sid = {
+ .override = 0x478,
+ .security = 0x47c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
.name = "ufshcr",
.sid = TEGRA186_SID_UFSHC,
.regs = {
- .override = 0x480,
- .security = 0x484,
+ .sid = {
+ .override = 0x480,
+ .security = 0x484,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
.name = "ufshcw",
.sid = TEGRA186_SID_UFSHC,
.regs = {
- .override = 0x488,
- .security = 0x48c,
+ .sid = {
+ .override = 0x488,
+ .security = 0x48c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
.name = "nvdisplayr",
.sid = TEGRA186_SID_NVDISPLAY,
.regs = {
- .override = 0x490,
- .security = 0x494,
+ .sid = {
+ .override = 0x490,
+ .security = 0x494,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_BPMPR,
.name = "bpmpr",
.sid = TEGRA186_SID_BPMP,
.regs = {
- .override = 0x498,
- .security = 0x49c,
+ .sid = {
+ .override = 0x498,
+ .security = 0x49c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_BPMPW,
.name = "bpmpw",
.sid = TEGRA186_SID_BPMP,
.regs = {
- .override = 0x4a0,
- .security = 0x4a4,
+ .sid = {
+ .override = 0x4a0,
+ .security = 0x4a4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
.name = "bpmpdmar",
.sid = TEGRA186_SID_BPMP,
.regs = {
- .override = 0x4a8,
- .security = 0x4ac,
+ .sid = {
+ .override = 0x4a8,
+ .security = 0x4ac,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
.name = "bpmpdmaw",
.sid = TEGRA186_SID_BPMP,
.regs = {
- .override = 0x4b0,
- .security = 0x4b4,
+ .sid = {
+ .override = 0x4b0,
+ .security = 0x4b4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_AONR,
.name = "aonr",
.sid = TEGRA186_SID_AON,
.regs = {
- .override = 0x4b8,
- .security = 0x4bc,
+ .sid = {
+ .override = 0x4b8,
+ .security = 0x4bc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_AONW,
.name = "aonw",
.sid = TEGRA186_SID_AON,
.regs = {
- .override = 0x4c0,
- .security = 0x4c4,
+ .sid = {
+ .override = 0x4c0,
+ .security = 0x4c4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
.name = "aondmar",
.sid = TEGRA186_SID_AON,
.regs = {
- .override = 0x4c8,
- .security = 0x4cc,
+ .sid = {
+ .override = 0x4c8,
+ .security = 0x4cc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
.name = "aondmaw",
.sid = TEGRA186_SID_AON,
.regs = {
- .override = 0x4d0,
- .security = 0x4d4,
+ .sid = {
+ .override = 0x4d0,
+ .security = 0x4d4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SCER,
.name = "scer",
.sid = TEGRA186_SID_SCE,
.regs = {
- .override = 0x4d8,
- .security = 0x4dc,
+ .sid = {
+ .override = 0x4d8,
+ .security = 0x4dc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SCEW,
.name = "scew",
.sid = TEGRA186_SID_SCE,
.regs = {
- .override = 0x4e0,
- .security = 0x4e4,
+ .sid = {
+ .override = 0x4e0,
+ .security = 0x4e4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
.name = "scedmar",
.sid = TEGRA186_SID_SCE,
.regs = {
- .override = 0x4e8,
- .security = 0x4ec,
+ .sid = {
+ .override = 0x4e8,
+ .security = 0x4ec,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
.name = "scedmaw",
.sid = TEGRA186_SID_SCE,
.regs = {
- .override = 0x4f0,
- .security = 0x4f4,
+ .sid = {
+ .override = 0x4f0,
+ .security = 0x4f4,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
.name = "apedmar",
.sid = TEGRA186_SID_APE,
.regs = {
- .override = 0x4f8,
- .security = 0x4fc,
+ .sid = {
+ .override = 0x4f8,
+ .security = 0x4fc,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
.name = "apedmaw",
.sid = TEGRA186_SID_APE,
.regs = {
- .override = 0x500,
- .security = 0x504,
+ .sid = {
+ .override = 0x500,
+ .security = 0x504,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
.name = "nvdisplayr1",
.sid = TEGRA186_SID_NVDISPLAY,
.regs = {
- .override = 0x508,
- .security = 0x50c,
+ .sid = {
+ .override = 0x508,
+ .security = 0x50c,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
.name = "vicsrd1",
.sid = TEGRA186_SID_VIC,
.regs = {
- .override = 0x510,
- .security = 0x514,
+ .sid = {
+ .override = 0x510,
+ .security = 0x514,
+ },
},
}, {
+ .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
.name = "nvdecsrd1",
.sid = TEGRA186_SID_NVDEC,
.regs = {
- .override = 0x518,
- .security = 0x51c,
+ .sid = {
+ .override = 0x518,
+ .security = 0x51c,
+ },
},
},
};
-static const struct tegra186_mc_soc tegra186_mc_soc = {
+const struct tegra_mc_soc tegra186_mc_soc = {
.num_clients = ARRAY_SIZE(tegra186_mc_clients),
.clients = tegra186_mc_clients,
+ .num_address_bits = 40,
+ .ops = &tegra186_mc_ops,
};
#endif
-
-#if defined(CONFIG_ARCH_TEGRA_194_SOC)
-static const struct tegra186_mc_client tegra194_mc_clients[] = {
- {
- .name = "ptcr",
- .sid = TEGRA194_SID_PASSTHROUGH,
- .regs = {
- .override = 0x000,
- .security = 0x004,
- },
- }, {
- .name = "miu7r",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x008,
- .security = 0x00c,
- },
- }, {
- .name = "miu7w",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x010,
- .security = 0x014,
- },
- }, {
- .name = "hdar",
- .sid = TEGRA194_SID_HDA,
- .regs = {
- .override = 0x0a8,
- .security = 0x0ac,
- },
- }, {
- .name = "host1xdmar",
- .sid = TEGRA194_SID_HOST1X,
- .regs = {
- .override = 0x0b0,
- .security = 0x0b4,
- },
- }, {
- .name = "nvencsrd",
- .sid = TEGRA194_SID_NVENC,
- .regs = {
- .override = 0x0e0,
- .security = 0x0e4,
- },
- }, {
- .name = "satar",
- .sid = TEGRA194_SID_SATA,
- .regs = {
- .override = 0x0f8,
- .security = 0x0fc,
- },
- }, {
- .name = "mpcorer",
- .sid = TEGRA194_SID_PASSTHROUGH,
- .regs = {
- .override = 0x138,
- .security = 0x13c,
- },
- }, {
- .name = "nvencswr",
- .sid = TEGRA194_SID_NVENC,
- .regs = {
- .override = 0x158,
- .security = 0x15c,
- },
- }, {
- .name = "hdaw",
- .sid = TEGRA194_SID_HDA,
- .regs = {
- .override = 0x1a8,
- .security = 0x1ac,
- },
- }, {
- .name = "mpcorew",
- .sid = TEGRA194_SID_PASSTHROUGH,
- .regs = {
- .override = 0x1c8,
- .security = 0x1cc,
- },
- }, {
- .name = "sataw",
- .sid = TEGRA194_SID_SATA,
- .regs = {
- .override = 0x1e8,
- .security = 0x1ec,
- },
- }, {
- .name = "ispra",
- .sid = TEGRA194_SID_ISP,
- .regs = {
- .override = 0x220,
- .security = 0x224,
- },
- }, {
- .name = "ispfalr",
- .sid = TEGRA194_SID_ISP_FALCON,
- .regs = {
- .override = 0x228,
- .security = 0x22c,
- },
- }, {
- .name = "ispwa",
- .sid = TEGRA194_SID_ISP,
- .regs = {
- .override = 0x230,
- .security = 0x234,
- },
- }, {
- .name = "ispwb",
- .sid = TEGRA194_SID_ISP,
- .regs = {
- .override = 0x238,
- .security = 0x23c,
- },
- }, {
- .name = "xusb_hostr",
- .sid = TEGRA194_SID_XUSB_HOST,
- .regs = {
- .override = 0x250,
- .security = 0x254,
- },
- }, {
- .name = "xusb_hostw",
- .sid = TEGRA194_SID_XUSB_HOST,
- .regs = {
- .override = 0x258,
- .security = 0x25c,
- },
- }, {
- .name = "xusb_devr",
- .sid = TEGRA194_SID_XUSB_DEV,
- .regs = {
- .override = 0x260,
- .security = 0x264,
- },
- }, {
- .name = "xusb_devw",
- .sid = TEGRA194_SID_XUSB_DEV,
- .regs = {
- .override = 0x268,
- .security = 0x26c,
- },
- }, {
- .name = "sdmmcra",
- .sid = TEGRA194_SID_SDMMC1,
- .regs = {
- .override = 0x300,
- .security = 0x304,
- },
- }, {
- .name = "sdmmcr",
- .sid = TEGRA194_SID_SDMMC3,
- .regs = {
- .override = 0x310,
- .security = 0x314,
- },
- }, {
- .name = "sdmmcrab",
- .sid = TEGRA194_SID_SDMMC4,
- .regs = {
- .override = 0x318,
- .security = 0x31c,
- },
- }, {
- .name = "sdmmcwa",
- .sid = TEGRA194_SID_SDMMC1,
- .regs = {
- .override = 0x320,
- .security = 0x324,
- },
- }, {
- .name = "sdmmcw",
- .sid = TEGRA194_SID_SDMMC3,
- .regs = {
- .override = 0x330,
- .security = 0x334,
- },
- }, {
- .name = "sdmmcwab",
- .sid = TEGRA194_SID_SDMMC4,
- .regs = {
- .override = 0x338,
- .security = 0x33c,
- },
- }, {
- .name = "vicsrd",
- .sid = TEGRA194_SID_VIC,
- .regs = {
- .override = 0x360,
- .security = 0x364,
- },
- }, {
- .name = "vicswr",
- .sid = TEGRA194_SID_VIC,
- .regs = {
- .override = 0x368,
- .security = 0x36c,
- },
- }, {
- .name = "viw",
- .sid = TEGRA194_SID_VI,
- .regs = {
- .override = 0x390,
- .security = 0x394,
- },
- }, {
- .name = "nvdecsrd",
- .sid = TEGRA194_SID_NVDEC,
- .regs = {
- .override = 0x3c0,
- .security = 0x3c4,
- },
- }, {
- .name = "nvdecswr",
- .sid = TEGRA194_SID_NVDEC,
- .regs = {
- .override = 0x3c8,
- .security = 0x3cc,
- },
- }, {
- .name = "aper",
- .sid = TEGRA194_SID_APE,
- .regs = {
- .override = 0x3c0,
- .security = 0x3c4,
- },
- }, {
- .name = "apew",
- .sid = TEGRA194_SID_APE,
- .regs = {
- .override = 0x3d0,
- .security = 0x3d4,
- },
- }, {
- .name = "nvjpgsrd",
- .sid = TEGRA194_SID_NVJPG,
- .regs = {
- .override = 0x3f0,
- .security = 0x3f4,
- },
- }, {
- .name = "nvjpgswr",
- .sid = TEGRA194_SID_NVJPG,
- .regs = {
- .override = 0x3f0,
- .security = 0x3f4,
- },
- }, {
- .name = "axiapr",
- .sid = TEGRA194_SID_PASSTHROUGH,
- .regs = {
- .override = 0x410,
- .security = 0x414,
- },
- }, {
- .name = "axiapw",
- .sid = TEGRA194_SID_PASSTHROUGH,
- .regs = {
- .override = 0x418,
- .security = 0x41c,
- },
- }, {
- .name = "etrr",
- .sid = TEGRA194_SID_ETR,
- .regs = {
- .override = 0x420,
- .security = 0x424,
- },
- }, {
- .name = "etrw",
- .sid = TEGRA194_SID_ETR,
- .regs = {
- .override = 0x428,
- .security = 0x42c,
- },
- }, {
- .name = "axisr",
- .sid = TEGRA194_SID_PASSTHROUGH,
- .regs = {
- .override = 0x460,
- .security = 0x464,
- },
- }, {
- .name = "axisw",
- .sid = TEGRA194_SID_PASSTHROUGH,
- .regs = {
- .override = 0x468,
- .security = 0x46c,
- },
- }, {
- .name = "eqosr",
- .sid = TEGRA194_SID_EQOS,
- .regs = {
- .override = 0x470,
- .security = 0x474,
- },
- }, {
- .name = "eqosw",
- .sid = TEGRA194_SID_EQOS,
- .regs = {
- .override = 0x478,
- .security = 0x47c,
- },
- }, {
- .name = "ufshcr",
- .sid = TEGRA194_SID_UFSHC,
- .regs = {
- .override = 0x480,
- .security = 0x484,
- },
- }, {
- .name = "ufshcw",
- .sid = TEGRA194_SID_UFSHC,
- .regs = {
- .override = 0x488,
- .security = 0x48c,
- },
- }, {
- .name = "nvdisplayr",
- .sid = TEGRA194_SID_NVDISPLAY,
- .regs = {
- .override = 0x490,
- .security = 0x494,
- },
- }, {
- .name = "bpmpr",
- .sid = TEGRA194_SID_BPMP,
- .regs = {
- .override = 0x498,
- .security = 0x49c,
- },
- }, {
- .name = "bpmpw",
- .sid = TEGRA194_SID_BPMP,
- .regs = {
- .override = 0x4a0,
- .security = 0x4a4,
- },
- }, {
- .name = "bpmpdmar",
- .sid = TEGRA194_SID_BPMP,
- .regs = {
- .override = 0x4a8,
- .security = 0x4ac,
- },
- }, {
- .name = "bpmpdmaw",
- .sid = TEGRA194_SID_BPMP,
- .regs = {
- .override = 0x4b0,
- .security = 0x4b4,
- },
- }, {
- .name = "aonr",
- .sid = TEGRA194_SID_AON,
- .regs = {
- .override = 0x4b8,
- .security = 0x4bc,
- },
- }, {
- .name = "aonw",
- .sid = TEGRA194_SID_AON,
- .regs = {
- .override = 0x4c0,
- .security = 0x4c4,
- },
- }, {
- .name = "aondmar",
- .sid = TEGRA194_SID_AON,
- .regs = {
- .override = 0x4c8,
- .security = 0x4cc,
- },
- }, {
- .name = "aondmaw",
- .sid = TEGRA194_SID_AON,
- .regs = {
- .override = 0x4d0,
- .security = 0x4d4,
- },
- }, {
- .name = "scer",
- .sid = TEGRA194_SID_SCE,
- .regs = {
- .override = 0x4d8,
- .security = 0x4dc,
- },
- }, {
- .name = "scew",
- .sid = TEGRA194_SID_SCE,
- .regs = {
- .override = 0x4e0,
- .security = 0x4e4,
- },
- }, {
- .name = "scedmar",
- .sid = TEGRA194_SID_SCE,
- .regs = {
- .override = 0x4e8,
- .security = 0x4ec,
- },
- }, {
- .name = "scedmaw",
- .sid = TEGRA194_SID_SCE,
- .regs = {
- .override = 0x4f0,
- .security = 0x4f4,
- },
- }, {
- .name = "apedmar",
- .sid = TEGRA194_SID_APE,
- .regs = {
- .override = 0x4f8,
- .security = 0x4fc,
- },
- }, {
- .name = "apedmaw",
- .sid = TEGRA194_SID_APE,
- .regs = {
- .override = 0x500,
- .security = 0x504,
- },
- }, {
- .name = "nvdisplayr1",
- .sid = TEGRA194_SID_NVDISPLAY,
- .regs = {
- .override = 0x508,
- .security = 0x50c,
- },
- }, {
- .name = "vicsrd1",
- .sid = TEGRA194_SID_VIC,
- .regs = {
- .override = 0x510,
- .security = 0x514,
- },
- }, {
- .name = "nvdecsrd1",
- .sid = TEGRA194_SID_NVDEC,
- .regs = {
- .override = 0x518,
- .security = 0x51c,
- },
- }, {
- .name = "miu0r",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x530,
- .security = 0x534,
- },
- }, {
- .name = "miu0w",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x538,
- .security = 0x53c,
- },
- }, {
- .name = "miu1r",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x540,
- .security = 0x544,
- },
- }, {
- .name = "miu1w",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x548,
- .security = 0x54c,
- },
- }, {
- .name = "miu2r",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x570,
- .security = 0x574,
- },
- }, {
- .name = "miu2w",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x578,
- .security = 0x57c,
- },
- }, {
- .name = "miu3r",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x580,
- .security = 0x584,
- },
- }, {
- .name = "miu3w",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x588,
- .security = 0x58c,
- },
- }, {
- .name = "miu4r",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x590,
- .security = 0x594,
- },
- }, {
- .name = "miu4w",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x598,
- .security = 0x59c,
- },
- }, {
- .name = "dpmur",
- .sid = TEGRA194_SID_PASSTHROUGH,
- .regs = {
- .override = 0x598,
- .security = 0x59c,
- },
- }, {
- .name = "vifalr",
- .sid = TEGRA194_SID_VI_FALCON,
- .regs = {
- .override = 0x5e0,
- .security = 0x5e4,
- },
- }, {
- .name = "vifalw",
- .sid = TEGRA194_SID_VI_FALCON,
- .regs = {
- .override = 0x5e8,
- .security = 0x5ec,
- },
- }, {
- .name = "dla0rda",
- .sid = TEGRA194_SID_NVDLA0,
- .regs = {
- .override = 0x5f0,
- .security = 0x5f4,
- },
- }, {
- .name = "dla0falrdb",
- .sid = TEGRA194_SID_NVDLA0,
- .regs = {
- .override = 0x5f8,
- .security = 0x5fc,
- },
- }, {
- .name = "dla0wra",
- .sid = TEGRA194_SID_NVDLA0,
- .regs = {
- .override = 0x600,
- .security = 0x604,
- },
- }, {
- .name = "dla0falwrb",
- .sid = TEGRA194_SID_NVDLA0,
- .regs = {
- .override = 0x608,
- .security = 0x60c,
- },
- }, {
- .name = "dla1rda",
- .sid = TEGRA194_SID_NVDLA1,
- .regs = {
- .override = 0x610,
- .security = 0x614,
- },
- }, {
- .name = "dla1falrdb",
- .sid = TEGRA194_SID_NVDLA1,
- .regs = {
- .override = 0x618,
- .security = 0x61c,
- },
- }, {
- .name = "dla1wra",
- .sid = TEGRA194_SID_NVDLA1,
- .regs = {
- .override = 0x620,
- .security = 0x624,
- },
- }, {
- .name = "dla1falwrb",
- .sid = TEGRA194_SID_NVDLA1,
- .regs = {
- .override = 0x628,
- .security = 0x62c,
- },
- }, {
- .name = "pva0rda",
- .sid = TEGRA194_SID_PVA0,
- .regs = {
- .override = 0x630,
- .security = 0x634,
- },
- }, {
- .name = "pva0rdb",
- .sid = TEGRA194_SID_PVA0,
- .regs = {
- .override = 0x638,
- .security = 0x63c,
- },
- }, {
- .name = "pva0rdc",
- .sid = TEGRA194_SID_PVA0,
- .regs = {
- .override = 0x640,
- .security = 0x644,
- },
- }, {
- .name = "pva0wra",
- .sid = TEGRA194_SID_PVA0,
- .regs = {
- .override = 0x648,
- .security = 0x64c,
- },
- }, {
- .name = "pva0wrb",
- .sid = TEGRA194_SID_PVA0,
- .regs = {
- .override = 0x650,
- .security = 0x654,
- },
- }, {
- .name = "pva0wrc",
- .sid = TEGRA194_SID_PVA0,
- .regs = {
- .override = 0x658,
- .security = 0x65c,
- },
- }, {
- .name = "pva1rda",
- .sid = TEGRA194_SID_PVA1,
- .regs = {
- .override = 0x660,
- .security = 0x664,
- },
- }, {
- .name = "pva1rdb",
- .sid = TEGRA194_SID_PVA1,
- .regs = {
- .override = 0x668,
- .security = 0x66c,
- },
- }, {
- .name = "pva1rdc",
- .sid = TEGRA194_SID_PVA1,
- .regs = {
- .override = 0x670,
- .security = 0x674,
- },
- }, {
- .name = "pva1wra",
- .sid = TEGRA194_SID_PVA1,
- .regs = {
- .override = 0x678,
- .security = 0x67c,
- },
- }, {
- .name = "pva1wrb",
- .sid = TEGRA194_SID_PVA1,
- .regs = {
- .override = 0x680,
- .security = 0x684,
- },
- }, {
- .name = "pva1wrc",
- .sid = TEGRA194_SID_PVA1,
- .regs = {
- .override = 0x688,
- .security = 0x68c,
- },
- }, {
- .name = "rcer",
- .sid = TEGRA194_SID_RCE,
- .regs = {
- .override = 0x690,
- .security = 0x694,
- },
- }, {
- .name = "rcew",
- .sid = TEGRA194_SID_RCE,
- .regs = {
- .override = 0x698,
- .security = 0x69c,
- },
- }, {
- .name = "rcedmar",
- .sid = TEGRA194_SID_RCE,
- .regs = {
- .override = 0x6a0,
- .security = 0x6a4,
- },
- }, {
- .name = "rcedmaw",
- .sid = TEGRA194_SID_RCE,
- .regs = {
- .override = 0x6a8,
- .security = 0x6ac,
- },
- }, {
- .name = "nvenc1srd",
- .sid = TEGRA194_SID_NVENC1,
- .regs = {
- .override = 0x6b0,
- .security = 0x6b4,
- },
- }, {
- .name = "nvenc1swr",
- .sid = TEGRA194_SID_NVENC1,
- .regs = {
- .override = 0x6b8,
- .security = 0x6bc,
- },
- }, {
- .name = "pcie0r",
- .sid = TEGRA194_SID_PCIE0,
- .regs = {
- .override = 0x6c0,
- .security = 0x6c4,
- },
- }, {
- .name = "pcie0w",
- .sid = TEGRA194_SID_PCIE0,
- .regs = {
- .override = 0x6c8,
- .security = 0x6cc,
- },
- }, {
- .name = "pcie1r",
- .sid = TEGRA194_SID_PCIE1,
- .regs = {
- .override = 0x6d0,
- .security = 0x6d4,
- },
- }, {
- .name = "pcie1w",
- .sid = TEGRA194_SID_PCIE1,
- .regs = {
- .override = 0x6d8,
- .security = 0x6dc,
- },
- }, {
- .name = "pcie2ar",
- .sid = TEGRA194_SID_PCIE2,
- .regs = {
- .override = 0x6e0,
- .security = 0x6e4,
- },
- }, {
- .name = "pcie2aw",
- .sid = TEGRA194_SID_PCIE2,
- .regs = {
- .override = 0x6e8,
- .security = 0x6ec,
- },
- }, {
- .name = "pcie3r",
- .sid = TEGRA194_SID_PCIE3,
- .regs = {
- .override = 0x6f0,
- .security = 0x6f4,
- },
- }, {
- .name = "pcie3w",
- .sid = TEGRA194_SID_PCIE3,
- .regs = {
- .override = 0x6f8,
- .security = 0x6fc,
- },
- }, {
- .name = "pcie4r",
- .sid = TEGRA194_SID_PCIE4,
- .regs = {
- .override = 0x700,
- .security = 0x704,
- },
- }, {
- .name = "pcie4w",
- .sid = TEGRA194_SID_PCIE4,
- .regs = {
- .override = 0x708,
- .security = 0x70c,
- },
- }, {
- .name = "pcie5r",
- .sid = TEGRA194_SID_PCIE5,
- .regs = {
- .override = 0x710,
- .security = 0x714,
- },
- }, {
- .name = "pcie5w",
- .sid = TEGRA194_SID_PCIE5,
- .regs = {
- .override = 0x718,
- .security = 0x71c,
- },
- }, {
- .name = "ispfalw",
- .sid = TEGRA194_SID_ISP_FALCON,
- .regs = {
- .override = 0x720,
- .security = 0x724,
- },
- }, {
- .name = "dla0rda1",
- .sid = TEGRA194_SID_NVDLA0,
- .regs = {
- .override = 0x748,
- .security = 0x74c,
- },
- }, {
- .name = "dla1rda1",
- .sid = TEGRA194_SID_NVDLA1,
- .regs = {
- .override = 0x750,
- .security = 0x754,
- },
- }, {
- .name = "pva0rda1",
- .sid = TEGRA194_SID_PVA0,
- .regs = {
- .override = 0x758,
- .security = 0x75c,
- },
- }, {
- .name = "pva0rdb1",
- .sid = TEGRA194_SID_PVA0,
- .regs = {
- .override = 0x760,
- .security = 0x764,
- },
- }, {
- .name = "pva1rda1",
- .sid = TEGRA194_SID_PVA1,
- .regs = {
- .override = 0x768,
- .security = 0x76c,
- },
- }, {
- .name = "pva1rdb1",
- .sid = TEGRA194_SID_PVA1,
- .regs = {
- .override = 0x770,
- .security = 0x774,
- },
- }, {
- .name = "pcie5r1",
- .sid = TEGRA194_SID_PCIE5,
- .regs = {
- .override = 0x778,
- .security = 0x77c,
- },
- }, {
- .name = "nvencsrd1",
- .sid = TEGRA194_SID_NVENC,
- .regs = {
- .override = 0x780,
- .security = 0x784,
- },
- }, {
- .name = "nvenc1srd1",
- .sid = TEGRA194_SID_NVENC1,
- .regs = {
- .override = 0x788,
- .security = 0x78c,
- },
- }, {
- .name = "ispra1",
- .sid = TEGRA194_SID_ISP,
- .regs = {
- .override = 0x790,
- .security = 0x794,
- },
- }, {
- .name = "pcie0r1",
- .sid = TEGRA194_SID_PCIE0,
- .regs = {
- .override = 0x798,
- .security = 0x79c,
- },
- }, {
- .name = "nvdec1srd",
- .sid = TEGRA194_SID_NVDEC1,
- .regs = {
- .override = 0x7c8,
- .security = 0x7cc,
- },
- }, {
- .name = "nvdec1srd1",
- .sid = TEGRA194_SID_NVDEC1,
- .regs = {
- .override = 0x7d0,
- .security = 0x7d4,
- },
- }, {
- .name = "nvdec1swr",
- .sid = TEGRA194_SID_NVDEC1,
- .regs = {
- .override = 0x7d8,
- .security = 0x7dc,
- },
- }, {
- .name = "miu5r",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x7e0,
- .security = 0x7e4,
- },
- }, {
- .name = "miu5w",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x7e8,
- .security = 0x7ec,
- },
- }, {
- .name = "miu6r",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x7f0,
- .security = 0x7f4,
- },
- }, {
- .name = "miu6w",
- .sid = TEGRA194_SID_MIU,
- .regs = {
- .override = 0x7f8,
- .security = 0x7fc,
- },
- },
-};
-
-static const struct tegra186_mc_soc tegra194_mc_soc = {
- .num_clients = ARRAY_SIZE(tegra194_mc_clients),
- .clients = tegra194_mc_clients,
-};
-#endif
-
-static int tegra186_mc_probe(struct platform_device *pdev)
-{
- struct tegra186_mc *mc;
- struct resource *res;
- int err;
-
- mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
- if (!mc)
- return -ENOMEM;
-
- mc->soc = of_device_get_match_data(&pdev->dev);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- mc->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(mc->regs))
- return PTR_ERR(mc->regs);
-
- mc->dev = &pdev->dev;
-
- err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
- if (err < 0)
- return err;
-
- platform_set_drvdata(pdev, mc);
- tegra186_mc_program_sid(mc);
-
- return 0;
-}
-
-static int tegra186_mc_remove(struct platform_device *pdev)
-{
- struct tegra186_mc *mc = platform_get_drvdata(pdev);
-
- of_platform_depopulate(mc->dev);
-
- return 0;
-}
-
-static const struct of_device_id tegra186_mc_of_match[] = {
-#if defined(CONFIG_ARCH_TEGRA_186_SOC)
- { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
-#endif
-#if defined(CONFIG_ARCH_TEGRA_194_SOC)
- { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
-#endif
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, tegra186_mc_of_match);
-
-static int __maybe_unused tegra186_mc_suspend(struct device *dev)
-{
- return 0;
-}
-
-static int __maybe_unused tegra186_mc_resume(struct device *dev)
-{
- struct tegra186_mc *mc = dev_get_drvdata(dev);
-
- tegra186_mc_program_sid(mc);
-
- return 0;
-}
-
-static const struct dev_pm_ops tegra186_mc_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(tegra186_mc_suspend, tegra186_mc_resume)
-};
-
-static struct platform_driver tegra186_mc_driver = {
- .driver = {
- .name = "tegra186-mc",
- .of_match_table = tegra186_mc_of_match,
- .pm = &tegra186_mc_pm_ops,
- .suppress_bind_attrs = true,
- },
- .probe = tegra186_mc_probe,
- .remove = tegra186_mc_remove,
-};
-module_platform_driver(tegra186_mc_driver);
-
-MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
-MODULE_DESCRIPTION("NVIDIA Tegra186 Memory Controller driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c
new file mode 100644
index 000000000000..cab998b8bd5c
--- /dev/null
+++ b/drivers/memory/tegra/tegra194.c
@@ -0,0 +1,1351 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <soc/tegra/mc.h>
+
+#include <dt-bindings/memory/tegra194-mc.h>
+
+#include "mc.h"
+
+static const struct tegra_mc_client tegra194_mc_clients[] = {
+ {
+ .id = TEGRA194_MEMORY_CLIENT_PTCR,
+ .name = "ptcr",
+ .sid = TEGRA194_SID_PASSTHROUGH,
+ .regs = {
+ .sid = {
+ .override = 0x000,
+ .security = 0x004,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU7R,
+ .name = "miu7r",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x008,
+ .security = 0x00c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU7W,
+ .name = "miu7w",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x010,
+ .security = 0x014,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_HDAR,
+ .name = "hdar",
+ .sid = TEGRA194_SID_HDA,
+ .regs = {
+ .sid = {
+ .override = 0x0a8,
+ .security = 0x0ac,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
+ .name = "host1xdmar",
+ .sid = TEGRA194_SID_HOST1X,
+ .regs = {
+ .sid = {
+ .override = 0x0b0,
+ .security = 0x0b4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
+ .name = "nvencsrd",
+ .sid = TEGRA194_SID_NVENC,
+ .regs = {
+ .sid = {
+ .override = 0x0e0,
+ .security = 0x0e4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SATAR,
+ .name = "satar",
+ .sid = TEGRA194_SID_SATA,
+ .regs = {
+ .sid = {
+ .override = 0x0f8,
+ .security = 0x0fc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MPCORER,
+ .name = "mpcorer",
+ .sid = TEGRA194_SID_PASSTHROUGH,
+ .regs = {
+ .sid = {
+ .override = 0x138,
+ .security = 0x13c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVENCSWR,
+ .name = "nvencswr",
+ .sid = TEGRA194_SID_NVENC,
+ .regs = {
+ .sid = {
+ .override = 0x158,
+ .security = 0x15c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_HDAW,
+ .name = "hdaw",
+ .sid = TEGRA194_SID_HDA,
+ .regs = {
+ .sid = {
+ .override = 0x1a8,
+ .security = 0x1ac,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MPCOREW,
+ .name = "mpcorew",
+ .sid = TEGRA194_SID_PASSTHROUGH,
+ .regs = {
+ .sid = {
+ .override = 0x1c8,
+ .security = 0x1cc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SATAW,
+ .name = "sataw",
+ .sid = TEGRA194_SID_SATA,
+ .regs = {
+ .sid = {
+ .override = 0x1e8,
+ .security = 0x1ec,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_ISPRA,
+ .name = "ispra",
+ .sid = TEGRA194_SID_ISP,
+ .regs = {
+ .sid = {
+ .override = 0x220,
+ .security = 0x224,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_ISPFALR,
+ .name = "ispfalr",
+ .sid = TEGRA194_SID_ISP_FALCON,
+ .regs = {
+ .sid = {
+ .override = 0x228,
+ .security = 0x22c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_ISPWA,
+ .name = "ispwa",
+ .sid = TEGRA194_SID_ISP,
+ .regs = {
+ .sid = {
+ .override = 0x230,
+ .security = 0x234,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_ISPWB,
+ .name = "ispwb",
+ .sid = TEGRA194_SID_ISP,
+ .regs = {
+ .sid = {
+ .override = 0x238,
+ .security = 0x23c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR,
+ .name = "xusb_hostr",
+ .sid = TEGRA194_SID_XUSB_HOST,
+ .regs = {
+ .sid = {
+ .override = 0x250,
+ .security = 0x254,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW,
+ .name = "xusb_hostw",
+ .sid = TEGRA194_SID_XUSB_HOST,
+ .regs = {
+ .sid = {
+ .override = 0x258,
+ .security = 0x25c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR,
+ .name = "xusb_devr",
+ .sid = TEGRA194_SID_XUSB_DEV,
+ .regs = {
+ .sid = {
+ .override = 0x260,
+ .security = 0x264,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW,
+ .name = "xusb_devw",
+ .sid = TEGRA194_SID_XUSB_DEV,
+ .regs = {
+ .sid = {
+ .override = 0x268,
+ .security = 0x26c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCRA,
+ .name = "sdmmcra",
+ .sid = TEGRA194_SID_SDMMC1,
+ .regs = {
+ .sid = {
+ .override = 0x300,
+ .security = 0x304,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCR,
+ .name = "sdmmcr",
+ .sid = TEGRA194_SID_SDMMC3,
+ .regs = {
+ .sid = {
+ .override = 0x310,
+ .security = 0x314,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB,
+ .name = "sdmmcrab",
+ .sid = TEGRA194_SID_SDMMC4,
+ .regs = {
+ .sid = {
+ .override = 0x318,
+ .security = 0x31c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCWA,
+ .name = "sdmmcwa",
+ .sid = TEGRA194_SID_SDMMC1,
+ .regs = {
+ .sid = {
+ .override = 0x320,
+ .security = 0x324,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCW,
+ .name = "sdmmcw",
+ .sid = TEGRA194_SID_SDMMC3,
+ .regs = {
+ .sid = {
+ .override = 0x330,
+ .security = 0x334,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB,
+ .name = "sdmmcwab",
+ .sid = TEGRA194_SID_SDMMC4,
+ .regs = {
+ .sid = {
+ .override = 0x338,
+ .security = 0x33c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_VICSRD,
+ .name = "vicsrd",
+ .sid = TEGRA194_SID_VIC,
+ .regs = {
+ .sid = {
+ .override = 0x360,
+ .security = 0x364,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_VICSWR,
+ .name = "vicswr",
+ .sid = TEGRA194_SID_VIC,
+ .regs = {
+ .sid = {
+ .override = 0x368,
+ .security = 0x36c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_VIW,
+ .name = "viw",
+ .sid = TEGRA194_SID_VI,
+ .regs = {
+ .sid = {
+ .override = 0x390,
+ .security = 0x394,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVDECSRD,
+ .name = "nvdecsrd",
+ .sid = TEGRA194_SID_NVDEC,
+ .regs = {
+ .sid = {
+ .override = 0x3c0,
+ .security = 0x3c4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVDECSWR,
+ .name = "nvdecswr",
+ .sid = TEGRA194_SID_NVDEC,
+ .regs = {
+ .sid = {
+ .override = 0x3c8,
+ .security = 0x3cc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_APER,
+ .name = "aper",
+ .sid = TEGRA194_SID_APE,
+ .regs = {
+ .sid = {
+ .override = 0x3c0,
+ .security = 0x3c4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_APEW,
+ .name = "apew",
+ .sid = TEGRA194_SID_APE,
+ .regs = {
+ .sid = {
+ .override = 0x3d0,
+ .security = 0x3d4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD,
+ .name = "nvjpgsrd",
+ .sid = TEGRA194_SID_NVJPG,
+ .regs = {
+ .sid = {
+ .override = 0x3f0,
+ .security = 0x3f4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR,
+ .name = "nvjpgswr",
+ .sid = TEGRA194_SID_NVJPG,
+ .regs = {
+ .sid = {
+ .override = 0x3f0,
+ .security = 0x3f4,
+ },
+ },
+ }, {
+ .name = "axiapr",
+ .id = TEGRA194_MEMORY_CLIENT_AXIAPR,
+ .sid = TEGRA194_SID_PASSTHROUGH,
+ .regs = {
+ .sid = {
+ .override = 0x410,
+ .security = 0x414,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_AXIAPW,
+ .name = "axiapw",
+ .sid = TEGRA194_SID_PASSTHROUGH,
+ .regs = {
+ .sid = {
+ .override = 0x418,
+ .security = 0x41c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_ETRR,
+ .name = "etrr",
+ .sid = TEGRA194_SID_ETR,
+ .regs = {
+ .sid = {
+ .override = 0x420,
+ .security = 0x424,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_ETRW,
+ .name = "etrw",
+ .sid = TEGRA194_SID_ETR,
+ .regs = {
+ .sid = {
+ .override = 0x428,
+ .security = 0x42c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_AXISR,
+ .name = "axisr",
+ .sid = TEGRA194_SID_PASSTHROUGH,
+ .regs = {
+ .sid = {
+ .override = 0x460,
+ .security = 0x464,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_AXISW,
+ .name = "axisw",
+ .sid = TEGRA194_SID_PASSTHROUGH,
+ .regs = {
+ .sid = {
+ .override = 0x468,
+ .security = 0x46c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_EQOSR,
+ .name = "eqosr",
+ .sid = TEGRA194_SID_EQOS,
+ .regs = {
+ .sid = {
+ .override = 0x470,
+ .security = 0x474,
+ },
+ },
+ }, {
+ .name = "eqosw",
+ .id = TEGRA194_MEMORY_CLIENT_EQOSW,
+ .sid = TEGRA194_SID_EQOS,
+ .regs = {
+ .sid = {
+ .override = 0x478,
+ .security = 0x47c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_UFSHCR,
+ .name = "ufshcr",
+ .sid = TEGRA194_SID_UFSHC,
+ .regs = {
+ .sid = {
+ .override = 0x480,
+ .security = 0x484,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_UFSHCW,
+ .name = "ufshcw",
+ .sid = TEGRA194_SID_UFSHC,
+ .regs = {
+ .sid = {
+ .override = 0x488,
+ .security = 0x48c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR,
+ .name = "nvdisplayr",
+ .sid = TEGRA194_SID_NVDISPLAY,
+ .regs = {
+ .sid = {
+ .override = 0x490,
+ .security = 0x494,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_BPMPR,
+ .name = "bpmpr",
+ .sid = TEGRA194_SID_BPMP,
+ .regs = {
+ .sid = {
+ .override = 0x498,
+ .security = 0x49c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_BPMPW,
+ .name = "bpmpw",
+ .sid = TEGRA194_SID_BPMP,
+ .regs = {
+ .sid = {
+ .override = 0x4a0,
+ .security = 0x4a4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR,
+ .name = "bpmpdmar",
+ .sid = TEGRA194_SID_BPMP,
+ .regs = {
+ .sid = {
+ .override = 0x4a8,
+ .security = 0x4ac,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW,
+ .name = "bpmpdmaw",
+ .sid = TEGRA194_SID_BPMP,
+ .regs = {
+ .sid = {
+ .override = 0x4b0,
+ .security = 0x4b4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_AONR,
+ .name = "aonr",
+ .sid = TEGRA194_SID_AON,
+ .regs = {
+ .sid = {
+ .override = 0x4b8,
+ .security = 0x4bc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_AONW,
+ .name = "aonw",
+ .sid = TEGRA194_SID_AON,
+ .regs = {
+ .sid = {
+ .override = 0x4c0,
+ .security = 0x4c4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_AONDMAR,
+ .name = "aondmar",
+ .sid = TEGRA194_SID_AON,
+ .regs = {
+ .sid = {
+ .override = 0x4c8,
+ .security = 0x4cc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_AONDMAW,
+ .name = "aondmaw",
+ .sid = TEGRA194_SID_AON,
+ .regs = {
+ .sid = {
+ .override = 0x4d0,
+ .security = 0x4d4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SCER,
+ .name = "scer",
+ .sid = TEGRA194_SID_SCE,
+ .regs = {
+ .sid = {
+ .override = 0x4d8,
+ .security = 0x4dc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SCEW,
+ .name = "scew",
+ .sid = TEGRA194_SID_SCE,
+ .regs = {
+ .sid = {
+ .override = 0x4e0,
+ .security = 0x4e4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SCEDMAR,
+ .name = "scedmar",
+ .sid = TEGRA194_SID_SCE,
+ .regs = {
+ .sid = {
+ .override = 0x4e8,
+ .security = 0x4ec,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_SCEDMAW,
+ .name = "scedmaw",
+ .sid = TEGRA194_SID_SCE,
+ .regs = {
+ .sid = {
+ .override = 0x4f0,
+ .security = 0x4f4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_APEDMAR,
+ .name = "apedmar",
+ .sid = TEGRA194_SID_APE,
+ .regs = {
+ .sid = {
+ .override = 0x4f8,
+ .security = 0x4fc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_APEDMAW,
+ .name = "apedmaw",
+ .sid = TEGRA194_SID_APE,
+ .regs = {
+ .sid = {
+ .override = 0x500,
+ .security = 0x504,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1,
+ .name = "nvdisplayr1",
+ .sid = TEGRA194_SID_NVDISPLAY,
+ .regs = {
+ .sid = {
+ .override = 0x508,
+ .security = 0x50c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_VICSRD1,
+ .name = "vicsrd1",
+ .sid = TEGRA194_SID_VIC,
+ .regs = {
+ .sid = {
+ .override = 0x510,
+ .security = 0x514,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1,
+ .name = "nvdecsrd1",
+ .sid = TEGRA194_SID_NVDEC,
+ .regs = {
+ .sid = {
+ .override = 0x518,
+ .security = 0x51c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU0R,
+ .name = "miu0r",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x530,
+ .security = 0x534,
+ },
+ },
+ }, {
+ .name = "miu0w",
+ .id = TEGRA194_MEMORY_CLIENT_MIU0W,
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x538,
+ .security = 0x53c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU1R,
+ .name = "miu1r",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x540,
+ .security = 0x544,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU1W,
+ .name = "miu1w",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x548,
+ .security = 0x54c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU2R,
+ .name = "miu2r",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x570,
+ .security = 0x574,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU2W,
+ .name = "miu2w",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x578,
+ .security = 0x57c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU3R,
+ .name = "miu3r",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x580,
+ .security = 0x584,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU3W,
+ .name = "miu3w",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x588,
+ .security = 0x58c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU4R,
+ .name = "miu4r",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x590,
+ .security = 0x594,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU4W,
+ .name = "miu4w",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x598,
+ .security = 0x59c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DPMUR,
+ .name = "dpmur",
+ .sid = TEGRA194_SID_PASSTHROUGH,
+ .regs = {
+ .sid = {
+ .override = 0x598,
+ .security = 0x59c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_VIFALR,
+ .name = "vifalr",
+ .sid = TEGRA194_SID_VI_FALCON,
+ .regs = {
+ .sid = {
+ .override = 0x5e0,
+ .security = 0x5e4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_VIFALW,
+ .name = "vifalw",
+ .sid = TEGRA194_SID_VI_FALCON,
+ .regs = {
+ .sid = {
+ .override = 0x5e8,
+ .security = 0x5ec,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0RDA,
+ .name = "dla0rda",
+ .sid = TEGRA194_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x5f0,
+ .security = 0x5f4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB,
+ .name = "dla0falrdb",
+ .sid = TEGRA194_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x5f8,
+ .security = 0x5fc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0WRA,
+ .name = "dla0wra",
+ .sid = TEGRA194_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x600,
+ .security = 0x604,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB,
+ .name = "dla0falwrb",
+ .sid = TEGRA194_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x608,
+ .security = 0x60c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1RDA,
+ .name = "dla1rda",
+ .sid = TEGRA194_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x610,
+ .security = 0x614,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB,
+ .name = "dla1falrdb",
+ .sid = TEGRA194_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x618,
+ .security = 0x61c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1WRA,
+ .name = "dla1wra",
+ .sid = TEGRA194_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x620,
+ .security = 0x624,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB,
+ .name = "dla1falwrb",
+ .sid = TEGRA194_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x628,
+ .security = 0x62c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDA,
+ .name = "pva0rda",
+ .sid = TEGRA194_SID_PVA0,
+ .regs = {
+ .sid = {
+ .override = 0x630,
+ .security = 0x634,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDB,
+ .name = "pva0rdb",
+ .sid = TEGRA194_SID_PVA0,
+ .regs = {
+ .sid = {
+ .override = 0x638,
+ .security = 0x63c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDC,
+ .name = "pva0rdc",
+ .sid = TEGRA194_SID_PVA0,
+ .regs = {
+ .sid = {
+ .override = 0x640,
+ .security = 0x644,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0WRA,
+ .name = "pva0wra",
+ .sid = TEGRA194_SID_PVA0,
+ .regs = {
+ .sid = {
+ .override = 0x648,
+ .security = 0x64c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0WRB,
+ .name = "pva0wrb",
+ .sid = TEGRA194_SID_PVA0,
+ .regs = {
+ .sid = {
+ .override = 0x650,
+ .security = 0x654,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0WRC,
+ .name = "pva0wrc",
+ .sid = TEGRA194_SID_PVA0,
+ .regs = {
+ .sid = {
+ .override = 0x658,
+ .security = 0x65c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDA,
+ .name = "pva1rda",
+ .sid = TEGRA194_SID_PVA1,
+ .regs = {
+ .sid = {
+ .override = 0x660,
+ .security = 0x664,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDB,
+ .name = "pva1rdb",
+ .sid = TEGRA194_SID_PVA1,
+ .regs = {
+ .sid = {
+ .override = 0x668,
+ .security = 0x66c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDC,
+ .name = "pva1rdc",
+ .sid = TEGRA194_SID_PVA1,
+ .regs = {
+ .sid = {
+ .override = 0x670,
+ .security = 0x674,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1WRA,
+ .name = "pva1wra",
+ .sid = TEGRA194_SID_PVA1,
+ .regs = {
+ .sid = {
+ .override = 0x678,
+ .security = 0x67c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1WRB,
+ .name = "pva1wrb",
+ .sid = TEGRA194_SID_PVA1,
+ .regs = {
+ .sid = {
+ .override = 0x680,
+ .security = 0x684,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1WRC,
+ .name = "pva1wrc",
+ .sid = TEGRA194_SID_PVA1,
+ .regs = {
+ .sid = {
+ .override = 0x688,
+ .security = 0x68c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_RCER,
+ .name = "rcer",
+ .sid = TEGRA194_SID_RCE,
+ .regs = {
+ .sid = {
+ .override = 0x690,
+ .security = 0x694,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_RCEW,
+ .name = "rcew",
+ .sid = TEGRA194_SID_RCE,
+ .regs = {
+ .sid = {
+ .override = 0x698,
+ .security = 0x69c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_RCEDMAR,
+ .name = "rcedmar",
+ .sid = TEGRA194_SID_RCE,
+ .regs = {
+ .sid = {
+ .override = 0x6a0,
+ .security = 0x6a4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_RCEDMAW,
+ .name = "rcedmaw",
+ .sid = TEGRA194_SID_RCE,
+ .regs = {
+ .sid = {
+ .override = 0x6a8,
+ .security = 0x6ac,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD,
+ .name = "nvenc1srd",
+ .sid = TEGRA194_SID_NVENC1,
+ .regs = {
+ .sid = {
+ .override = 0x6b0,
+ .security = 0x6b4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR,
+ .name = "nvenc1swr",
+ .sid = TEGRA194_SID_NVENC1,
+ .regs = {
+ .sid = {
+ .override = 0x6b8,
+ .security = 0x6bc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE0R,
+ .name = "pcie0r",
+ .sid = TEGRA194_SID_PCIE0,
+ .regs = {
+ .sid = {
+ .override = 0x6c0,
+ .security = 0x6c4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE0W,
+ .name = "pcie0w",
+ .sid = TEGRA194_SID_PCIE0,
+ .regs = {
+ .sid = {
+ .override = 0x6c8,
+ .security = 0x6cc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE1R,
+ .name = "pcie1r",
+ .sid = TEGRA194_SID_PCIE1,
+ .regs = {
+ .sid = {
+ .override = 0x6d0,
+ .security = 0x6d4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE1W,
+ .name = "pcie1w",
+ .sid = TEGRA194_SID_PCIE1,
+ .regs = {
+ .sid = {
+ .override = 0x6d8,
+ .security = 0x6dc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE2AR,
+ .name = "pcie2ar",
+ .sid = TEGRA194_SID_PCIE2,
+ .regs = {
+ .sid = {
+ .override = 0x6e0,
+ .security = 0x6e4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE2AW,
+ .name = "pcie2aw",
+ .sid = TEGRA194_SID_PCIE2,
+ .regs = {
+ .sid = {
+ .override = 0x6e8,
+ .security = 0x6ec,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE3R,
+ .name = "pcie3r",
+ .sid = TEGRA194_SID_PCIE3,
+ .regs = {
+ .sid = {
+ .override = 0x6f0,
+ .security = 0x6f4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE3W,
+ .name = "pcie3w",
+ .sid = TEGRA194_SID_PCIE3,
+ .regs = {
+ .sid = {
+ .override = 0x6f8,
+ .security = 0x6fc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE4R,
+ .name = "pcie4r",
+ .sid = TEGRA194_SID_PCIE4,
+ .regs = {
+ .sid = {
+ .override = 0x700,
+ .security = 0x704,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE4W,
+ .name = "pcie4w",
+ .sid = TEGRA194_SID_PCIE4,
+ .regs = {
+ .sid = {
+ .override = 0x708,
+ .security = 0x70c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE5R,
+ .name = "pcie5r",
+ .sid = TEGRA194_SID_PCIE5,
+ .regs = {
+ .sid = {
+ .override = 0x710,
+ .security = 0x714,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE5W,
+ .name = "pcie5w",
+ .sid = TEGRA194_SID_PCIE5,
+ .regs = {
+ .sid = {
+ .override = 0x718,
+ .security = 0x71c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_ISPFALW,
+ .name = "ispfalw",
+ .sid = TEGRA194_SID_ISP_FALCON,
+ .regs = {
+ .sid = {
+ .override = 0x720,
+ .security = 0x724,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1,
+ .name = "dla0rda1",
+ .sid = TEGRA194_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x748,
+ .security = 0x74c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1,
+ .name = "dla1rda1",
+ .sid = TEGRA194_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x750,
+ .security = 0x754,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1,
+ .name = "pva0rda1",
+ .sid = TEGRA194_SID_PVA0,
+ .regs = {
+ .sid = {
+ .override = 0x758,
+ .security = 0x75c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1,
+ .name = "pva0rdb1",
+ .sid = TEGRA194_SID_PVA0,
+ .regs = {
+ .sid = {
+ .override = 0x760,
+ .security = 0x764,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1,
+ .name = "pva1rda1",
+ .sid = TEGRA194_SID_PVA1,
+ .regs = {
+ .sid = {
+ .override = 0x768,
+ .security = 0x76c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1,
+ .name = "pva1rdb1",
+ .sid = TEGRA194_SID_PVA1,
+ .regs = {
+ .sid = {
+ .override = 0x770,
+ .security = 0x774,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE5R1,
+ .name = "pcie5r1",
+ .sid = TEGRA194_SID_PCIE5,
+ .regs = {
+ .sid = {
+ .override = 0x778,
+ .security = 0x77c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1,
+ .name = "nvencsrd1",
+ .sid = TEGRA194_SID_NVENC,
+ .regs = {
+ .sid = {
+ .override = 0x780,
+ .security = 0x784,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1,
+ .name = "nvenc1srd1",
+ .sid = TEGRA194_SID_NVENC1,
+ .regs = {
+ .sid = {
+ .override = 0x788,
+ .security = 0x78c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_ISPRA1,
+ .name = "ispra1",
+ .sid = TEGRA194_SID_ISP,
+ .regs = {
+ .sid = {
+ .override = 0x790,
+ .security = 0x794,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_PCIE0R1,
+ .name = "pcie0r1",
+ .sid = TEGRA194_SID_PCIE0,
+ .regs = {
+ .sid = {
+ .override = 0x798,
+ .security = 0x79c,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD,
+ .name = "nvdec1srd",
+ .sid = TEGRA194_SID_NVDEC1,
+ .regs = {
+ .sid = {
+ .override = 0x7c8,
+ .security = 0x7cc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1,
+ .name = "nvdec1srd1",
+ .sid = TEGRA194_SID_NVDEC1,
+ .regs = {
+ .sid = {
+ .override = 0x7d0,
+ .security = 0x7d4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR,
+ .name = "nvdec1swr",
+ .sid = TEGRA194_SID_NVDEC1,
+ .regs = {
+ .sid = {
+ .override = 0x7d8,
+ .security = 0x7dc,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU5R,
+ .name = "miu5r",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x7e0,
+ .security = 0x7e4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU5W,
+ .name = "miu5w",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x7e8,
+ .security = 0x7ec,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU6R,
+ .name = "miu6r",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x7f0,
+ .security = 0x7f4,
+ },
+ },
+ }, {
+ .id = TEGRA194_MEMORY_CLIENT_MIU6W,
+ .name = "miu6w",
+ .sid = TEGRA194_SID_MIU,
+ .regs = {
+ .sid = {
+ .override = 0x7f8,
+ .security = 0x7fc,
+ },
+ },
+ },
+};
+
+const struct tegra_mc_soc tegra194_mc_soc = {
+ .num_clients = ARRAY_SIZE(tegra194_mc_clients),
+ .clients = tegra194_mc_clients,
+ .num_address_bits = 40,
+ .ops = &tegra186_mc_ops,
+};
diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index da8a0da8da79..c3462dbc8c22 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -776,10 +776,6 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc)
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
- if (!emc->debugfs.root) {
- dev_err(emc->dev, "failed to create debugfs directory\n");
- return;
- }
debugfs_create_file("available_rates", 0444, emc->debugfs.root,
emc, &tegra_emc_debug_available_rates_fops);
@@ -908,49 +904,6 @@ err_msg:
return err;
}
-static int tegra_emc_opp_table_init(struct tegra_emc *emc)
-{
- u32 hw_version = BIT(tegra_sku_info.soc_process_id);
- struct opp_table *hw_opp_table;
- int err;
-
- hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
- err = PTR_ERR_OR_ZERO(hw_opp_table);
- if (err) {
- dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
- return err;
- }
-
- err = dev_pm_opp_of_add_table(emc->dev);
- if (err) {
- if (err == -ENODEV)
- dev_err(emc->dev, "OPP table not found, please update your device tree\n");
- else
- dev_err(emc->dev, "failed to add OPP table: %d\n", err);
-
- goto put_hw_table;
- }
-
- dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
- hw_version, clk_get_rate(emc->clk) / 1000000);
-
- /* first dummy rate-set initializes voltage state */
- err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
- if (err) {
- dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
- goto remove_table;
- }
-
- return 0;
-
-remove_table:
- dev_pm_opp_of_remove_table(emc->dev);
-put_hw_table:
- dev_pm_opp_put_supported_hw(hw_opp_table);
-
- return err;
-}
-
static void devm_tegra_emc_unset_callback(void *data)
{
tegra20_clk_set_emc_round_callback(NULL, NULL);
@@ -1077,6 +1030,7 @@ static int tegra_emc_devfreq_init(struct tegra_emc *emc)
static int tegra_emc_probe(struct platform_device *pdev)
{
+ struct tegra_core_opp_params opp_params = {};
struct device_node *np;
struct tegra_emc *emc;
int irq, err;
@@ -1122,7 +1076,9 @@ static int tegra_emc_probe(struct platform_device *pdev)
if (err)
return err;
- err = tegra_emc_opp_table_init(emc);
+ opp_params.init_state = true;
+
+ err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params);
if (err)
return err;
diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c
index 2db68a913b7a..fcd7738fcb53 100644
--- a/drivers/memory/tegra/tegra20.c
+++ b/drivers/memory/tegra/tegra20.c
@@ -679,7 +679,7 @@ static int tegra20_mc_stats_show(struct seq_file *s, void *unused)
return 0;
}
-static int tegra20_mc_init(struct tegra_mc *mc)
+static int tegra20_mc_probe(struct tegra_mc *mc)
{
debugfs_create_devm_seqfile(mc->dev, "stats", mc->debugfs.root,
tegra20_mc_stats_show);
@@ -687,6 +687,112 @@ static int tegra20_mc_init(struct tegra_mc *mc)
return 0;
}
+static int tegra20_mc_suspend(struct tegra_mc *mc)
+{
+ int err;
+
+ if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
+ err = tegra_gart_suspend(mc->gart);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int tegra20_mc_resume(struct tegra_mc *mc)
+{
+ int err;
+
+ if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
+ err = tegra_gart_resume(mc->gart);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static irqreturn_t tegra20_mc_handle_irq(int irq, void *data)
+{
+ struct tegra_mc *mc = data;
+ unsigned long status;
+ unsigned int bit;
+
+ /* mask all interrupts to avoid flooding */
+ status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
+ if (!status)
+ return IRQ_NONE;
+
+ for_each_set_bit(bit, &status, 32) {
+ const char *error = tegra_mc_status_names[bit];
+ const char *direction = "read", *secure = "";
+ const char *client, *desc;
+ phys_addr_t addr;
+ u32 value, reg;
+ u8 id, type;
+
+ switch (BIT(bit)) {
+ case MC_INT_DECERR_EMEM:
+ reg = MC_DECERR_EMEM_OTHERS_STATUS;
+ value = mc_readl(mc, reg);
+
+ id = value & mc->soc->client_id_mask;
+ desc = tegra_mc_error_names[2];
+
+ if (value & BIT(31))
+ direction = "write";
+ break;
+
+ case MC_INT_INVALID_GART_PAGE:
+ reg = MC_GART_ERROR_REQ;
+ value = mc_readl(mc, reg);
+
+ id = (value >> 1) & mc->soc->client_id_mask;
+ desc = tegra_mc_error_names[2];
+
+ if (value & BIT(0))
+ direction = "write";
+ break;
+
+ case MC_INT_SECURITY_VIOLATION:
+ reg = MC_SECURITY_VIOLATION_STATUS;
+ value = mc_readl(mc, reg);
+
+ id = value & mc->soc->client_id_mask;
+ type = (value & BIT(30)) ? 4 : 3;
+ desc = tegra_mc_error_names[type];
+ secure = "secure ";
+
+ if (value & BIT(31))
+ direction = "write";
+ break;
+
+ default:
+ continue;
+ }
+
+ client = mc->soc->clients[id].name;
+ addr = mc_readl(mc, reg + sizeof(u32));
+
+ dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
+ client, secure, direction, &addr, error,
+ desc);
+ }
+
+ /* clear interrupts */
+ mc_writel(mc, status, MC_INTSTATUS);
+
+ return IRQ_HANDLED;
+}
+
+static const struct tegra_mc_ops tegra20_mc_ops = {
+ .probe = tegra20_mc_probe,
+ .suspend = tegra20_mc_suspend,
+ .resume = tegra20_mc_resume,
+ .handle_irq = tegra20_mc_handle_irq,
+};
+
const struct tegra_mc_soc tegra20_mc_soc = {
.clients = tegra20_mc_clients,
.num_clients = ARRAY_SIZE(tegra20_mc_clients),
@@ -698,5 +804,5 @@ const struct tegra_mc_soc tegra20_mc_soc = {
.resets = tegra20_mc_resets,
.num_resets = ARRAY_SIZE(tegra20_mc_resets),
.icc_ops = &tegra20_mc_icc_ops,
- .init = tegra20_mc_init,
+ .ops = &tegra20_mc_ops,
};
diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c
index 5f224796e32e..06c0f17fa429 100644
--- a/drivers/memory/tegra/tegra210-emc-core.c
+++ b/drivers/memory/tegra/tegra210-emc-core.c
@@ -1759,10 +1759,6 @@ static void tegra210_emc_debugfs_init(struct tegra210_emc *emc)
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
- if (!emc->debugfs.root) {
- dev_err(dev, "failed to create debugfs directory\n");
- return;
- }
debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
&tegra210_emc_debug_available_rates_fops);
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index b3bbc5a05ba1..8ab6498dbe7d 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -16,1005 +16,1149 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 1,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 2,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 3,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 4,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 5,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 6,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x228,
- .bit = 14,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x2e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x2e,
+ },
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x228,
- .bit = 15,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 16,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 17,
- },
- .la = {
- .reg = 0x2fc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2fc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x228,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 0,
- .mask = 0xff,
- .def = 0x24,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x24,
+ },
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 22,
- },
- .la = {
- .reg = 0x310,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 23,
- },
- .la = {
- .reg = 0x310,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x1c,
.name = "nvencsrd",
.swgroup = TEGRA_SWGROUP_NVENC,
- .smmu = {
- .reg = 0x228,
- .bit = 28,
- },
- .la = {
- .reg = 0x328,
- .shift = 0,
- .mask = 0xff,
- .def = 0x23,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x23,
+ },
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 29,
- },
- .la = {
- .reg = 0x344,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 30,
- },
- .la = {
- .reg = 0x344,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x228,
- .bit = 31,
- },
- .la = {
- .reg = 0x350,
- .shift = 0,
- .mask = 0xff,
- .def = 0x65,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x65,
+ },
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x2b,
.name = "nvencswr",
.swgroup = TEGRA_SWGROUP_NVENC,
- .smmu = {
- .reg = 0x22c,
- .bit = 11,
- },
- .la = {
- .reg = 0x328,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x22c,
- .bit = 17,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x22c,
- .bit = 18,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x22c,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x22c,
- .bit = 22,
- },
- .la = {
- .reg = 0x314,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x314,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 27,
- },
- .la = {
- .reg = 0x348,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 28,
- },
- .la = {
- .reg = 0x348,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x22c,
- .bit = 29,
- },
- .la = {
- .reg = 0x350,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x44,
.name = "ispra",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 4,
- },
- .la = {
- .reg = 0x370,
- .shift = 0,
- .mask = 0xff,
- .def = 0x18,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x370,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x18,
+ },
},
}, {
.id = 0x46,
.name = "ispwa",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 6,
- },
- .la = {
- .reg = 0x374,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x374,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x47,
.name = "ispwb",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 7,
- },
- .la = {
- .reg = 0x374,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x374,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 10,
- },
- .la = {
- .reg = 0x37c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x7a,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x7a,
+ },
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 11,
- },
- .la = {
- .reg = 0x37c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 12,
- },
- .la = {
- .reg = 0x380,
- .shift = 0,
- .mask = 0xff,
- .def = 0x39,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x39,
+ },
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 13,
- },
- .la = {
- .reg = 0x380,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4e,
.name = "isprab",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 14,
- },
- .la = {
- .reg = 0x384,
- .shift = 0,
- .mask = 0xff,
- .def = 0x18,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x384,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x18,
+ },
},
}, {
.id = 0x50,
.name = "ispwab",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 16,
- },
- .la = {
- .reg = 0x388,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x51,
.name = "ispwbb",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 17,
- },
- .la = {
- .reg = 0x388,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 20,
- },
- .la = {
- .reg = 0x390,
- .shift = 0,
- .mask = 0xff,
- .def = 0x9b,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x9b,
+ },
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 21,
- },
- .la = {
- .reg = 0x390,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x56,
.name = "a9avpscr",
.swgroup = TEGRA_SWGROUP_A9AVP,
- .smmu = {
- .reg = 0x230,
- .bit = 22,
- },
- .la = {
- .reg = 0x3a4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x3a4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x57,
.name = "a9avpscw",
.swgroup = TEGRA_SWGROUP_A9AVP,
- .smmu = {
- .reg = 0x230,
- .bit = 23,
- },
- .la = {
- .reg = 0x3a4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x3a4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x58,
.name = "gpusrd",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0x230,
- .bit = 24,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0x230,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x59,
.name = "gpuswr",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0x230,
- .bit = 25,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0x230,
+ .bit = 25,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x5a,
.name = "displayt",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x230,
- .bit = 26,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x60,
.name = "sdmmcra",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
- .smmu = {
- .reg = 0x234,
- .bit = 0,
- },
- .la = {
- .reg = 0x3b8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x3b8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x61,
.name = "sdmmcraa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
- .smmu = {
- .reg = 0x234,
- .bit = 1,
- },
- .la = {
- .reg = 0x3bc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x5a,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x3bc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x5a,
+ },
},
}, {
.id = 0x62,
.name = "sdmmcr",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
- .smmu = {
- .reg = 0x234,
- .bit = 2,
- },
- .la = {
- .reg = 0x3c0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x3c0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x63,
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.name = "sdmmcrab",
- .smmu = {
- .reg = 0x234,
- .bit = 3,
- },
- .la = {
- .reg = 0x3c4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x5a,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x3c4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x5a,
+ },
},
}, {
.id = 0x64,
.name = "sdmmcwa",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
- .smmu = {
- .reg = 0x234,
- .bit = 4,
- },
- .la = {
- .reg = 0x3b8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x3b8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x65,
.name = "sdmmcwaa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
- .smmu = {
- .reg = 0x234,
- .bit = 5,
- },
- .la = {
- .reg = 0x3bc,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x3bc,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x66,
.name = "sdmmcw",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
- .smmu = {
- .reg = 0x234,
- .bit = 6,
- },
- .la = {
- .reg = 0x3c0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x3c0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x67,
.name = "sdmmcwab",
.swgroup = TEGRA_SWGROUP_SDMMC4A,
- .smmu = {
- .reg = 0x234,
- .bit = 7,
- },
- .la = {
- .reg = 0x3c4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x3c4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x6c,
.name = "vicsrd",
.swgroup = TEGRA_SWGROUP_VIC,
- .smmu = {
- .reg = 0x234,
- .bit = 12,
- },
- .la = {
- .reg = 0x394,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x394,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x6d,
.name = "vicswr",
.swgroup = TEGRA_SWGROUP_VIC,
- .smmu = {
- .reg = 0x234,
- .bit = 13,
- },
- .la = {
- .reg = 0x394,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x394,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x72,
.name = "viw",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x234,
- .bit = 18,
- },
- .la = {
- .reg = 0x398,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x398,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x73,
.name = "displayd",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x234,
- .bit = 19,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x78,
.name = "nvdecsrd",
.swgroup = TEGRA_SWGROUP_NVDEC,
- .smmu = {
- .reg = 0x234,
- .bit = 24,
- },
- .la = {
- .reg = 0x3d8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x23,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x3d8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x23,
+ },
},
}, {
.id = 0x79,
.name = "nvdecswr",
.swgroup = TEGRA_SWGROUP_NVDEC,
- .smmu = {
- .reg = 0x234,
- .bit = 25,
- },
- .la = {
- .reg = 0x3d8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 25,
+ },
+ .la = {
+ .reg = 0x3d8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x7a,
.name = "aper",
.swgroup = TEGRA_SWGROUP_APE,
- .smmu = {
- .reg = 0x234,
- .bit = 26,
- },
- .la = {
- .reg = 0x3dc,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x3dc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x7b,
.name = "apew",
.swgroup = TEGRA_SWGROUP_APE,
- .smmu = {
- .reg = 0x234,
- .bit = 27,
- },
- .la = {
- .reg = 0x3dc,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x3dc,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x7e,
.name = "nvjpgsrd",
.swgroup = TEGRA_SWGROUP_NVJPG,
- .smmu = {
- .reg = 0x234,
- .bit = 30,
- },
- .la = {
- .reg = 0x3e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x23,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x3e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x23,
+ },
},
}, {
.id = 0x7f,
.name = "nvjpgswr",
.swgroup = TEGRA_SWGROUP_NVJPG,
- .smmu = {
- .reg = 0x234,
- .bit = 31,
- },
- .la = {
- .reg = 0x3e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x3e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x80,
.name = "sesrd",
.swgroup = TEGRA_SWGROUP_SE,
- .smmu = {
- .reg = 0xb98,
- .bit = 0,
- },
- .la = {
- .reg = 0x3e0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x2e,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x3e0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x2e,
+ },
},
}, {
.id = 0x81,
.name = "seswr",
.swgroup = TEGRA_SWGROUP_SE,
- .smmu = {
- .reg = 0xb98,
- .bit = 1,
- },
- .la = {
- .reg = 0x3e0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x3e0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x82,
.name = "axiapr",
.swgroup = TEGRA_SWGROUP_AXIAP,
- .smmu = {
- .reg = 0xb98,
- .bit = 2,
- },
- .la = {
- .reg = 0x3a0,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x3a0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x83,
.name = "axiapw",
.swgroup = TEGRA_SWGROUP_AXIAP,
- .smmu = {
- .reg = 0xb98,
- .bit = 3,
- },
- .la = {
- .reg = 0x3a0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x3a0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x84,
.name = "etrr",
.swgroup = TEGRA_SWGROUP_ETR,
- .smmu = {
- .reg = 0xb98,
- .bit = 4,
- },
- .la = {
- .reg = 0x3ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x3ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x85,
.name = "etrw",
.swgroup = TEGRA_SWGROUP_ETR,
- .smmu = {
- .reg = 0xb98,
- .bit = 5,
- },
- .la = {
- .reg = 0x3ec,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x3ec,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x86,
.name = "tsecsrdb",
.swgroup = TEGRA_SWGROUP_TSECB,
- .smmu = {
- .reg = 0xb98,
- .bit = 6,
- },
- .la = {
- .reg = 0x3f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x9b,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x3f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x9b,
+ },
},
}, {
.id = 0x87,
.name = "tsecswrb",
.swgroup = TEGRA_SWGROUP_TSECB,
- .smmu = {
- .reg = 0xb98,
- .bit = 7,
- },
- .la = {
- .reg = 0x3f0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x3f0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x88,
.name = "gpusrd2",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0xb98,
- .bit = 8,
- },
- .la = {
- .reg = 0x3e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0xb98,
+ .bit = 8,
+ },
+ .la = {
+ .reg = 0x3e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x89,
.name = "gpuswr2",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0xb98,
- .bit = 9,
- },
- .la = {
- .reg = 0x3e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0xb98,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x3e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
},
};
@@ -1142,4 +1286,5 @@ const struct tegra_mc_soc tegra210_mc_soc = {
.reset_ops = &tegra_mc_reset_ops_common,
.resets = tegra210_mc_resets,
.num_resets = ARRAY_SIZE(tegra210_mc_resets),
+ .ops = &tegra30_mc_ops,
};
diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c
index 829f6d673c96..7e21a852f2e1 100644
--- a/drivers/memory/tegra/tegra30-emc.c
+++ b/drivers/memory/tegra/tegra30-emc.c
@@ -150,8 +150,8 @@
#define EMC_SELF_REF_CMD_ENABLED BIT(0)
#define DRAM_DEV_SEL_ALL (0 << 30)
-#define DRAM_DEV_SEL_0 (2 << 30)
-#define DRAM_DEV_SEL_1 (1 << 30)
+#define DRAM_DEV_SEL_0 BIT(31)
+#define DRAM_DEV_SEL_1 BIT(30)
#define DRAM_BROADCAST(num) \
((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
@@ -1354,10 +1354,6 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc)
}
emc->debugfs.root = debugfs_create_dir("emc", NULL);
- if (!emc->debugfs.root) {
- dev_err(emc->dev, "failed to create debugfs directory\n");
- return;
- }
debugfs_create_file("available_rates", 0444, emc->debugfs.root,
emc, &tegra_emc_debug_available_rates_fops);
@@ -1480,49 +1476,6 @@ err_msg:
return err;
}
-static int tegra_emc_opp_table_init(struct tegra_emc *emc)
-{
- u32 hw_version = BIT(tegra_sku_info.soc_speedo_id);
- struct opp_table *hw_opp_table;
- int err;
-
- hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1);
- err = PTR_ERR_OR_ZERO(hw_opp_table);
- if (err) {
- dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err);
- return err;
- }
-
- err = dev_pm_opp_of_add_table(emc->dev);
- if (err) {
- if (err == -ENODEV)
- dev_err(emc->dev, "OPP table not found, please update your device tree\n");
- else
- dev_err(emc->dev, "failed to add OPP table: %d\n", err);
-
- goto put_hw_table;
- }
-
- dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n",
- hw_version, clk_get_rate(emc->clk) / 1000000);
-
- /* first dummy rate-set initializes voltage state */
- err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk));
- if (err) {
- dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err);
- goto remove_table;
- }
-
- return 0;
-
-remove_table:
- dev_pm_opp_of_remove_table(emc->dev);
-put_hw_table:
- dev_pm_opp_put_supported_hw(hw_opp_table);
-
- return err;
-}
-
static void devm_tegra_emc_unset_callback(void *data)
{
tegra20_clk_set_emc_round_callback(NULL, NULL);
@@ -1568,6 +1521,7 @@ static int tegra_emc_init_clk(struct tegra_emc *emc)
static int tegra_emc_probe(struct platform_device *pdev)
{
+ struct tegra_core_opp_params opp_params = {};
struct device_node *np;
struct tegra_emc *emc;
int err;
@@ -1617,7 +1571,9 @@ static int tegra_emc_probe(struct platform_device *pdev)
if (err)
return err;
- err = tegra_emc_opp_table_init(emc);
+ opp_params.init_state = true;
+
+ err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params);
if (err)
return err;
diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c
index ea849003014b..84316357513d 100644
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c
@@ -37,970 +37,1102 @@ static const struct tegra_mc_client tegra30_mc_clients[] = {
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
- .la = {
- .reg = 0x34c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0,
+ .regs = {
+ .la = {
+ .reg = 0x34c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 1,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 2,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 3,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 4,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 5,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 6,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x07,
.name = "display1b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 7,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x08,
.name = "display1bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 8,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 8,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x09,
.name = "eppup",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x228,
- .bit = 9,
- },
- .la = {
- .reg = 0x300,
- .shift = 0,
- .mask = 0xff,
- .def = 0x17,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x300,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x17,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x0a,
.name = "g2pr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 10,
- },
- .la = {
- .reg = 0x308,
- .shift = 0,
- .mask = 0xff,
- .def = 0x09,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x308,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x09,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x0b,
.name = "g2sr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 11,
- },
- .la = {
- .reg = 0x308,
- .shift = 16,
- .mask = 0xff,
- .def = 0x09,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x308,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x09,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x0c,
.name = "mpeunifbr",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x228,
- .bit = 12,
- },
- .la = {
- .reg = 0x328,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x0d,
.name = "viruv",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x228,
- .bit = 13,
- },
- .la = {
- .reg = 0x364,
- .shift = 0,
- .mask = 0xff,
- .def = 0x2c,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x364,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x2c,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x228,
- .bit = 14,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x228,
- .bit = 15,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 16,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 17,
- },
- .la = {
- .reg = 0x2fc,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2fc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x12,
.name = "fdcdrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 18,
- },
- .la = {
- .reg = 0x334,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x334,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x13,
.name = "fdcdrd2",
.swgroup = TEGRA_SWGROUP_NV2,
- .smmu = {
- .reg = 0x228,
- .bit = 19,
- },
- .la = {
- .reg = 0x33c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x33c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x14,
.name = "g2dr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 20,
- },
- .la = {
- .reg = 0x30c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x30c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x228,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 22,
- },
- .la = {
- .reg = 0x310,
- .shift = 0,
- .mask = 0xff,
- .def = 0x05,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x05,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 23,
- },
- .la = {
- .reg = 0x310,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x18,
.name = "idxsrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 24,
- },
- .la = {
- .reg = 0x334,
- .shift = 16,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x334,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x19,
.name = "idxsrd2",
.swgroup = TEGRA_SWGROUP_NV2,
- .smmu = {
- .reg = 0x228,
- .bit = 25,
- },
- .la = {
- .reg = 0x33c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 25,
+ },
+ .la = {
+ .reg = 0x33c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x1a,
.name = "mpe_ipred",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x228,
- .bit = 26,
- },
- .la = {
- .reg = 0x328,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x1b,
.name = "mpeamemrd",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x228,
- .bit = 27,
- },
- .la = {
- .reg = 0x32c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x42,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x32c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x42,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x1c,
.name = "mpecsrd",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x228,
- .bit = 28,
- },
- .la = {
- .reg = 0x32c,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x32c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 29,
- },
- .la = {
- .reg = 0x344,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 30,
- },
- .la = {
- .reg = 0x344,
- .shift = 16,
- .mask = 0xff,
- .def = 0x12,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x12,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x228,
- .bit = 31,
- },
- .la = {
- .reg = 0x350,
- .shift = 0,
- .mask = 0xff,
- .def = 0x33,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x33,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x20,
.name = "texsrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 0,
- },
- .la = {
- .reg = 0x338,
- .shift = 0,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x338,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x21,
.name = "texsrd2",
.swgroup = TEGRA_SWGROUP_NV2,
- .smmu = {
- .reg = 0x22c,
- .bit = 1,
- },
- .la = {
- .reg = 0x340,
- .shift = 0,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x340,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 2,
- },
- .la = {
- .reg = 0x354,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 3,
- },
- .la = {
- .reg = 0x354,
- .shift = 16,
- .mask = 0xff,
- .def = 0xd0,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xd0,
+ },
},
.fifo_size = 16 * 4,
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 4,
- },
- .la = {
- .reg = 0x358,
- .shift = 0,
- .mask = 0xff,
- .def = 0x2a,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x2a,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 5,
- },
- .la = {
- .reg = 0x358,
- .shift = 16,
- .mask = 0xff,
- .def = 0x74,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x74,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
.fifo_size = 16 * 14,
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
.fifo_size = 16 * 14,
}, {
.id = 0x28,
.name = "eppu",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 8,
- },
- .la = {
- .reg = 0x300,
- .shift = 16,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 8,
+ },
+ .la = {
+ .reg = 0x300,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x29,
.name = "eppv",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 9,
- },
- .la = {
- .reg = 0x304,
- .shift = 0,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x304,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2a,
.name = "eppy",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 10,
- },
- .la = {
- .reg = 0x304,
- .shift = 16,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x304,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2b,
.name = "mpeunifbw",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x22c,
- .bit = 11,
- },
- .la = {
- .reg = 0x330,
- .shift = 0,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x330,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x2c,
.name = "viwsb",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 12,
- },
- .la = {
- .reg = 0x364,
- .shift = 16,
- .mask = 0xff,
- .def = 0x12,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x364,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x12,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2d,
.name = "viwu",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 13,
- },
- .la = {
- .reg = 0x368,
- .shift = 0,
- .mask = 0xff,
- .def = 0xb2,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x368,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xb2,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2e,
.name = "viwv",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 14,
- },
- .la = {
- .reg = 0x368,
- .shift = 16,
- .mask = 0xff,
- .def = 0xb2,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x368,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xb2,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2f,
.name = "viwy",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 15,
- },
- .la = {
- .reg = 0x36c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x12,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x36c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x12,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x30,
.name = "g2dw",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x22c,
- .bit = 16,
- },
- .la = {
- .reg = 0x30c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x9,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x30c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x9,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x22c,
- .bit = 17,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x22c,
- .bit = 18,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x33,
.name = "fdcdwr",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 19,
- },
- .la = {
- .reg = 0x338,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x338,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x34,
.name = "fdcdwr2",
.swgroup = TEGRA_SWGROUP_NV2,
- .smmu = {
- .reg = 0x22c,
- .bit = 20,
- },
- .la = {
- .reg = 0x340,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x340,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x22c,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x22c,
- .bit = 22,
- },
- .la = {
- .reg = 0x314,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x314,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x37,
.name = "ispw",
.swgroup = TEGRA_SWGROUP_ISP,
- .smmu = {
- .reg = 0x22c,
- .bit = 23,
- },
- .la = {
- .reg = 0x31c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x31c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
.fifo_size = 16 * 24,
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
.fifo_size = 16 * 24,
}, {
.id = 0x3a,
.name = "mpecswr",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x22c,
- .bit = 26,
- },
- .la = {
- .reg = 0x330,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x330,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 27,
- },
- .la = {
- .reg = 0x348,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 28,
- },
- .la = {
- .reg = 0x348,
- .shift = 16,
- .mask = 0xff,
- .def = 0x06,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x06,
+ },
},
.fifo_size = 16 * 4,
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x22c,
- .bit = 29,
- },
- .la = {
- .reg = 0x350,
- .shift = 16,
- .mask = 0xff,
- .def = 0x33,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x33,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 30,
- },
- .la = {
- .reg = 0x35c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 4,
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 31,
- },
- .la = {
- .reg = 0x35c,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 0,
- },
- .la = {
- .reg = 0x360,
- .shift = 0,
- .mask = 0xff,
- .def = 0x42,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x42,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 1,
- },
- .la = {
- .reg = 0x360,
- .shift = 16,
- .mask = 0xff,
- .def = 0x2a,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x2a,
+ },
},
.fifo_size = 16 * 16,
},
@@ -1089,7 +1221,6 @@ static void tegra30_mc_tune_client_latency(struct tegra_mc *mc,
unsigned int bandwidth_mbytes_sec)
{
u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;
- const struct tegra_mc_la *la = &client->la;
unsigned int fifo_size = client->fifo_size;
u32 arb_nsec, la_ticks, value;
@@ -1149,12 +1280,12 @@ static void tegra30_mc_tune_client_latency(struct tegra_mc *mc,
* request.
*/
la_ticks = arb_nsec / mc->tick;
- la_ticks = min(la_ticks, la->mask);
+ la_ticks = min(la_ticks, client->regs.la.mask);
- value = mc_readl(mc, la->reg);
- value &= ~(la->mask << la->shift);
- value |= la_ticks << la->shift;
- mc_writel(mc, value, la->reg);
+ value = mc_readl(mc, client->regs.la.reg);
+ value &= ~(client->regs.la.mask << client->regs.la.shift);
+ value |= la_ticks << client->regs.la.shift;
+ mc_writel(mc, value, client->regs.la.reg);
}
static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst)
@@ -1268,4 +1399,5 @@ const struct tegra_mc_soc tegra30_mc_soc = {
.resets = tegra30_mc_resets,
.num_resets = ARRAY_SIZE(tegra30_mc_resets),
.icc_ops = &tegra30_mc_icc_ops,
+ .ops = &tegra30_mc_ops,
};
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-24 01:52:07 +0300