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| author | Ben Skeggs <bskeggs@redhat.com> | 2012-09-26 06:43:10 +0400 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-09-26 06:43:10 +0400 |
| commit | 79eee7aa0d4de5a42331c63d3c7c735248b53d0c (patch) | |
| tree | 6c5cd081e1d2181d4f9ef3ac33481e3e049ec80a /drivers/gpu | |
| parent | c7ead11d0b498984169871fd03c57441862ec3f3 (diff) | |
| download | linux-79eee7aa0d4de5a42331c63d3c7c735248b53d0c.tar.xz | |
drm/nvc0/ltcg: mask off intr 0x10
NVIDIA do that at startup too on Fermi, so perhaps the heap of 0x10
intrs we receive are normal and we can ignore them.
On Kepler NVIDIA *don't* do this, but the hardware appears to come up
with the bit masked off by default - so that's probably why :)
This should silence some interrupt spam seen on Fermi+ boards.
Backported patch from reworked nouveau kernel tree.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_fb.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_fb.c b/drivers/gpu/drm/nouveau/nvc0_fb.c index f704e942372e..f376c39310df 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fb.c +++ b/drivers/gpu/drm/nouveau/nvc0_fb.c @@ -124,6 +124,7 @@ nvc0_fb_init(struct drm_device *dev) priv = dev_priv->engine.fb.priv; nv_wr32(dev, 0x100c10, priv->r100c10 >> 8); + nv_mask(dev, 0x17e820, 0x00100000, 0x00000000); /* NV_PLTCG_INTR_EN */ return 0; } |