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author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-09-25 23:24:29 +0400 |
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committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2015-03-24 14:50:55 +0300 |
commit | 7cb0d6c17b96b8bf3c25de2dfde4fdeb9191f4c3 (patch) | |
tree | 941dfbd181591b7f3ea22a585d05e8d462b40fbf /drivers/gpu/drm/omapdrm/omap_gem.c | |
parent | 2dab0bab6b749590086d44a04f9debc4fe894fd6 (diff) | |
download | linux-7cb0d6c17b96b8bf3c25de2dfde4fdeb9191f4c3.tar.xz |
drm/omap: fix TILER on OMAP5
On OMAP5 it is not possible to use TILER buffer with CPU when caching or
write-combining is used. Doing so leads to errors from the memory
manager.
However, on OMAP4, write-combining works fine.
This patch adds platform specific data for the TILER, and a function
tiler_get_cpu_cache_flags() which can be used to get the caching mode to
be used.
Note that without write-combining the use of the TILER buffer with CPU
is unusably slow. It's still good to have it operational for testing
purposes.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm/omap_gem.c')
-rw-r--r-- | drivers/gpu/drm/omapdrm/omap_gem.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c b/drivers/gpu/drm/omapdrm/omap_gem.c index 9b250c93b046..d37ee756a0b1 100644 --- a/drivers/gpu/drm/omapdrm/omap_gem.c +++ b/drivers/gpu/drm/omapdrm/omap_gem.c @@ -1359,8 +1359,8 @@ struct drm_gem_object *omap_gem_new(struct drm_device *dev, /* currently don't allow cached buffers.. there is some caching * stuff that needs to be handled better */ - flags &= ~(OMAP_BO_CACHED|OMAP_BO_UNCACHED); - flags |= OMAP_BO_WC; + flags &= ~(OMAP_BO_CACHED|OMAP_BO_WC|OMAP_BO_UNCACHED); + flags |= tiler_get_cpu_cache_flags(); /* align dimensions to slot boundaries... */ tiler_align(gem2fmt(flags), |