diff options
| author | Ben Skeggs <bskeggs@redhat.com> | 2012-01-17 15:10:58 +0400 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2012-03-13 11:08:03 +0400 |
| commit | fd99fd6100d3b7aaa8dc76888a38bbb15e8041bc (patch) | |
| tree | 5bda24f2755bde247eb1e3a8ae143632351130ff /drivers/gpu/drm/nouveau/nouveau_pm.h | |
| parent | 68a64cad07057c3395b3b18c282df884e87ff3d6 (diff) | |
| download | linux-fd99fd6100d3b7aaa8dc76888a38bbb15e8041bc.tar.xz | |
drm/nouveau/pm: calculate memory timings at perflvl creation time
Statically generating the PFB register and MR values for each timing set
turns out to be insufficient. There's at least one (so far) known piece
of information which effects MR values which is stored in the perflvl
entry on some chipsets (and in another table on later ones), which is
disconnected from the timing table entries.
After this change we will generate a timing set based on an input clock
frequency instead, and have this data stored in the performance level
data.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_pm.h')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_pm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h index 2f8e14fbcff8..9e7ad33aa091 100644 --- a/drivers/gpu/drm/nouveau/nouveau_pm.h +++ b/drivers/gpu/drm/nouveau/nouveau_pm.h @@ -41,6 +41,7 @@ int nouveau_voltage_gpio_set(struct drm_device *, int voltage); /* nouveau_perf.c */ void nouveau_perf_init(struct drm_device *); void nouveau_perf_fini(struct drm_device *); +u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len); /* nouveau_mem.c */ void nouveau_mem_timing_init(struct drm_device *); |