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| author | Mahesh Kumar <mahesh1.kumar@intel.com> | 2018-05-17 16:26:26 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2018-06-07 11:39:15 +0300 |
| commit | 197af5f2131101f9a6118b238901cb1988f5d7f9 (patch) | |
| tree | 39ff12cd1c9f7ba3f7552d5865b214119ba1cbea /drivers/gpu/drm/i915/gvt/handlers.c | |
| parent | 2f08b23d70324bb0f592c71bd36cdc1d2f12face (diff) | |
| download | linux-197af5f2131101f9a6118b238901cb1988f5d7f9.tar.xz | |
drm/i915/icl: Don't update enabled dbuf slices struct until updated in hw
Do not update number of enabled dbuf slices in dev_priv struct until we
actually enable/disable dbuf slice in hw. This is leading to never
updating dbuf slices and resulting in DBuf slice mismatch warning.
Fixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when needed")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180517132626.5885-1-mahesh1.kumar@intel.com
(cherry picked from commit 6ceb7277173597eeed8d635e08db51e35235ab21)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/handlers.c')
0 files changed, 0 insertions, 0 deletions